DE10110151A1 - Verdrahtungssubstrat, Verfahren zum Herstellen desselben und elektronische Vorrichtung, die dasselbe verwendet - Google Patents
Verdrahtungssubstrat, Verfahren zum Herstellen desselben und elektronische Vorrichtung, die dasselbe verwendetInfo
- Publication number
- DE10110151A1 DE10110151A1 DE10110151A DE10110151A DE10110151A1 DE 10110151 A1 DE10110151 A1 DE 10110151A1 DE 10110151 A DE10110151 A DE 10110151A DE 10110151 A DE10110151 A DE 10110151A DE 10110151 A1 DE10110151 A1 DE 10110151A1
- Authority
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- Germany
- Prior art keywords
- wiring
- substrate
- pattern
- ceramic
- patterns
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- H05K2201/017—Glass ceramic coating, e.g. formed on inorganic substrate
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
- H05K2201/09909—Special local insulating pattern, e.g. as dam around component
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
- H05K3/4626—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials
- H05K3/4629—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials laminating inorganic sheets comprising printed circuits, e.g. green ceramic sheets
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Geometry (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Parts Printed On Printed Circuit Boards (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Abstract
Description
Claims (16)
Bilden eines Verdrahtungsmusters (4; 34; 43a-c) auf einem Substrat (1; 21; 31; 49); und
Bilden eines Isoliermusters (8; 28a, 28b; 35a, 35b; 48a-c) auf dem Substrat (1; 21; 31; 49), so daß das selbe das Verdrahtungsmuster (4; 34; 43a-c) schneidet und einen Teil des Verdrahtungsmusters (4; 34; 43a-c) für eine Anschlußbereichselektrode (7; 27; 37; 44-47) definiert.
Bilden mehrerer Verdrahtungsmuster (4; 34; 43a-c) auf dem Substrat (1; 21; 31; 49); und
Bilden des Isoliermuster (8; 28a, 28b; 35a, 35b; 48a-c), so daß es sich über die mehreren Verdrahtungsmus ter (4; 34; 43a-c) erstreckt.
Bilden des Verdrahtungsmusters (4; 34; 43a-c) auf ei nem keramischen Substrat (1; 21; 31; 49); und
Bilden eines Musters, das Keramik als eine Hauptkompo nente enthält, als das Isoliermuster (8; 28a, 28b; 35a, 35b; 48a-c).
Bilden des Verdrahtungsmusters (4; 34; 43a-c) auf ei ner keramischen Grünschicht;
Bilden des Isoliermusters (8; 28a, 28b; 35a, 35b; 48a-c) auf der keramischen Grünschicht;
Durchführen eines Druck-Verbindens der keramischen Grünschicht zusammen mit anderen keramischen Grün schichten, um einen Druck-Verbund-Körper zu bilden; und
Brennen des Druck-Verbund-Körpers.
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE10164879A DE10164879B4 (de) | 2000-03-02 | 2001-03-02 | Verdrahtungssubstrat |
DE10164880A DE10164880B4 (de) | 2000-03-02 | 2001-03-02 | Verdrahtungssubstrat, Verfahren zum Herstellen desselben und elektronische Vorrichtung, die dasselbe verwendet |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2000057475 | 2000-03-02 | ||
JP00-057475 | 2000-03-02 | ||
JP2000354130A JP2001320168A (ja) | 2000-03-02 | 2000-11-21 | 配線基板およびその製造方法、ならびにそれを用いた電子装置 |
JP00-354130 | 2000-11-21 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE10110151A1 true DE10110151A1 (de) | 2001-09-20 |
DE10110151B4 DE10110151B4 (de) | 2006-08-17 |
Family
ID=26586628
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE10110151A Expired - Lifetime DE10110151B4 (de) | 2000-03-02 | 2001-03-02 | Verdrahtungssubstrat, Verfahren zum Herstellen desselben und elektronische Vorrichtung, die dasselbe verwendet |
Country Status (5)
Country | Link |
---|---|
US (1) | US7009114B2 (de) |
JP (1) | JP2001320168A (de) |
DE (1) | DE10110151B4 (de) |
FR (1) | FR2807284A1 (de) |
GB (1) | GB2362038B (de) |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002026187A (ja) * | 2000-07-07 | 2002-01-25 | Sony Corp | 半導体パッケージ及び半導体パッケージの製造方法 |
TWI221343B (en) * | 2003-10-21 | 2004-09-21 | Advanced Semiconductor Eng | Wafer structure for preventing contamination of bond pads during SMT process and process for the same |
JP4432973B2 (ja) * | 2004-12-20 | 2010-03-17 | 株式会社村田製作所 | 積層セラミック電子部品の製造方法 |
JP2008172127A (ja) * | 2007-01-15 | 2008-07-24 | Alps Electric Co Ltd | 電子回路モジュール |
KR101473267B1 (ko) * | 2009-04-02 | 2014-12-16 | 가부시키가이샤 무라타 세이사쿠쇼 | 회로 기판 |
JP2011088756A (ja) * | 2009-10-20 | 2011-05-06 | Murata Mfg Co Ltd | 低温焼結セラミック材料、低温焼結セラミック焼結体および多層セラミック基板 |
JP5481724B2 (ja) * | 2009-12-24 | 2014-04-23 | 新光電気工業株式会社 | 半導体素子内蔵基板 |
JP5762376B2 (ja) | 2012-09-21 | 2015-08-12 | 日本特殊陶業株式会社 | 配線基板及びその製造方法 |
CN109923950B (zh) * | 2016-11-11 | 2021-09-21 | 株式会社村田制作所 | 陶瓷基板以及陶瓷基板的制造方法 |
JP7248038B2 (ja) * | 2018-12-06 | 2023-03-29 | 株式会社村田製作所 | モジュールおよびその製造方法 |
CN114731765A (zh) * | 2019-12-04 | 2022-07-08 | 索尼集团公司 | 电子部件安装基板、电子部件安装体、及其制造方法以及电子装置 |
Family Cites Families (18)
Publication number | Priority date | Publication date | Assignee | Title |
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JPS53147968A (en) * | 1977-05-30 | 1978-12-23 | Hitachi Ltd | Thick film circuit board |
US4976813A (en) | 1988-07-01 | 1990-12-11 | Amoco Corporation | Process for using a composition for a solder mask |
JPH0362688A (ja) * | 1990-03-29 | 1991-03-18 | Seiko Epson Corp | 液晶表示装置 |
US5667934A (en) * | 1990-10-09 | 1997-09-16 | International Business Machines Corporation | Thermally stable photoimaging composition |
JPH04196191A (ja) | 1990-11-26 | 1992-07-15 | Matsushita Electric Ind Co Ltd | プリント基板 |
JPH04354398A (ja) | 1991-05-31 | 1992-12-08 | Internatl Business Mach Corp <Ibm> | 配線基板及びその製造方法 |
JP2702839B2 (ja) | 1991-11-20 | 1998-01-26 | シャープ株式会社 | 配線基板の電極構造 |
JPH0661368A (ja) | 1992-08-05 | 1994-03-04 | Nec Corp | フリップチップ型半導体装置 |
US5265792A (en) | 1992-08-20 | 1993-11-30 | Hewlett-Packard Company | Light source and technique for mounting light emitting diodes |
JPH09162688A (ja) | 1995-12-11 | 1997-06-20 | Matsushita Electric Ind Co Ltd | 弾性表面波装置 |
JP3495203B2 (ja) * | 1996-09-30 | 2004-02-09 | 京セラ株式会社 | 回路基板の製造方法 |
US5910334A (en) * | 1997-12-16 | 1999-06-08 | Delco Electronics Corporation | Method of manufacture for a thick film multi-layer circuit |
JPH11251723A (ja) * | 1998-02-26 | 1999-09-17 | Kyocera Corp | 回路基板 |
US6492251B1 (en) * | 1999-03-10 | 2002-12-10 | Tessera, Inc. | Microelectronic joining processes with bonding material application |
US6531664B1 (en) * | 1999-04-05 | 2003-03-11 | Delphi Technologies, Inc. | Surface mount devices with solder |
US6542379B1 (en) * | 1999-07-15 | 2003-04-01 | International Business Machines Corporation | Circuitry with integrated passive components and method for producing |
DE19945914C1 (de) | 1999-09-24 | 2001-08-30 | Siemens Ag | Verfahren zur Erzeugung von präzisen Lötflächen auf einem Schaltungsträger, insbesondere Dünnfilm-Substrat |
TW533555B (en) * | 2001-11-21 | 2003-05-21 | Siliconware Precision Industries Co Ltd | Substrate for passive device |
-
2000
- 2000-11-21 JP JP2000354130A patent/JP2001320168A/ja active Pending
-
2001
- 2001-02-19 GB GB0104068A patent/GB2362038B/en not_active Expired - Lifetime
- 2001-02-21 US US09/789,454 patent/US7009114B2/en not_active Expired - Lifetime
- 2001-03-01 FR FR0102825A patent/FR2807284A1/fr not_active Withdrawn
- 2001-03-02 DE DE10110151A patent/DE10110151B4/de not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
US7009114B2 (en) | 2006-03-07 |
GB2362038A (en) | 2001-11-07 |
US20030011999A1 (en) | 2003-01-16 |
FR2807284A1 (fr) | 2001-10-05 |
GB0104068D0 (en) | 2001-04-04 |
JP2001320168A (ja) | 2001-11-16 |
GB2362038B (en) | 2002-04-03 |
DE10110151B4 (de) | 2006-08-17 |
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