CN85104551A - 在硅衬底上形成隔离硅区和场效应器件的工艺过程 - Google Patents

在硅衬底上形成隔离硅区和场效应器件的工艺过程 Download PDF

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CN85104551A
CN85104551A CN85104551.0A CN85104551A CN85104551A CN 85104551 A CN85104551 A CN 85104551A CN 85104551 A CN85104551 A CN 85104551A CN 85104551 A CN85104551 A CN 85104551A
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贝格
赵·H·挺
华泰礼
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Abstract

在一个类似外延层的硅层中形成MOS和CMOS晶体管的改进的工艺过程。先形成一些场氧化物区，接着再沉积一层多晶硅层或非晶硅层，这些硅层在这些场氧化物区之间形成“晶种窗”处同衬底接触。这些层由衬底通过晶种窗重新结晶。晶体管就造在这层重新结晶过的硅层中。

Description

在硅衬底上形成隔离硅区和场效应器件的工艺过程
本发明涉及MOS集成电路领域，尤其涉及在一块硅衬底上形成隔离硅区的有关问题。
在金属-氧化物-半导体（MOS）集成电路制造过程中，常常要采取步骤把一个器件同另一个器件从电气上隔离开，这样以消除或减小器件之间的寄生通路。例如，若把场效应晶体管不加隔离的制造在一块硅衬底上，这样，两个不同晶体管的源区或漏区就可能成为不需要的第三只晶体管。复盖在表面的相互连接，象安排在一个晶体管的源和另一晶体管的漏之间的铝线，起了栅极的作用而可能引起传导寄生。
在互补MOS（CMOS）集成电路中，寄生通路的问题甚至更大。这里，衬底，互补晶体管的n+区或p+区，以及用于形成一种导电型晶体管的井都可能相互一起形成一个不需要的晶体管，在这些不同区域之间的晶体管的作用可能导致产生一个破坏集成电路的寄生通路，这问题有时称作“latchup”。（闩锁）
现在有几种加工技术用来减少寄生传导，通常在相邻晶体管之间用场氧化物区来把一个晶体管的源同另一个晶体管的漏隔离开，这些较厚的氧化物区在相邻的晶体管之间提供了一个导电性差的通路（或更长的通路），而且复盖在上面的线离衬底的距离更大了，这样就降低了它们作为不需要的栅极的效率。对于CMOS电路，典型的从n+到p+的场氧化物是6微米宽，这样它耗掉的衬底面积，同制造这场效应管所需要的面积相比是相当大的，在另一些情况下，在衬底上形成一些沟，并用一种绝缘材料把这沟填满。尽管这项技术是有效的，分开的距离甚至小到1微米，但它需要更为复杂的工艺过程。
在CMOS器路中也用其他技术来防止闩锁，例如，在一块高度掺杂的衬底上生长出一外延层，再在这外延层上形成这些电路。在另一些电路中，在一个绝缘体上方，象在SOS（硅在兰宝石上一即兰宝石衬底）工艺中一样形成一层薄层。
现在这项发明提供一种与上述老技术不同的技术，根据此项发明，利用衬底的晶状结构，作为生长晶种在绝缘区上形成一种类似外延层的硅层。
用来由晶种形成类外延层的其他工艺过程都是熟知的，一般说来，这些老的工艺过程用一个晶种，而且不是在晶种窗上制造器件，衬底从电气上也不加入最后的电路，就申请人所知，以往的工艺中最近的技术是：（1）Electronic    Week，（电子周刊）1984年8月6日，第31页“Britain    Getting    Its    Act    Together    in    SoI    Technology    In    Bid    To    Get    Jump    OU    u.S    And    Japanese    chip    Makers;（2）Electronic    Week，（电子周刊）1984年8月6日，第32-33页，“cam-bride    Lab    Heats    Wafers    Top    and    Bottom”;（3）LED82，16、4，第433页-436页“Characterization    of    Laser-Sol    Double    Si    Active    Layers    By    Fabricating    Device    Structures”;（4）IEDM82，16、1第420-423页，“MOS    Trausistors    in    Bean-Recrystallized    Polysilicon”;（5）J.Elect-rochem.Soc.
（电化学协会会报）1981年9月，第1981页-1986页（128卷，第9期）“Single    Crystal    SilicoN-ON-Oxide    By    A    Scanning    CW    Laser    Induced    Lateral    Seeding    Process”;34、5，第808-811页，“Device    Performances    of    A    submicron    SoI    Technology”;以及（7）Journal    of    Crystal    Growth    63，63，（晶体生长杂志），1983年，第453-483页“Graphite-Strip-Heater-Zone-Melting    Recry-stallization    of    si    Films”。
叙述了一种在一块硅衬底上制造场效应器件的改进工艺过程，按这种工艺，用绝缘区来把这些器件彼此隔离开来。在衬底上形成了这些绝缘区，它们确定了这些区域之间开口的大小;这些区域为衬底提供了晶种窗。在这些绝缘区的上方形成一层硅（如，多晶硅或非晶硅硅），这层硅伸展到窗里面去，这层硅需经处理以使该衬底的结晶结构经过晶种窗长入这层硅里，硅层的这个重新结晶过程是经过这些窗口引入晶种的，重新结晶过的这层硅形成一个主晶层，在它里面或它上面制造场效应器件，而这些器件的沟道直接形成在晶种筒的上方。
图1是一部分硅衬底的横截面正视图，这一部分包括一个型井，一个二氧化硅层和氮化硅掩膜;
图2示出的是图1的衬底在氧化并去掉了氮化硅掩膜后的情况;
图3示出的是图2的衬底磨平后的情况;
图4示出的是图3的衬底，在它上面形成一层硅层后的情况;
图5示出的是图4的衬底，在衬底的结晶结构传入上面硅层后的情况;
图6示出的是图5的衬底在进行掺杂用以调整器件的阀值电压时的情况;
图7示出的是图6的衬底在另一掩膜步骤后的情况;
图8示出的是图7的衬底在加工处理了硅层以隔离两相邻晶体管区后的情况;
图9示出的是图8的衬底，在上面硅层中制造了CMOS晶体管后的情况;
图10是一个衬底的横截面正视图，它示出了本发明的另一种具体实现，这对制造CMOS反相器是特别有用的。
本发明叙述在一块硅衬底上形成隔离区和场效应器件的一种工艺过程。下面的说明提出了许多具体细节，以便本发明能被彻底了解。显然，对熟悉本专业的人来说，没有这些具体细节，也能实现这个工艺过程。而在另一些场合，大家所熟悉的那些工艺步骤就没有详细叙述，以便不会不必要地掩盖本发明。
图1-9举例说明了如何用本发明教给的方法制造互补MOS场效应器件（特别是场效应晶体管）。制造过程从一块通常的P型单晶硅衬底开始，它在图1中用10表示。用大家熟知的工艺过程，在衬底上产生一个供P沟道器件用的型井34。这个井可用n、磷或其他n型杂质掺杂。在衬底10的上表面沉积了一个象二氧化硅层这样的保护层12。用普通的掩膜和刻蚀工艺步骤形成氮化硅部分13。这些氮化硅部分彼此隔离，如图所示的那样，其中一个在井34的上方。这些氮化硅的宽度对于本发明并不关键;例如，它们可在1微米的量级或更小。
图1的衬底再经过一个高温氧化步骤，如通常所用的那样，以形成图2所示的场氧化物区14。（这一步骤也可用“打入”步骤形成井34）这个场氧化物区14的厚度，比方说可为6000A°。
尽管没有必要，但人们还是喜欢把图2的结构平面化，也就是说，利用一些步骤形成图3所示的平坦表面15，可以利用已知的加工工艺来实现这种平面化。要形成一个平面层，可在图2结构的上方形成一个聚异丁烯酸甲酯（硬有机玻璃）复盖层或者一个层。然后再对这平面进行反应性的离子刻蚀，它在这层和场氧化物区14之间的选择为1-1。图2的场氧化物区的厚度减小了，它作为场氧化物区14a示于图3。
现在用氟氢酸洗把场氧化物区14a之间的硅衬底暴露出来，跟着再在这衬底上方沉积一层多晶硅或非晶硅层20。这硅层既盖着硅衬底露出的区域又盖着场氧化物区14a。如图4所示的那样，上部的硅层20在窗口或开口24处同衬底10相接触。也就是说，区域14a确定了到衬底10的开口。在这上部硅层20上方形成一层二氧化硅层或二氧化硅/氮化硅复合层22。这上部硅层20和复盖层22可以利用熟知的化学蒸发沉积步骤来产生。在现在优院选用的具体实现中，层20大约5000A°厚，复盖层厚可以为1000A°。
现在使上部硅层20重新结晶，这使层20采取衬底的结晶结构，也就是说，若衬底的晶向为（100），则层20的多晶硅或非晶硅也采取这结构的晶向（100）。通过用扫描激光（如连续波氩气激光）扫描电子束或石墨带加热器把图4的结构加热就可实现这重新结晶过程。图4中重新结晶过的层20作为层20a示于图5上。图4的开口24起晶种窗的作用，使衬底的结晶结构可以通过这晶种窗传入或长入层20。直接在晶种上方的层20的硅，图5中用箭头27表示，它的单晶结构质量最高，因为它直接在硅衬底上方，但是，衬底的结晶结构横向传进氧化物区14a上方的硅层，到图5中箭头28标出的区域。这横向重新结晶将发生在超出晶种窗边缘几微米的一段距离上，虽然最后形成的晶体结构的质量可能不如晶种窗上方的那么好。因此，层20a就其性质而言是一个外延硅层，其晶体生长是由予先确定的由场氧化物区分开的晶种窗产生的。正是在这硅层20a上，或者在其里面制造了场效应器件。
在重新结晶过程中，也可使用各种其他方法来加热衬底的背部。例如，可用一个热夹具来保持晶片结晶时的温升，也可用专门的石英炉。
再形成一个带有开口32的掩膜30，此开口在所选的晶种窗上方由掩膜层30确定。现在通过层20a把一种象磷或这样的杂质引进去。这杂质可以扩散进层20a，此处，先把层22在开口32处刻掉，或者这杂质也可通过层21用离子注入。杂质如所熟知的那样用来调整该n沟道器件的阀值电压。用另一个掩膜步骤来形成开口（在图6层30中用虚线表示）以对P沟道器件进行阀值电压调整。
下面几个工艺步骤是用来确定分开的区域，或用来构成再结晶过的硅层20的图案。图6的层22可用于构成这种图案，如果这一层被去掉了，可用另一个二氧化硅或氮化硅层35，如图7所示。（现在优先使用氮化硅）。掩膜元件36用来确定通过层35的开口37。用局部氧化以形成图8的氧化区38。可以利用反应离子刻蚀或局部氧化的组合来去掉开口37处的层20a，或者也可只用刻蚀来去掉它。
最后产生的结构示于图8，其中重新结晶过的这些硅区20b，彼此由氧化物38分开。注意，硅区20b在氧化物区14a的上方，彼此是电气绝缘的，而且在这些区20b之间经过硅衬底的通路（通过晶种窗）是相当长的。在如图8所示的区20b上可以生长一个高质量的栅氧化物40。假如采用刻蚀，这些区20b也是彼此绝缘的。
接下来，在图8结构的上方形成一层多晶硅层，而且使其形成图形，以确定图9所示的栅元件42和43。然后用两次掺杂步骤形成
型源、漏区44和P型源、漏区45。例如，如众所周知的那样，先把P沟道器件区用一种档光物盖上，在这过程中同栅42对齐，引进一种n型杂质以形成源和漏区44。然后把n沟道器件盖上，同栅43对齐，引进一种P型杂质以形成源和漏区45。通常，这时可以形成众所周知的纯化层（图上未画出）和金属化层，完成图9的晶体管。
图10画出了对图9结构的另一种具体实现方法。同图9类似的区域在图10上用同样的数字表示，只是每个数字后面加了一个零。例如在图10上，场效应器件是做在一个衬底100上，n沟道器件有一个栅420，而P沟道器件有一个栅430。图10器件的工艺过程大致上是同上面对图1-9所说的相同，只是重新结晶的硅区200b并不在图10箭头46所标出的区域被分成一些独立的区域。（例如，这要求去掉最中心的开口37，这开口用图7的掩膜层36表示出来）。用图10的结构，n沟道器件的源区和漏区之一是同P沟道器件的源和漏区之一相接触的。这在这些晶体管之间提供了一个公共结，这一点在CMOS反相器的制造上特别有用。（注意，为了把这些区域连起来，用了一个金属旁路）
跟用以前的隔离工艺的电路相比，图9和图10所示的集成电路有几个优点。例如，可注意到，图9上n+区44最接近P+区45，它们在氧化物区14a的上方，彼此是完全绝缘的。这样，这些区域相互隔开的距离就可以近到掩膜公差所允许的程度，而不用害怕会产生穿通。经过衬底上的窗口和氧化物区14a下方形成的这些区域之间的通道是相当长的（如3微米），由于它太长而不会引起什么问题。如已提到过的那样，最高质量的重新结晶发生在图9的晶种窗24处，这些高质量的硅在晶体管的沟道处，这里正是最需要它的地方。较差的重新结晶靠近源和漏区的外边缘，这些差的重新结晶发生在这里不象它假如发生在沟道区那么要紧。对于图9和图10的电路，这些器件是同下面的衬底相接触的。（在井34和340的外部和里面）这就可以更好地控制由热电子形成的衬底漏电流。而且由于源结和漏结几乎全部在氧化物区14a的上方，故其结电容小、结的漏电流小。接触到衬底的漏电，（如由金属接触形成）要比以前技术的结构更容易，因为可以把这些接点连到氧化物区14a或140a上方的源和漏区。从而以前的技术中常用的防止脉冲尖峰（spiking）的扩散塞（diffusion    plug）就不需要了。
至此，已经介绍了为准备一块硅衬底以在其上制造场效应晶体管的改进工艺过程。在氧化物区的上方形成一些空间上分开的重新结晶过的硅区。重新结晶是从在氧化物区之间形成的晶种窗发生的。场效应器件就形成在这些晶种窗的上方。

Claims (16)

1、在一片硅衬底上制造场效应器件的过程中，利用一些绝缘区把所述器件彼此隔离开来，改进的工艺过程包括下列步骤：
在所述的衬底上形成所述的绝缘区，以便定下在这些所述绝缘区之间的窗口；
在所述的绝缘区和窗口上方形成一层硅层；
把所述的硅层进行处理，使所述硅层重新结晶，所述的这种重新结晶是通过所述的窗口发生的；
在所述的重新结晶过的硅层中，在所述窗口的上方形成场效应器件；
由此，就由所述的硅层形成了一层可在其中制造场效应器件的硅层。
2、由权项1确定的工艺过程，包括在所述重新结晶硅层中确定隔离区的附加步骤，这些所述的隔离区是在所述的绝缘区上方彼此隔离开的;
3、由权项2确定的工艺过程，这里所述器件的沟道一般位于所述窗口的上方，而所述器件的源和漏区伸展到所述绝缘区的上方;
4、由权项1确定的工艺过程，这里，所述的硅衬底是一片单晶硅，所述的重新结晶过的硅层取所述衬底的晶向，这样便形成了一层类似外延层的上部硅层;
5、由权项4确定的工艺过程，这里，形成所述硅层的所述工艺步骤包括形成一层多晶硅的步骤;
6、由权项4确定的工艺过程，这里，形成一层硅层的步骤包含形成一层非晶硅的步骤;
7、由权项1确定的工艺过程，这里，所述的绝缘区是由所述衬底生长出来的生长氧化硅区;
8、由权项7确定的工艺过程，它包括在所述的形成所述硅层的步骤前把所述的生长二氧化硅区弄平的步骤;
9、由权项1定义的工艺过程，这里，对所述硅层进行处理以形成所述的重新结晶过的硅的所述步骤包括把所述硅层加热;
10、一种在一片硅衬底上制造场效应晶体管的工艺过程，它包括下列步骤：
在所述衬底上形成空间上隔开的氧化物区;
在所述氧化物区上方形成一层硅层，所述的硅层同所述的空间上隔开的氧化物区之间的所述衬底相接触;
对所述硅层进行处理，使所述硅层重新结晶，结晶时所述硅层采取所述衬底的结晶结构，所述的重新结晶是从所述的空间上分开的氧化物区之间（在这里所述硅层同所述衬底有所述的接触）传入所述硅层的;
在所述重新结晶过的硅层中，在所述的空间上分开的氧化物区上方形成场效应晶体管;
由此制造出了场效应晶体管;
11、由权项10确定的工艺过程，这里，所述的形成所述硅层的步骤包括形成一个多晶硅的过程;
12、由权项10确定的工艺过程，这里，所述的形成所述硅层的步骤包括形成一层非晶硅的步骤;
13、由权项11或12确定的工艺过程，这里，所述的形成空间上分开的氧化物区的步骤包括由所述衬底生长出氧化物区的步骤;
14、由权项13确定的工艺过程，这里，对所述硅层进行处理，引起所述的重新结晶的所述步骤包括把所述硅层加热;
15、由权项14确定的工艺过程，这里，在形成所述硅层前要把所述氧化物区弄平;
16、由权项10确定的工艺过程，它包括一些在所述重新结晶过的硅层中形成隔离区的步骤。
CN85104551.0A 1985-02-11 1985-06-14 在硅衬底上形成隔离硅区和场效应器件的工艺过程 Expired CN1006261B (zh)

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