WO1996042112A1 - Circuit integre a semi-conducteur, son procede de fabrication et plaquette semi-conductrice - Google Patents

Circuit integre a semi-conducteur, son procede de fabrication et plaquette semi-conductrice Download PDF

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Publication number
WO1996042112A1
WO1996042112A1 PCT/JP1996/000940 JP9600940W WO9642112A1 WO 1996042112 A1 WO1996042112 A1 WO 1996042112A1 JP 9600940 W JP9600940 W JP 9600940W WO 9642112 A1 WO9642112 A1 WO 9642112A1
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WO
WIPO (PCT)
Prior art keywords
semiconductor
integrated circuit
circuit device
layer
insulating layer
Prior art date
Application number
PCT/JP1996/000940
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English (en)
Japanese (ja)
Inventor
Shinichiro Wada
Tamotsu Miyake
Nobuo Tamba
Akihisa Uchida
Original Assignee
Hitachi, Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi, Ltd. filed Critical Hitachi, Ltd.
Publication of WO1996042112A1 publication Critical patent/WO1996042112A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0921—Means for preventing a bipolar, e.g. thyristor, action between the different transistor regions, e.g. Latchup prevention
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78612—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device for preventing the kink- or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect

Definitions

  • the present invention relates to a semiconductor integrated circuit device and a manufacturing technology thereof, and more particularly to a technology effective when applied to a semiconductor integrated circuit device having a SOI (Silicon On Insulator) structure.
  • SOI Silicon On Insulator
  • SOI technology in which a thin semiconductor layer is formed on a semiconductor substrate via an insulating layer and an element is formed in this semiconductor layer, is capable of complete element isolation. Therefore, when a semiconductor element is formed on a single-crystal silicon substrate, The following advantages are obtained as compared with.
  • the above-mentioned document discloses a technique for forming a sufficiently thin semiconductor layer and completely depleting the channel region when a gate voltage is applied, as a measure for preventing floating of the channel region.
  • Japanese Patent Application Laid-Open No. 62-109355 discloses that as a measure for preventing floating of a channel region, a second p-type semiconductor region electrically connected to a p-type semiconductor region where a channel region is formed is an n-channel type. It discloses a technique that is formed at the end of the source / drain region (n-type semiconductor region) of the MIS FET and applies a fixed potential to this second p-type semiconductor region.
  • An object of the present invention is to provide a technique capable of preventing a threshold voltage of a MIS FET formed on an S01 substrate from fluctuating and setting a threshold voltage to an enhancement type.
  • Another object of the present invention is to provide a technique capable of preventing a fluctuation of a threshold voltage of an MIS FET formed on an SOI substrate and improving a current driving capability. It is in.
  • an MIS FET is formed on a main surface of a semiconductor layer formed on a semiconductor substrate via an insulating layer, and the MIS FET is formed on the insulating layer below a channel region of the MIS FET.
  • An opening is provided, and the channel region and the semiconductor substrate are electrically connected through the opening.
  • the method for manufacturing a semiconductor integrated circuit device includes the steps of: forming a MISFET on a substrate having an SOI structure in which a semiconductor layer is formed on a semiconductor substrate via an insulating layer;
  • the channel region of the MIS FET is electrically connected to the semiconductor substrate through the opening in the insulating layer, fluctuation of the threshold voltage due to floating of the channel region is prevented. Thus, stable operation of the MIS FET can be achieved.
  • the threshold voltage can be controlled without reducing the thickness of the semiconductor layer until the channel region is completely depleted when the gate voltage is applied, the resistance values of the source and drain regions can be prevented from increasing.
  • the current drive capability of the MIS FET can be improved.
  • FIG. 1 is a plan view of a main part of an SOI substrate showing a semiconductor integrated circuit device according to a first embodiment of the present invention
  • FIG. 2 is a cross-sectional view taken along line II in FIG. 1
  • FIG. 4 is a cross-sectional view of a main part of an SOI substrate showing a method of manufacturing a semiconductor integrated circuit device according to a first embodiment of the present invention
  • FIG. 5 is a sectional view of a main part of an SOI substrate showing a method of manufacturing a semiconductor integrated circuit device according to a first embodiment of the present invention.
  • FIG. 6 is a sectional view of a semiconductor according to the first embodiment of the present invention.
  • FIG. 1 is a plan view of a main part of an SOI substrate showing a semiconductor integrated circuit device according to a first embodiment of the present invention
  • FIG. 2 is a cross-sectional view taken along line II in FIG. 1
  • FIG. 4 is a cross-sectional view of a main part of an SOI substrate showing a
  • FIG. 7 is a perspective view of an SOI substrate showing a method of manufacturing an integrated circuit device
  • FIG. 7 is a sectional view of a main part of the SOI substrate showing a method of manufacturing a semiconductor integrated circuit device according to a first embodiment of the present invention
  • FIG. 9 is a cross-sectional view of a main part of an SOI substrate showing a method of manufacturing a semiconductor integrated circuit device according to a first embodiment of the present invention
  • FIG. 10 is a cross-sectional view of a main part of an SOI substrate showing a method of manufacturing a semiconductor integrated circuit device according to a first embodiment of the present invention.
  • FIG. 11 is a cross-sectional view of a main part of an SOI substrate showing a method of manufacturing a semiconductor integrated circuit device according to a first embodiment of the present invention.
  • FIG. 12 is a sectional view of the semiconductor integrated circuit device according to the first embodiment of the present invention.
  • FIG. 13 is a cross-sectional view of a main part of an SOI substrate showing a manufacturing method.
  • FIG. 13 is a cross-sectional view of a main part of an SOI substrate showing a method of manufacturing a semiconductor integrated circuit device according to a second embodiment of the present invention.
  • FIG. 15 is a cross-sectional view of a main part of an SOI substrate showing a method of manufacturing a semiconductor integrated circuit device according to a second embodiment of the present invention.
  • FIG. 12 is a sectional view of the semiconductor integrated circuit device according to the first embodiment of the present invention.
  • FIG. 13 is a cross-sectional view of a main part of an SOI substrate showing a manufacturing method.
  • FIG. 13 is
  • FIG. 15 is a view illustrating a method of manufacturing a semiconductor integrated circuit device according to a second embodiment of the present invention.
  • FIG. 16 is a sectional view of a main part of an SOI substrate, and FIG. 16 is an SOI substrate showing a method of manufacturing a semiconductor integrated circuit device according to a second embodiment of the present invention.
  • Fragmentary cross-sectional view, FIG. 1 7 is a fragmentary cross-sectional view of a SOI substrate showing a method of manufacturing another semiconductor integrated circuit device which is an embodiment of the present invention. Best mode for implementing
  • FIG. 1 and 2 show a semiconductor integrated circuit device according to a first embodiment of the present invention.
  • FIG. 1 is a plan view of a main part of the SOI substrate
  • FIG. 2 is a cross-sectional view taken along line II in FIG.
  • the semiconductor integrated circuit device according to the present embodiment includes a semiconductor substrate 1 and semiconductor layers 3 a and 3 b formed on the semiconductor substrate 1 via an insulating layer 2.
  • a CMOS (Complimentary MOS) circuit composed of an n-channel MIS FETQn and a p-channel MISFETQp is formed.
  • the semiconductor substrate 1 is made of P-type single-crystal silicon (Si), and an n-type well 4 is formed on a part thereof.
  • the insulating layer 2 is composed of a silicon oxide layer having a large number of openings 5 formed at equal intervals.
  • the semiconductor layer 3a is made of an n-type epitaxial single-crystal silicon, and is electrically connected to the n-type well 4 through an opening 5 formed in the insulating layer 2 thereunder.
  • the semiconductor layer 3b is made of p-type epitaxial single crystal silicon, and is electrically connected to the p-type semiconductor substrate 1 through an opening 5 formed in the insulating layer 2 thereunder.
  • the n-channel type MISFETQn is formed on the main surface of the active region of the p-type semiconductor layer 3b surrounded by the element isolation field insulating film 6 made of silicon oxide.
  • the n-channel type MIS FETQn includes an n-type semiconductor region (source region, drain region) 7 formed in the semiconductor layer 3 b, a silicon oxide gate insulating film 8 formed on the surface of the semiconductor layer 3 b, A gate electrode 9 made of polycrystalline silicon formed on the gate insulating film 8.
  • the semiconductor layer 3 b immediately below the gate electrode 9, that is, the channel region, is electrically connected to the semiconductor substrate 1 through the opening 5 in the insulating layer 2.
  • a wiring 12 is connected to another active region of the p-type semiconductor layer 3b through a connection hole 11 formed in a silicon oxide insulating film 10, and a substrate potential of about 12 V is supplied. Is done.
  • the semiconductor layer 3b is formed with the n-channel type MIS FETQn. Like the semiconductor layer 3b, the semiconductor layer 1b is electrically connected to the semiconductor substrate 1 through the opening 5 in the insulating layer 2 thereunder.
  • the n-channel type MISFETQn electrically connects the channel region to the semiconductor substrate 1 through the opening 5 of the insulating layer 2 and supplies a substrate potential to the channel region, thereby forming the channel region.
  • the P-channel type MISFETQp is formed on the main surface of the active region of the IT type semiconductor layer 3a surrounded by the field insulating film 6.
  • the p-channel type MIS FETQp includes a p-type semiconductor region (source region and drain region) formed in the semiconductor layer 3a, a gate insulating film 8 formed on the surface of the semiconductor layer 3a, and a gate insulating film 8 And a gate electrode 9 formed thereon.
  • the semiconductor layer 3 a immediately below the gate electrode 9, that is, the channel region is electrically connected to the n-type well 4 through the opening 5 of the insulating layer 2.
  • a wiring 12 is connected to another region of the IT type semiconductor layer 3 a through a connection hole 11 formed in the insulating film 10, and a gate potential of about 2 V is supplied.
  • the semiconductor layer 3a is electrically connected to the n-type well 4 through the opening 5 of the insulating layer 2 below the semiconductor layer 3a, similarly to the semiconductor layer 3a on which the p-channel type MIS FETQ is formed. .
  • the p-channel type MIS FETQp electrically connects the channel region to the n-type well 4 through the opening 5 of the insulating layer 2 and supplies a jewel potential to the channel region, thereby forming a channel. This prevents the area from floating.
  • the threshold voltage is controlled without reducing the thickness of the semiconductor layers 3a and 3b until the channel region is completely depleted when the gate voltage is applied.
  • the resistance of the source and drain regions (n-type semiconductor region 7 and p-type semiconductor region 13) is prevented from increasing, and the current drive capability of each of the n-channel MIS FETQn and p-channel MIS FETQp Can be improved.
  • the threshold voltage can be prevented from lowering due to the manifestation of the parasitic bipolar transistor effect, and the threshold voltage can be set to an enhancement type.
  • a fixed potential is supplied to the channel region through the opening 5 of the insulating layer 2 below the semiconductor layers 3a and 3b.
  • the current drive capability of each of the n-channel MISFETQn and the p-channel MISFETQp can be improved. Further, it is possible to prevent an increase in the junction capacitance of the source and drain regions (the n-type semiconductor region 7 and the p-type semiconductor region 13), thereby improving the operation speed.
  • the heat generated during the operation of the n-channel MIS FETQn and the p-channel MIS FETQp is transferred to the semiconductor substrate 1 through the opening 5 of the insulating layer 2 below the semiconductor layers 3a and 3b. Since the heat can escape, the heat dissipation of the SOI substrate can be improved.
  • the insulating layer 2 and the photoresist 15 are formed.
  • removing the photoresist 15 see FIG.
  • an opening 5 reaching the semiconductor substrate 1 and an opening 5 reaching the n-type well 4 are formed.
  • the openings 5 are formed at equal intervals along directions orthogonal to each other on the main surface of the insulating layer 2.
  • the opening 5 is formed such that its diameter is smaller than the gate length of the gate electrode of the MISFET.
  • the interval between the openings 5 that are in contact with each other is smaller than the MIS that is in contact with each other along the gate length direction. It is set to be lZn (n is a natural number) of the interval between the gate electrodes of the FET.
  • a ⁇ -type semiconductor layer 3b is selectively formed on each surface of the semiconductor substrate 1 and the n-type well 4 exposed at the bottom of the opening 5. Epitaxial growth. The semiconductor layer 3 b is grown until the semiconductor layers 3 b grown through the respective openings 5 are connected to each other at the upper part of the insulating layer 2 so as to cover the entire surface of the insulating layer 2.
  • the semiconductor layer 3b is removed by CMP (Chemical Mechanical Polishing). (ng; chemical mechanical polishing) method or etch back, and the surface is flattened.
  • CMP Chemical Mechanical Polishing
  • the semiconductor layer 3b has a thickness at least such that the channel region is not completely depleted when a gate voltage is applied.
  • an n-type impurity (phosphorous or arsenic) is implanted into the semiconductor layer 3 b in the region where the p-channel MIS FET Qp is formed using the photoresist 17 as a mask.
  • An ⁇ -type semiconductor layer 3a is formed.
  • a thick field insulating film 6 for device isolation and a gate insulating film 8 are formed on each surface of the semiconductor layers 3a and 3b.
  • the gate electrode 9 is formed on the gate insulating film 8 of each of the semiconductor layers 3a and 3b by patterning the polycrystalline silicon film deposited by the CVD method as shown in FIG. .
  • a p-type impurity (boron) is implanted into the semiconductor layer 3a to form a source / drain region (p-type semiconductor region 13) of the P-channel type MIS FET Qp.
  • a source / drain region (n-type semiconductor region 7) of n-channel type MIS FETQn is formed.
  • an insulating film 10 of silicon oxide is deposited on each of the n-channel type MISFETQn and the p-channel type MISFETQp by the CVD method.
  • the wiring 12 is connected to each of the source and drain region (p-type semiconductor region 13) of the channel type MIS FETQp and the source and drain region (n-type semiconductor region 7) of the ⁇ -channel type MIS FETQn.
  • the CMOS circuit shown in FIGS. 1 and 2 is completed by connecting the wiring 12 for supplying the gate potential to the semiconductor layer 3a and the wiring 12 for supplying the substrate potential to the semiconductor layer 3b in another region. I do.
  • the SOI substrate composed of the semiconductor substrate 1, the insulating layer 2, and the semiconductor layers 3a and 3b made of epitaxial silicon single crystal was used. After implanting oxygen ions into the semiconductor substrate 1 made of, the semiconductor substrate 1 is heat-treated to form a silicon oxide insulating layer therein.
  • An SOI substrate obtained by a so-called SI OX (Separation by Implanted Oxygen) method can also be used.
  • the insulating film (or photoresist) 18 of silicon oxide or the like formed on the p-type semiconductor substrate 1 is used as a mask to form a semiconductor in the formation region of the p-channel type MIS FETQp.
  • an n-type impurity phosphorous or arsenic
  • the insulating film 18 is removed, and then, as shown in FIG.
  • the epitaxial semiconductor layer 19b is epitaxially grown.
  • island-shaped insulating film patterns 20 are formed at equal intervals on the semiconductor layer 19b, oxygen ions are formed inside the semiconductor layer 19b using the insulating film pattern 20 as a mask. inject.
  • the island-shaped insulating film pattern 20 is formed, for example, by patterning a silicon oxide film formed on the semiconductor layer 1b.
  • the dimensions and intervals of the insulating film pattern 20 are the same as those of the openings 5 formed in the insulating layer 2 of the SOI substrate used in the first embodiment.
  • the semiconductor substrate 1 is heat-treated to react silicon with oxygen, thereby forming an insulating layer 21 made of silicon oxide on the bottom of the semiconductor layer 19b.
  • the SOI since the insulating layer 21 is not formed in the region below the insulating film pattern 20 where the oxygen ions have not been implanted, the SOI has a structure substantially similar to that of the first embodiment shown in FIG. A substrate is obtained.
  • CMOS gate array may be formed according to the steps shown in FIGS. 9 to 12 of the first embodiment.
  • a fixed potential is supplied to each channel region of the n-channel MIS FETQn and the p-channel MISFETQp constituting the CMOS gate array.
  • a fixed potential may be supplied only to the channel region.
  • the insulating layer 2 formed on the semiconductor substrate 1 is etched to form the opening 5, as shown in FIG. 2 may be removed entirely. In this case, the region from which the insulating layer 2 has been removed does not have an SOI structure. It is possible to form a MIS FET with different characteristics. That is, MIS FETs having different characteristics can be mixed on the same semiconductor substrate 1.
  • the present invention can be applied not only to a CMOS gate array but also to a case where a circuit is constituted only by n-channel MIS FETQn. That is, the present invention can be widely applied to a semiconductor integrated circuit device including a MIS FET formed on an SOI substrate.
  • the semiconductor integrated circuit device of the present invention can suppress the fluctuation of the threshold voltage of the MIS FET formed on the semiconductor layer of the SOI substrate, and can achieve the stable operation of the MIS FET. It is suitable for use in various LSIs using SOI substrates.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)

Abstract

L'invention porte sur un circuit intégré à semi-conducteur à substrat de SOI comportant un MISFET Qp à canal p et un MISFET Qn à canal n disposés sur la face principale de couches semi-conductrices (3a et 3b) formées sur un substrat semi-conducteur (1) (n puits 4) à travers une couche isolante (2). Un trou (5) traverse la couche isolante (2) sous la région canal de chacun des MISFET Qp à canal p et un MISFET Qn à canal n. Chacune des régions canal ainsi que le substrat semi-conducteur (1) (n puits 4) sont reliés électriquement par ledit trou (5).
PCT/JP1996/000940 1995-06-12 1996-04-05 Circuit integre a semi-conducteur, son procede de fabrication et plaquette semi-conductrice WO1996042112A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP7/145035 1995-06-12
JP14503595 1995-06-12

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Publication Number Publication Date
WO1996042112A1 true WO1996042112A1 (fr) 1996-12-27

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2812970A1 (fr) * 2000-08-11 2002-02-15 Samsung Electronics Co Ltd Transistor a effet de champ de type metal-oxyde-semiconducteur a sillicium sur isolant et son procede de fabrication
JP2007110029A (ja) * 2005-10-17 2007-04-26 Toshiba Corp 半導体記憶装置及びその製造方法

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Publication number Priority date Publication date Assignee Title
JPS61187224A (ja) * 1985-02-11 1986-08-20 インテル・コーポレーシヨン シリコン基板上に電界効果装置を製造する方法
JPS61265859A (ja) * 1985-05-20 1986-11-25 Toshiba Corp 相補型ｍｏｓ半導体装置
JPS63181421A (ja) * 1987-01-23 1988-07-26 Matsushita Electric Ind Co Ltd イオン注入に対するマスク材料
JPS63192266A (ja) * 1987-02-04 1988-08-09 Oki Electric Ind Co Ltd Ｃｍｏｓ集積回路及びその製造方法
JPS63228668A (ja) * 1987-03-17 1988-09-22 Nec Corp 半導体装置の製造方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61187224A (ja) * 1985-02-11 1986-08-20 インテル・コーポレーシヨン シリコン基板上に電界効果装置を製造する方法
JPS61265859A (ja) * 1985-05-20 1986-11-25 Toshiba Corp 相補型ｍｏｓ半導体装置
JPS63181421A (ja) * 1987-01-23 1988-07-26 Matsushita Electric Ind Co Ltd イオン注入に対するマスク材料
JPS63192266A (ja) * 1987-02-04 1988-08-09 Oki Electric Ind Co Ltd Ｃｍｏｓ集積回路及びその製造方法
JPS63228668A (ja) * 1987-03-17 1988-09-22 Nec Corp 半導体装置の製造方法

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Title
IEDM, 1987, W.T. LYNCH, "Self-Aligned Contact Schemes for Source-Drains in Submicron Devices", pages 354-357. *

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2812970A1 (fr) * 2000-08-11 2002-02-15 Samsung Electronics Co Ltd Transistor a effet de champ de type metal-oxyde-semiconducteur a sillicium sur isolant et son procede de fabrication
US6794716B2 (en) 2000-08-11 2004-09-21 Samsung Electronics Co., Ltd. SOI MOSFET having body contact for preventing floating body effect and method of fabricating the same
JP2007110029A (ja) * 2005-10-17 2007-04-26 Toshiba Corp 半導体記憶装置及びその製造方法

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