CN1006261B - 在硅衬底上形成隔离硅区和场效应器件的工艺过程 - Google Patents

在硅衬底上形成隔离硅区和场效应器件的工艺过程 Download PDF

Info

Publication number
CN1006261B
CN1006261B CN85104551.0A CN85104551A CN1006261B CN 1006261 B CN1006261 B CN 1006261B CN 85104551 A CN85104551 A CN 85104551A CN 1006261 B CN1006261 B CN 1006261B
Authority
CN
China
Prior art keywords
layer
silicon layer
substrate
technical process
silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
CN85104551.0A
Other languages
English (en)
Other versions
CN85104551A (zh
Inventor
贝格
赵·H·挺
华泰礼
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of CN85104551A publication Critical patent/CN85104551A/zh
Publication of CN1006261B publication Critical patent/CN1006261B/zh
Expired legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/761—PN junctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/02433—Crystal orientation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02488—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H01L21/0259—Microstructure
    • H01L21/02598—Microstructure monocrystalline
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02609—Crystal orientation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02675—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
    • H01L21/02683—Continuous wave laser beam
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02689—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using particle beams
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02691—Scanning of a beam
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66651—Lateral single gate silicon transistors with a single crystalline channel formed on the silicon substrate after insulating device isolation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76272—Vertical isolation by lateral overgrowth techniques, i.e. ELO techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76281—Lateral isolation by selective oxidation of silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration

Abstract

在一个类似延层的硅层中形成ＭＯＳ和ＣＭＯＳ晶体管的改进的工艺过程。先形成一些场氧化物区，接着再沉积一层多晶硅层或非晶硅层，这些硅层在这些场氧化物区之间形成“晶种窗”处同衬底接触。这硅层由衬底通过晶种窗重新结晶，晶体管就造在这层重新结晶过的硅层中。

Description

在硅衬底上形成隔离硅区和场效应器件的工艺过程
本发明涉及MOS集成电路领域，尤其涉及在一块硅衬底上形成隔离硅区的有关问题。
在金属-氧化物-半导体（MOS）集成电路制造过程中，常常采取把一个器件同另一个器件隔离开的步骤以消除或减少器件之间的寄生通路。例如，若把场效应晶体管不加隔离的制造在一块硅衬底上，这样，两个不同晶体管的源区或漏区就可能成为无用的第三只晶体管。复盖在表面的相互连接，象安排在一个晶体管的源和另一晶体管的漏之间的铝线，起了栅极的作用而可能引起寄生传导。
在互补MOS（CMOS）集成电路中，寄生通路的问题甚至更大。这里，互补晶体管的衬底n+区或P+区，以及用于形成一种导电型晶体管的井都可能相互一起形成一个无用的晶体管，在这些不同区域之间的晶体管的作用可能导致产生一个破坏集成电路的寄生通路，这问题有时称作“latch-up”。（闩锁）
现在有几种加工技术用来减少寄生传导，通常在相邻晶体管之间用场氧化物区来把一个晶体管的源同另一个晶体管的漏隔离开，这些较厚的氧化物区在相邻的晶体管之间提供了一个导电性较小的通路（或更长的通路），而且复盖在上面的线离衬底的距离更大了，这样就降低了它们作为无用的栅极的效率。对于CMOS电路，典型的从n+到p+的场氧化物是6微米宽，这样它耗掉的衬底面积，同制造这场效应管所需要的面积相比是相当大的，在另一些情况下，在衬底上形成一些沟，并用一种绝缘材料把这沟填满。尽管这项技术是有效的，分开的距离甚至小到1微米，但它需要更为复杂的工艺过程。
在CMOS电路中也用其他技术来防止闩锁，例如，在一块高度掺杂的衬底上生长出一外延层，在这外延层上形成这些电路。在另一些电路中，在一个绝缘体上方，象在SOS（兰宝石硅片）工艺中一样形成一层薄层。
现在这项发明提供一种与上述先有技术不同的技术，根据此项发明，利用衬底的晶状结构，作为在绝缘区上形成一种类似外延层的生长籽晶。
用来由籽晶形成类外延层的其他工艺过程都是熟知的，一般来说，这些老的工艺过程用一个籽晶，而且不是在籽晶窗上制造器件，或者在最后的电路中衬底也不参加电气活动。就申请人所知的最接近的先有技术是：（1）电子周刊（Electronic Week），1984年8月6日，第31页“英国聚集力量于SOI技术工艺在际价上攻击美国和日本芯片制造商;（2）电子周刊（Electronic Week）1984年8月6日，第32-33页，“剑桥实验室加使晶片顶部和底部呈现热潮”（3）IED.1982年4月16日，第433页-436页“通过制造基本的器件结构所得的激光-SOI双层硅活性层的特征”（4）国际电子器件会（TEDM）1982年1月16日，第420-423页，“以电子束使多晶硅再结晶的MOS晶体管”;（5）电化学协会会报（J.Electrochem.soc）1981年9月，第1981页-1986页（128卷，第9期）“由扫描连续波激光诱发横向引晶工艺在氧化物上生长单晶硅”;（6）34、5，第808-811页，“一亚微型SOI技术的器件特性”;以及（7）晶体生长杂志（Journal of Crystal Crowth63，），1983年，第453-483页，“石墨带状加热器-区域熔化的硅膜的再结晶”。
叙述了一种在一块硅衬底上制造场效应器件的改进工艺过程，按这种工艺，用绝缘区来把这些器件彼此隔离开来。在衬底上形成了这些绝缘区，它们确定了这些区域之间开口的大小;这些区域为衬底提供了“籽晶窗”。在这些绝缘区的上方形成一层硅（如，多晶硅或非晶硅），这层硅伸进窗里面，这层硅需经处理以使该衬底的结晶结构经过籽晶窗长入这层硅里，硅层的这个再结晶过程是经过这些窗口引入籽晶的。再结晶过的这层硅形成一个主晶层，在它里面或它上面制造场效应器件，而这些器件的沟道区直接形成在籽晶窗的上方。
附图的简要说明
图1是一部分硅衬底的横截面正视图，这一部分包括一个n型井，一个二氧化硅层和氮化硅掩膜;
图2示出的是图1的衬底在氧化并去掉了氮化硅掩膜后的情况;
图3示出的是图2的衬底平面化后的情况;
图4示出的是图3的衬底，在它上面形成一层硅层后的情况;
图5示出的是图4的衬底，在衬底的结晶结构传入上面硅层后的情况;
图6示出的是图5的衬底在进行掺杂用以调整器件的阈值电压时的情况;
图7示出的是图6的衬底在另一掩膜步骤后的情况;
图8示出的是图7的衬底在加工处理了硅层以隔离两相邻晶体管区后的情况;
图9示出的是图8的衬底，在硅层上面中制造了CMOS晶体管后的情况;
图10是一个衬底的横截面正视图，它示出了本发明的另一种实施例，这对制造CMOS反相器是特别有用的。
本发明叙述在一块硅衬底上形成隔离区和场效应器件的一种工艺过程。下面的说明提出了许多具体细节，以便本发明能被彻底了解。显然，对熟释本专业的人来说，没有这些具体细节，也能实现这个工艺过程。而在另一些场合，大家所熟悉的那些工艺步骤就没有详细叙述，以便不致不必要地掩盖本发明。
图1-9举例说明了如何用本发明教给的方法制造互补MOS场效应器件（特别是场效应晶体管）。制造过程从一块通常的P型单晶硅衬底开始，它在图1中用10表示。用大家熟知的工艺过程，在衬底上产生一个供P沟道器件用的n型井34。这个井可用砷、磷或其他n型杂质掺杂。在衬底10的上表面沉积了一个象二氧化硅层这样的保护层12。用普通的掩膜和刻蚀工艺步骤形成氮化硅部分13。这些氮化硅部分彼此隔离，如图所示的那样，其中一个在井34的上方形成。这些氮化硅的宽度对于本发明并不关键;例如，它们可在1微米的量级或更小。
图1的衬底再经过一个高温氧化步骤，如通常所用的那样，以形成图2所示的场氧化物区14。（这一步骤也可用“推进”步骤形成井34）这个场氧化物区14的厚度，比方说可为6000
Figure 85104551_IMG2
。
尽管没有必要，但人们还是喜欢把图2的结构平面化，也就是说，利用一些步骤形成图3所示的平坦表面15，可以利用已知的加工工艺来实现这种平面化。要形成一个平面层，可在图2结构的上方形成一个聚甲基丙烯酸甲酯（有机玻璃）复盖层或者一层旋涂玻璃层（spin-on-glass）形成一平面表层，然后再对这平面进行反应离子刻蚀，它在这层和场氧化物区14之间具有1-1方向的选择性刻蚀。图2的场氧化物区的厚度减小了，它作为场氧化物区14a示于图3。
现在用氢氟酸浸渍把场氧化物区14a之间的硅衬底暴露出来，跟着再在这衬底上方沉积一层多晶硅或非晶硅层20，这种沉积是先有技术所熟知的。这硅层既盖着硅衬底露出的区域又盖着场氧化物区14a。如图4所示的那样，上部的硅层20在窗口或开口24处同衬底10相接触。也就是说，区域14a确定了到衬底10的开口。在这上部硅层20上方形成一层二氧化硅层或二氧化硅/氮化硅复合层22。这上部硅层20和复盖层22可以利用熟知的化学汽相沉积步骤来产生。在本实施例选用的具体实现中，层20大约5000
Figure 85104551_IMG3
厚，复盖层厚可以为1000。
现在使上部硅层20再结晶，这使层20采取衬底的结晶结构，也就是说，若衬底的晶向为（100），则层20的多晶硅或非晶硅也采取这结构的晶向（100）。通过用扫描激光（如连续波氩气激光）扫描电子束或石墨带加热器把图4的结构加热就可实现这再结晶过程。图4中再结晶过的层20作为层20a示于图5上。图4的开口24起籽晶窗的作用，使衬底的结晶结构可以通过这籽晶窗传入或长入层20。直接在籽晶窗上方的层20的硅，图5中用箭头27表示，它的单晶结构质量最高，因为它直接在硅衬底上方，但是，衬底的结晶结构横向传进氧化物区14a上方的硅层，到图5中箭头28标出的区域。这横向再结晶将发生在超出籽晶窗边缘几微米的一段距离上，虽然最后形成的晶体结构的质量可能不如籽晶窗上方的那么好。因此，层20a就其性质而言是一个外延硅层，其晶体生长是由预先确定的由场氧化物区分开的籽晶窗产生的。正是在这硅层20a上和在其里面制造了场效应器件。
在再结晶过程中，也可使用各种其他方法来加热衬底的背部。例如，可用一个热夹具来保持圆片再结晶时的高温，也可用专门的石英炉。
再形成一个带有开口32的掩膜层30，此开口在所选的籽晶窗上方由掩膜层30确定。现在通过层20a把一种象磷或砷这样的n型杂质引进去。这杂质可以扩散进层20a，此处，先把层22在开口32处刻掉，或者这杂质也可通过层22用离子注入，杂质如所熟知的那样用来调整该n沟道器件的阈值电压。用另一个掩膜步骤用来形成开口（在图6层30中用虚线表示）以对P沟道器件进行阈值电压调整。
下面几个工艺步骤是用来确定分开的区域，或用来构成再结晶过的硅层20的图案。图6的层22可用于构成这种图案，如果这一层被去掉了可用另一个二氧化硅或氮化硅层35，如图7所示。（现在优先使用氮化硅）。掩膜部分36用来确定通过层35的开口37。用局部氧化以形成图8的氧化区38。可以利用反应离子刻蚀或局部氧化的组合来去掉开口37处的层20a，或者也可只用刻蚀来去掉它。任何一种先有技术的大部分的材料都可以用来作掩膜部分30和36，而且，先有技术的掩膜方法的实现也可以用来作掩膜和确定开口32和37。
最后产生的结构示于图8，其中再结晶过的这些硅区20b，彼此由氧化物38分开。注意，硅区20b在氧化物区14a的上方，彼此是电气绝缘的，而且在这些区20b之间经过硅衬底的通路（通过籽晶窗）是相当长的。在如图8所示的区20b上可以生长一个高质量的栅氧化物40。假如采用刻蚀，这些区20b也些彼此绝缘的。
接下来，在图8结构的上方形成一层多晶硅层，而且使其形成图形，以确定图9所示的栅部分42和43。然后用两次掺杂步骤形成源、漏区44和源、漏区45。例如，如众所周知的那样，先把P沟道器件区用一种光致抗蚀剂盖上，在这过程中同栅42对齐，引起一种n型杂质以形成源和漏区44。然后把n沟道器件盖上，同栅43对齐，引起一种P型杂质以形成源和漏区45。通常，这时可以形成众所周知的钝化层（图上未画出）和金属化层，完成图9的晶体管。
图10画出了对图9结构的另一种实施例。同图9类似的区域在图10上用同样的数字表示，只是每个数字后面加了一个零。例如在图10上，场效应器件是做在一个衬底100上，n沟道器件有一个栅420，而P沟道器件有一个栅430。图10器件的工艺过程大致上是同上面对图1-9所说的相同，只是再结晶的硅区200b并不在图10箭头46所标出的区域被分成一些独立的区域。（例如，这要求去掉最中心的开口37，这开口用图7的掩膜层36表示出来）。用图10的结构，n沟道器件的源区或漏区之一是同P沟道器件的源或漏区之一相接触的。这在这些晶体管之间提供了一个公共结，这一点在CMOS反相器的制造上特别有用。（注意，为了把这些区域连起来，用了一个金属短路）
跟用以前的隔离工艺的电路相比，图9和图10所示的集成电路有几个优点。例如，可注意到，图9上最接近P+区45的n+区44，它们彼此是完全绝缘的。这样，这些区域相互隔开的距离就可以尽可能地接近掩膜公差所允许的程度，而不用担心会产生穿通。经过衬底上的窗口和氧化物区14a下方形成的这些区域之间的通道是相当长的（如3微米），由于它太长而不会引起什么问题。如已提到过的那样，最高质量的再结晶发生在图9的籽晶窗24处，这些高质量的硅在晶体管的沟道处，这里正是最需要它的地方。质量较差的再结晶靠近源和漏区的外边缘，这些差的再结晶发生在这里不象它假如发生在沟道区那么要紧。对于图9和图10的电路，这些器件是同下面的衬底相接触的。（在井34和340的外部和里面）这就可以更好地控制由热电子形成的衬底漏电流。而且由于源结和漏结几乎全部在氧化物区14a的上方，故其结电容小、结的漏电流小。接触到衬底的漏电（如由金属接触形成）要比先有技术的结构更容易，因为可以把这些接点连到氧化物区14a或140a上方的源和漏区。从而先有技术中常用的防止尖峰扩散（spiking）的扩散塞（diffusionplug）就不需要了。
至此，已经介绍了为准备一块硅衬底以在其上制造场效应晶体管的改进工艺过程。在氧化物区的上方形成一些空间上分开的再结晶过的硅区。再结晶是从在氧化物区之间形成的籽晶窗发生的。场效应器件就形成在这些籽晶窗的上方。

Claims (34)

1、在一片硅衬底上制造场效应器件的过程中，利用一些绝缘区把所述器件彼此隔离开来，改进的工艺过程的特征在于包括下列步骤：
在所述衬底上形成一绝缘层;
在所述绝缘层上形成掩膜部分;
在所述绝缘层未加掩膜的各部分形成绝缘区，其中所述各绝缘区延伸入衬底中，从而界定了所述各绝缘区之间的窗口;
蚀刻所述绝缘层和各绝缘区，使所述衬底在所述各窗口处暴露出来;
在所述各绝缘区和各窗口上面形成一硅层;
对所述硅层进行处理，促使所述硅层再结晶，所述再结晶过程是在所述衬底上生长出结晶，通过所述各窗口延伸入所述硅层中，再横向延伸入置于所述各绝缘区上方的所述硅层中;
形成一栅极，其中所述栅极置于形成漏区和源区的所述各绝缘区上方;
于是所述各绝缘区就把源区和漏区与所述衬底隔离开来。
2、根据权利要求1确定的工艺过程，其特征在于该工艺过程还包括在所述再结晶硅层中确定隔离区，以使各个所述器件在所述再结晶层里彼此隔离开的步骤。
3、根据权利要求2确定的工艺过程，其特征在于所述器件的沟道一般位于所述窗口的上方。
4、根据权利要求1确定的工艺过程，其特征在于所述的硅衬底是一单晶硅，所述的再结晶的硅层取所述衬底的晶向，这样便形成了一层类似外延层的上部硅层。
5、根据权利要求4确定的工艺过程，其特征在于形成所述硅层的所述工艺步骤包括形成一层多晶硅的步骤。
6、根据权利要求4确定的工艺过程，其特征在于形成一层硅层的所述步骤包含形成一层非晶硅的步骤。
7、根据权利要求1确定的工艺过程，其特征在于所述各绝缘区是由所述衬底生长出来的二氧化硅区。
8、根据权利要求7确定的工艺过程，其特征在于该工艺过程包括在所述的形成所述硅层的所述步骤前弄平所述绝缘层和各绝缘区的步骤。
9、根据权利要求1定义的工艺过程，其特征在于对所述硅层进行处理以形成所述的再结晶的硅的所述步骤包括把所述硅层加热。
10、一种在一单晶硅衬底上制造若干场效应晶体管（FETs）的工艺过程，其特征在于，该工艺过程包括下列步骤：
在所述衬底上形成一氧化层;
在所述氧化层上形成掩膜部分;
通过高温氧化在所述氧化层未加掩膜的各部分形成若干场氧化区，其中所述各场氧化区延伸入所述衬底中，从而界定所述各场氧化区之间的窗口;
适当地蚀刻所述氧化层和所述各场氧化区，使所述衬底在所述各窗口暴露出来;
在所述各场氧化区和各窗口上面形成一硅层，所述硅层在所述间隔的各场氧化区之间与所述衬底接触;
在所述硅层上面形成一硅复合层;
对所述硅层进行处理，促使所述硅层再结晶，从而使所述硅层具有所述衬底的结晶结构，所述再结晶过程是在所述衬底上生长结晶，通过所述各窗口延伸入所述硅层中，再横向延伸入置于所述各氧化层上方的所述硅层中;
形成若干栅极，其中各栅极置于各所述窗口的上方;
往置于所述第一氧化层上方的所述硅层的各区中搀入杂质，以形成所述各场效应晶体的漏区和源区;
于是所述氧化层就把源区和漏区与所述衬底隔离出来。
11、根据权利要求10确定的工艺过程，其特征在于形成所述硅层的所述步骤包括形成一个多晶硅层。
12、根据权利要求10确定的工艺过程，其特征在于形成所述硅层的所述步骤包括形成一非晶硅层的步骤。
13、根据权利要求11或12确定的工艺过程，其特征在于形成所述氧化区的所述步骤包括由所述衬底生长出氧化层的步骤;
14、根据权利要求13确定的工艺过程，其特征在于对所述硅层进行处理，引起所述再结晶的所述步骤包括把所述硅层加热。
15、根据权利要求14确定的工艺过程，其特征在于在形成所述硅层前要把所述氧化区弄平。
16、权利要求10所述的工艺过程，其特征在于，该工艺过程还包括在所述再结晶硅层中形成若干绝缘区的如下步骤：除去某一选定的场氧化区上方的所述硅层的各部分，使第二个氧化层可生长入腾出来的所述各部分，从而使所述第二个氧化层与所述选定的场氧化区接触，其中所述各场氧化区使各场效应晶体管的漏极和源极与其它场效应晶体管的漏极和源极隔离开来。
CN85104551.0A 1985-02-11 1985-06-14 在硅衬底上形成隔离硅区和场效应器件的工艺过程 Expired CN1006261B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US06/700,607 US4654958A (en) 1985-02-11 1985-02-11 Process for forming isolated silicon regions and field-effect devices on a silicon substrate
US06/700,607 1985-02-11

Publications (2)

Publication Number Publication Date
CN85104551A CN85104551A (zh) 1986-12-10
CN1006261B true CN1006261B (zh) 1989-12-27

Family

ID=24814181

Family Applications (1)

Application Number Title Priority Date Filing Date
CN85104551.0A Expired CN1006261B (zh) 1985-02-11 1985-06-14 在硅衬底上形成隔离硅区和场效应器件的工艺过程

Country Status (9)

Country Link
US (1) US4654958A (zh)
JP (1) JPS61187224A (zh)
KR (1) KR860006831A (zh)
CN (1) CN1006261B (zh)
DE (1) DE3603470A1 (zh)
FR (1) FR2577348B1 (zh)
GB (1) GB2170953B (zh)
HK (1) HK37989A (zh)
SG (1) SG86288G (zh)

Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61139058A (ja) * 1984-12-11 1986-06-26 Seiko Epson Corp 半導体製造装置
US5190886A (en) * 1984-12-11 1993-03-02 Seiko Epson Corporation Semiconductor device and method of production
JPS62177909A (ja) * 1986-01-31 1987-08-04 Hitachi Ltd 半導体装置の製造方法
US4717688A (en) * 1986-04-16 1988-01-05 Siemens Aktiengesellschaft Liquid phase epitaxy method
US5214302A (en) * 1987-05-13 1993-05-25 Hitachi, Ltd. Semiconductor integrated circuit device forming on a common substrate MISFETs isolated by a field oxide and bipolar transistors isolated by a groove
US4760036A (en) * 1987-06-15 1988-07-26 Delco Electronics Corporation Process for growing silicon-on-insulator wafers using lateral epitaxial growth with seed window oxidation
JPH01162376A (ja) * 1987-12-18 1989-06-26 Fujitsu Ltd 半導体装置の製造方法
US4997780A (en) * 1988-09-21 1991-03-05 Ncr Corporation Method of making CMOS integrated devices in seeded islands
JPH04226079A (ja) * 1990-04-17 1992-08-14 Canon Inc 半導体装置及びその製造方法及びそれを有する電子回路装置
US5026665A (en) * 1990-12-24 1991-06-25 Motorola Inc. Semiconductor device electrode method
KR100256322B1 (ko) * 1994-03-03 2000-05-15 제니 필더 파울러-노드하임 프로그래밍 및 이레이즈를 이용한 저전압 단일트랜지스터 플래쉬 이이피롬셀
US5543637A (en) * 1994-11-14 1996-08-06 North Carolina State University Silicon carbide semiconductor devices having buried silicon carbide conduction barrier layers therein
US6093936A (en) * 1995-06-07 2000-07-25 Lsi Logic Corporation Integrated circuit with isolation of field oxidation by noble gas implantation
WO1996042112A1 (fr) * 1995-06-12 1996-12-27 Hitachi, Ltd. Circuit integre a semi-conducteur, son procede de fabrication et plaquette semi-conductrice
US6627511B1 (en) * 1995-07-28 2003-09-30 Motorola, Inc. Reduced stress isolation for SOI devices and a method for fabricating
US5693975A (en) * 1995-10-05 1997-12-02 Integrated Device Technology, Inc. Compact P-channel/N-channel transistor structure
JPH1174522A (ja) * 1996-12-19 1999-03-16 Texas Instr Inc <Ti> 絶縁体上にソースとドレインと共にプレーナー型ｆｅｔを形成する方法および装置
KR100269289B1 (ko) * 1997-02-19 2000-10-16 윤종용 실리콘막의결정화방법
KR100240615B1 (ko) * 1997-03-13 2000-01-15 김영환 반도체장치의제조방법
US5972758A (en) * 1997-12-04 1999-10-26 Intel Corporation Pedestal isolated junction structure and method of manufacture
US6281521B1 (en) 1998-07-09 2001-08-28 Cree Research Inc. Silicon carbide horizontal channel buffered gate semiconductor devices
DE69940422D1 (de) * 1999-04-30 2009-04-02 St Microelectronics Srl Herstellungsverfahren für integrierte SOI Schaltkreisstrukturen
KR100319625B1 (ko) * 1999-05-28 2002-01-05 김영환 반도체소자의 제조방법
US20020117718A1 (en) * 2001-02-28 2002-08-29 Apostolos Voutsas Method of forming predominantly <100> polycrystalline silicon thin film transistors
GB0130485D0 (en) * 2001-12-21 2002-02-06 Plastic Logic Ltd Self-aligned printing
KR100525797B1 (ko) * 2003-06-18 2005-11-02 동부아남반도체 주식회사 소자분리막 구조 및 제조 방법
JP2008205053A (ja) * 2007-02-17 2008-09-04 Seiko Instruments Inc 半導体装置

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4269631A (en) * 1980-01-14 1981-05-26 International Business Machines Corporation Selective epitaxy method using laser annealing for making filamentary transistors
US4381201A (en) * 1980-03-11 1983-04-26 Fujitsu Limited Method for production of semiconductor devices
JPS56135969A (en) * 1980-03-27 1981-10-23 Fujitsu Ltd Manufacture of semiconductor device
US4487639A (en) * 1980-09-26 1984-12-11 Texas Instruments Incorporated Localized epitaxy for VLSI devices
NL188550C (nl) * 1981-07-02 1992-07-16 Suwa Seikosha Kk Werkwijze voor het vervaardigen van een halfgeleidersubstraat.
US4637127A (en) * 1981-07-07 1987-01-20 Nippon Electric Co., Ltd. Method for manufacturing a semiconductor device
EP0073487B1 (en) * 1981-08-31 1988-07-20 Kabushiki Kaisha Toshiba Method for manufacturing three-dimensional semiconductor device
US4461670A (en) * 1982-05-03 1984-07-24 At&T Bell Laboratories Process for producing silicon devices
US4497683A (en) * 1982-05-03 1985-02-05 At&T Bell Laboratories Process for producing dielectrically isolated silicon devices
US4566914A (en) * 1983-05-13 1986-01-28 Micro Power Systems, Inc. Method of forming localized epitaxy and devices formed therein

Also Published As

Publication number Publication date
KR860006831A (ko) 1986-09-15
GB8601163D0 (en) 1986-02-19
FR2577348A1 (fr) 1986-08-14
GB2170953A (en) 1986-08-13
DE3603470A1 (de) 1986-08-28
SG86288G (en) 1989-07-14
FR2577348B1 (fr) 1988-11-18
GB2170953B (en) 1988-08-10
JPS61187224A (ja) 1986-08-20
CN85104551A (zh) 1986-12-10
US4654958A (en) 1987-04-07
HK37989A (en) 1989-05-12

Similar Documents

Publication Publication Date Title
CN1006261B (zh) 在硅衬底上形成隔离硅区和场效应器件的工艺过程
US4838993A (en) Method of fabricating MOS field effect transistor
US4945070A (en) Method of making cmos with shallow source and drain junctions
US4716126A (en) Fabrication of double diffused metal oxide semiconductor transistor
US4686758A (en) Three-dimensional CMOS using selective epitaxial growth
JPS5856409A (ja) 半導体装置の製造方法
JPH0640582B2 (ja) 絶縁ゲ−ト電界効果トランジスタの製造方法
JPH0123954B2 (zh)
US5946578A (en) Method of fabricating semiconductor device having source/drain layer raised from substrate surface
US5904535A (en) Method of fabricating a bipolar integrated structure
GB2080024A (en) Semiconductor Device and Method for Fabricating the Same
JPH11163343A (ja) 半導体装置およびその製造方法
JPH04305978A (ja) 電力用ｍｏｓ半導体デバイスの製造方法
JP2515524B2 (ja) 絶縁ゲ―ト電界効果トランジスタの製造方法
JPS62200770A (ja) 絶縁ゲ−ト電界効果トランジスタの製造方法
JPS63133678A (ja) 縦型電界効果トランジスタの製造方法
JPH0350771A (ja) 半導体装置
JPH0750418A (ja) 半導体装置の製造方法
EP0042380B1 (en) Method for achieving ideal impurity base profile in a transistor
JPS6247151A (ja) 相互接続部を基板に形成する方法
JPS6238869B2 (zh)
JPH01293668A (ja) 絶縁ゲート電界効果トランジスタの製造方法
JPH0249019B2 (ja) Handotaisochinoseizohoho
KR0167667B1 (ko) 반도체 제조방법
JPS63117459A (ja) 絶縁ゲート電界効果トランジスタの製造方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C13 Decision
GR02 Examined patent application
C14 Grant of patent or utility model
GR01 Patent grant
C19 Lapse of patent right due to non-payment of the annual fee
CF01 Termination of patent right due to non-payment of annual fee