CN2603517Y - 半导体晶片堆叠构造 - Google Patents

半导体晶片堆叠构造 Download PDF

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CN2603517Y
CN2603517Y CN02294173.8U CN02294173U CN2603517Y CN 2603517 Y CN2603517 Y CN 2603517Y CN 02294173 U CN02294173 U CN 02294173U CN 2603517 Y CN2603517 Y CN 2603517Y
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substrate
plate body
chip
layer wafer
wafer
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CN02294173.8U
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谢志鸿
吴志成
陈炳光
蔡尚节
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Kingpak Technology Inc
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Kingpak Technology Inc
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32135Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors

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  • Wire Bonding (AREA)

Abstract

本实用新型为半导体晶片堆叠构造,其包括有一基板;一下层晶片设置于该基板上,其上设有复数个焊垫;一间隔层设有一板体及位于该板体四周之凸柱,该凸柱黏设于该下层晶片上;一上层晶片黏着固定于该间隔层的板体上,其上形成有复数个焊垫;复数条导线分别用以电连接该下层晶片及上层晶片的焊垫至该基板的讯号输入端;及一封胶层,其设于该基板上,用以将该上、下层晶片及复数条导线包覆住。如是,可减少胶体使用量,以降低生产成本,且可有效避免溢胶之情形,以便于打线作业之进行。

Description

半导体晶片堆叠构造
技术领域
本实用新型为一种晶片堆叠构造,特别指一种可便于将积体电路有效堆叠,在制造上更为便利。
背景技术
在科技的领域,各项科技产品皆以轻、薄、短小为其诉求,因此,对于积体电路的体积越小越理想,更可符合产品的需求。而以往积体电路即使体积再小,亦只能并列式地电连接于电路板上,而在有限的电路板面积上,并无法将积体电路的容置数量有效地提升,是以,欲使产品达到更为轻、薄、短小之诉求,将有其困难之处。
因此,将若干个积体电路予以叠合使用,可达到轻、薄、短小的诉求,然而,若干个积体电路叠合时,上层积体电路将会压到下层积体电路的导线,以致将影响到下层积体电路的讯号传递。
已知一种晶片堆叠构造,请参阅图1,其包括有一基板10、一下层晶片12、一上层晶片14、复数个导线16及一间隔层18。下层晶片12设于基板10上,上层晶片14由间隔层18叠合于下层晶片12上方,使下层晶片12与上层晶片14形成一适当的间距20,如是,复数个导线16即可电连接于下层晶片12边缘,使上层晶片14叠合于下层晶片12上时,不致于压损复数个导线16。
然而,此种结构的间隔层18,整个面涂布胶体22,再将其黏着固定于下层晶片12上,如是,其必使用较多的胶体22,以致造成制造成本的提高;再者,使用胶体22的量较多时,亦容易造成溢胶的现像,使溢胶覆盖住下层晶片12的焊垫24,而影响到讯号的传递效果。
有鉴于此,本创作人乃本于精益求精、创新突破的精神,而创作出本实用新型半导体晶片堆叠构造,可有效改进晶片堆叠制程,使其制造上更为便利,而降低生产成本。
发明内容
本实用新型的主要目的,在于提供一种半导体晶片堆叠构造,其可具有减少胶体用量的情形,以达到降低生产成本的目的。
本实用新型的另一目的,在于提供一种半导体晶片堆叠构造,其具有降低溢胶的功效,以达到提高电性传递效果的目的。
为达上述的目的,本实用新型的特征在于包括有一基板;一下层晶片设置于该基板上,其上设有复数个焊垫;一间隔层设有一板体及位于该板体四周的凸柱,该凸柱黏设于该下层晶片上;一上层晶片黏着固定于该间隔层的板体上,而该上表面形成有复数个焊垫;复数条导线,其分别用以电连接该下层晶片及上层晶片的焊垫至该基板的讯号输入端;及一封胶层,其设于该基板的上表面上,用以将该上、下层晶片及复数条导线包覆住。
如是,可减少胶体使用的量,以降低生产成本,且可有效避免溢胶的情形,以便于打线作业的进行。
如是,即可达到上述本实用新型的目的及功效,使其更为实用。
本实用新型的上述及其他目的、优点和特色由以下较佳实施例的详细说明并参考图式俾得以更深入了解。
附图说明
图1为已知半导体晶片堆叠构造的示意图。
图2为本实用新型半导体晶片堆叠构造的的分解图。
图3为本实用新型半导体晶片堆叠构造的的组合剖视图。图号说明
基板    30        下层晶片    32        间隔层    34
上层晶片  36        复数条导线  38    封胶层      40
第一表面  42        第二表面    44    讯号输入端  46
讯号输出端48        下表面      50    上表面      52
复数个焊垫54        凸柱        56    板体        58
黏胶      60        镂空区      61    下表面      62
上表面    64        复数个焊垫  66    印刷电路板  70
球栅阵列金属球(BGA)             68
具体实施方式
请参阅图2及图3,为本实用新型半导体晶片堆叠构造的立体分解图及剖面图,其包括一基板30、一下层晶片32、间隔层34、一上层晶片36、复数条导线38及一封胶层40:
基板30设有一第一表面42及一第二表面44,第一表面42周缘形成有复数个讯号输入端46,第二表面44形成有一讯号输出端48。
下层晶片32设有一下表面50及一上表面52,下表面50固定于基板30的第一表面42上,上表面52具有复数个焊垫54。
间隔层34设有一板体58及四凸柱56,四凸柱56分别设置于板体58四周,使板体58下方形成有四根凸柱56,而凸柱56由黏胶60黏着于下层晶片32的上表面52,使板体58与下层晶片32间形成一镂空区61,由间隔层34的凸柱56设计,将间隔层34黏着固定于下层晶片32上时,仅需于凸柱56与下层晶片32的黏着位置涂布黏胶60,而可减少黏胶60的使用量,以达到降低成本的目的。再者,减少黏胶60用量的情形下,更可避免溢胶的产生,以降低溢胶污染下层晶片32的焊垫54的情形。
上层晶片36有一下表面62及一上表面64,下表面62黏着固定于间隔层34的板体58上,而上表面64形成有复数个焊垫66。
复数条导线38分别用以电连接下层晶片32及上层晶片36的焊垫54、66至基板30的讯号输入端46,将下层晶片32及上层晶片36的讯号传递至基板30上。
封胶层40设于基板30的第一表面42上,用以将上、下层晶片36、32及复数条导线38包覆住。
另,基板30的第二表面44的讯号输出端48形成有球栅阵列金属球(BGA)68,用以将基板30的讯号传递至印刷电路板70。
是以,如上的构造组合,本实用新型具有如下的优点:
1.由于间隔层34由凸柱56黏着于下层晶片32上,因此,其所需的黏胶用量较少,可有效降低生产成本。
2.由于间隔层34所使用的黏胶较少,可降低溢胶的情形,使下层晶片32的焊垫54不致被溢胶覆盖,而影响到打线作业。
在较佳实施例的详细说明中所提出的具体实施例仅为了易于说明本实用新型的技术内容,并非将本实用新型狭义地限制于实施例,凡依本实用新型的精神及以下申请专利范围的情况所作种种变化实施均属本实用新型的范围。

Claims (3)

1.一种半导体晶片堆叠构造,其特征在于,包括有:
一基板,其设有一第一表面及一第二表面,该第一表面周缘形成有复数个讯号输入端,该第二表面形成有一讯号输出端;
一下层晶片,其设有一下表面及一上表面,该下表面系黏着于该基板的第一表面,该上表面具有复数个焊垫;
一间隔层,其设有一板体及位于板体四周的凸柱,该凸柱黏设于该下层晶片的上表面;
一上层晶片,其具有一下表面及一上表面,该下表面固定于该间隔层的板体上,而该上表面形成有复数个焊垫;
复数条导线,其分别用以电连接该下层晶片及上层晶片的焊垫至该基板的讯号输入端;及
一封胶层,其设于该基板的上表面上,用以将该上、下层晶片及复数条导线包覆住。
2.如权利要求1所述的半导体晶片堆叠构造,其特征在于,该基板的讯号输出端形成有球栅阵列金属球。
3.如权利要求1所述的半导体晶片堆叠构造,其特征在于,该间隔层于该板体周缘形成四根凸柱。
CN02294173.8U 2002-12-27 2002-12-27 半导体晶片堆叠构造 Expired - Fee Related CN2603517Y (zh)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100539131C (zh) * 2007-11-29 2009-09-09 日月光半导体制造股份有限公司 电子元件封装结构

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100539131C (zh) * 2007-11-29 2009-09-09 日月光半导体制造股份有限公司 电子元件封装结构

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