CN2562364Y - Semiconductor package shell and installation structure - Google Patents
Semiconductor package shell and installation structure Download PDFInfo
- Publication number
- CN2562364Y CN2562364Y CN 01231200 CN01231200U CN2562364Y CN 2562364 Y CN2562364 Y CN 2562364Y CN 01231200 CN01231200 CN 01231200 CN 01231200 U CN01231200 U CN 01231200U CN 2562364 Y CN2562364 Y CN 2562364Y
- Authority
- CN
- China
- Prior art keywords
- package casing
- semiconductor package
- circuit substrate
- lead frame
- radiator
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/45124—Aluminium (Al) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The utility model discloses a semiconductor package shell used for surface mounting, which comprises a connection face facing the circuit substrate side during the surface mounting, a package shell 7 made of insulating material and on the outer surface at the back of the connection face, a lead frame 1 with a first face and a second face at the back of the first face, and a semiconductor element 2 arranged on the first face of the lead frame. The lead frame 1 is arranged inside the package shell 7 in a way that the second face thereof is faced to the outer surface of the package shell. The heat produced by the semiconductor element 2 is dissipated to the exterior by the outer surface of the package shell. With the above arrangement, the package shell 7 has no influence on the circuit substrate, so that the circuit substrate has large degree of freedom in material and circuit design.
Description
(1) technical field
The present invention relates to be used for the structure and the mounting structure thereof of the semiconductor package casing of mounted on surface.
(2) background technology
Fig. 3 represents the internal structure as the Transistor packages shell of an example of semiconductor package casing of conventional art.Transistor chip 2 is installed on the 1st of lead frame 1.Below transistor chip 2 is its collector electrode, so lead frame 1 has the function as the collector electrode of transistor chip 2.Simultaneously, lead frame 1 has the function as fin, is the heating based on transistor chip 2, dispels the heat from the 2nd face at the 1st the back side.Lead frame 1 is connected with collector terminal 3.Be connected with grid lead end 5 with emitter terminal end 4 with pressure welding point such as the metal wire 6 of aluminum steel etc. transistor chip 2 upper surfaces.In order to fix the reliability of each lead end and assurance transistor chip 2, the package casing 7 that the insulant of use epoxy resin etc. is made.The stereogram of the package casing 7 of dress Fig. 3 structure in Fig. 4 represents.The lead end of collector terminal 3, emitter terminal 4 and gate terminal 5 and package casing lower surface almost are same planes.Package casing 7 has when mounted on surface towards the joint face of circuit substrate side and the outer surface at the back side thereof.The lower surface of the package casing 7 of Fig. 4 is joint faces.Package casing 7 is connected with circuit substrate in joint face one side.Lead frame 1 is configured in the package casing 7, with its 2nd joint face towards package casing.In to the high-power Transistor packages shell of controlling 7,, the 2nd joint face from package casing of lead frame 1 exposed for the heating that makes transistor chip 2 is dispelled the heat.As previously mentioned, because of the 2nd joint face of lead frame 1, so the heating of transistor chip 2 is mainly distributed towards circuit substrate by the joint face of package casing 7 towards package casing 7.That is to say that being electrically connected path is consistent with thermal dissipating path.Its result, in order to bear the heat from package casing 7, the material of circuit substrate is selected and the degree of freedom of circuit design just is restricted.The present invention is used to solve these problems in the past.
(3) summary of the invention
Mounted on surface of the present invention semiconductor package casing, comprise and have when mounted on surface the package casing of making towards the insulant of the outer surface at the joint face of circuit substrate side and the back side thereof, have the 2nd the lead frame at the 1st and the back side and be installed in semiconductor element on the 1st of lead frame.Aforementioned leadframe configurations is in package casing, with its 2nd outer surface towards package casing.Because of the 2nd outer surface of lead frame, so the heating of semiconductor element is mainly passed through the outer surface of package casing to outside space heat elimination towards package casing.Therefore, circuit substrate is not subjected to the influence of package casing heat radiation, so the material of circuit substrate is selected and the degree of freedom of circuit design increases.
(4) description of drawings
Fig. 1 represents the structure chart of the semiconductor package casing of one embodiment of the invention.
Fig. 2 represents the structure chart of the control device of other embodiment of the present invention.
Fig. 3 represents the structure chart of semiconductor package casing in the past.
Fig. 4 represents the outline drawing of semiconductor package casing in the past.
(5) embodiment
Below, describe implementing embodiments of the invention with reference to accompanying drawing.
Fig. 1 represents the internal structure of the Transistor packages shell of present embodiment.Transistor chip 2 is installed on the 1st of lead frame 1.Below transistor chip 2 is its collector electrode, so lead frame 1 has the function as the collector electrode of transistor chip 2.Simultaneously, lead frame 1 has the function as fin, is the heating based on transistor chip 2, dispels the heat from the 2nd face at the 1st the back side.Lead frame 1 is connected with collector terminal 3.With metal wire 6 pressure welding point above the transistor chip 2 is connected with grid lead end 5 with emitter terminal end 4.In conventional art shown in Figure 3, the leads ends such as the collector terminal that is connected with circuit substrate 3, emitter terminal 4 and gate terminal 5 that form be with the package casing lower surface almost on same plane, but in the present embodiment, be towards the bending of package casing upper surface, and the front end that is shaped is parallel with the package casing upper surface.For the reliability of fixing each lead end and saving transistor chip 2 from damage, the package casing 7 that the insulant of use epoxy resin etc. is made.Package casing 7 has when mounted on surface towards the joint face of circuit substrate side and the outer surface at the back side thereof.The upper surface of the package casing 7 of present embodiment is a joint face.Package casing 7 is connected with circuit substrate in the joint face side.Lead frame 1 is configured in the package casing 7, with its 2nd outer surface towards package casing.In to the high-power Transistor packages shell of controlling 7, for the heating that makes transistor chip 2 is dispelled the heat, the outer surface to a part of the 2nd of major general's lead frame 1 from package casing exposes.In the package casing 7 of present embodiment, because of the 2nd outer surface of lead frame 1 towards package casing 7, so the heating of transistor chip 2 mainly dispel the heat towards space outerpace by the outer surface of package casing 7, towards the part of circuit substrate seldom.Therefore, will be electrically connected path separates with thermal dissipating path.Like this, the degree of freedom of the selected and circuit design of the material of the heat dissipation design degree of freedom of package casing and circuit substrate etc. increases.
Below, with reference to Fig. 1 embodiments of the invention 2 are described.As shown in Figure 1.The upper surface of the semiconductor package casing of present embodiment has collector terminal 3, emitter terminal 4 and gate terminal 5, and will encapsulate above the appearance surface shell and carry out mounted on surface towards the circuit substrate side on circuit substrate.On the other hand, the heat that produces owing to the loss of transistor chip 2, the mainly heat conduction of the 2nd by lead frame 1 and the outer surface of package casing is dispelled the heat from the outer surface of package casing.So, also radiator can be installed in the outer surface of package casing or the 2nd of the lead frame 1 that exposes from the outer surface of package casing on.
Fig. 2 represents the structure of the embodiment of the invention 3.Be with install semiconductor package casing 8 circuit substrate 9 and with the radiator 10 almost parallels configuration of package casing 8 thermal couplings, and aforesaid semiconductor package casing 8 is clipped between the two.Circuit elements device 11 is installed on the circuit substrate 9, so that realize that for example inverter drives function.
Below, with reference to Fig. 2 embodiments of the invention 4 are described.The package casing 8 that is installed on the circuit substrate 9 is clipped between circuit substrate 9 and the radiator 10.Because the flatness in package casing 8 and the radiator 10 and the variation of the depth of parallelism might make the package casing 8 and the conductive coefficient of radiator 10 reduce, thus with high heat transfer medium 12 every between package casing 8 and radiator 10, can prevent the reduction of thermo-contact.Especially,, just can absorb the variation of the flatness and the depth of parallelism, prevent the reduction of thermo-contact by means of carrying out thermal coupling with soft high thermal conductivity layer 12 with flexibility.In addition, replace soft high thermal conductivity layer 12, dose between semiconductor package casing 8 and radiator 10 and the side and the upper surface of semiconductor package casing 8, also can prevent the reduction of thermo-contact with the heat conductivity composite material.In addition, also can be used in when unhardened is that the thermosetting thermally-conductive materials of pasty state replaces soft high thermal conductivity layer 12, dose between semiconductor package casing 8 and radiator 10 and the side and the upper surface of semiconductor package casing 8, prevent the reduction of thermo-contact.In addition, replace soft high thermal conductivity layer 12, dose between semiconductor package casing 8 and radiator 10 and the side and the upper surface of semiconductor package casing 8, also can prevent the reduction of thermo-contact with gelatinous thermally-conductive materials.In addition, replace the transistor chip 2 of aforesaid three ends, also can obtain identical effect with the composite component of the diode at two ends or transistor AND gate diode.Terminal is formed on the single face of semiconductor package casing, is flat shape, replace in the processing that is shaped, forming collector terminal 3, emitter terminal 4 and the gate terminal 5 of the pin-type of terminal, also can obtain identical effect.In addition, insert the resin with heat conductivity and insulation property of enough degree of depth, till control basal plate is imbedded, by further improving heat-conductive characteristic like this.
Claims (7)
1. a semiconductor package casing that carries out mounted on surface on circuit substrate comprises
Have when mounted on surface the package casing of making towards the insulant of the outer surface at the joint face of circuit substrate side and the back side thereof,
The 2nd lead frame with the 1st and back side,
Be installed on the 1st of lead frame semiconductor element and
Be fixed on a plurality of ends that are electrically connected with semiconductor element on the package casing,
It is characterized in that,
The leadframe configurations that will on the 1st semiconductor element be installed is in package casing, with its 2nd outer surface towards package casing.
2. semiconductor package casing as claimed in claim 1 is characterized in that,
Outer surface to a part of the 2nd of major general's lead frame from package casing is exposed to the outside.
3. a control device comprises
The circuit substrate of mounted on surface semiconductor package casing as claimed in claim 1 and
The outside is installed in the radiator on the package casing outer surface,
It is characterized in that,
Circuit substrate, semiconductor package casing and radiator are parallel in the horizontal direction.
4. control device as claimed in claim 3 is characterized in that,
Between semiconductor package casing and radiator, soft high thermal conductivity layer is set.
5. control device as claimed in claim 3 is characterized in that,
Between semiconductor package casing and radiator, the heat conductivity composite material is set.
6. control device as claimed in claim 3 is characterized in that,
Between semiconductor package casing and radiator, being arranged on when unhardened is the thermosetting thermally-conductive materials of pasty state.
7. control device as claimed in claim 3 is characterized in that,
Between semiconductor package casing and radiator, gelatinous thermally-conductive materials is set.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP232640/2000 | 2000-08-01 | ||
| JP2000232640A JP2002050722A (en) | 2000-08-01 | 2000-08-01 | Semiconductor package and application device thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN2562364Y true CN2562364Y (en) | 2003-07-23 |
Family
ID=18725290
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 01231200 Expired - Fee Related CN2562364Y (en) | 2000-08-01 | 2001-08-01 | Semiconductor package shell and installation structure |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JP2002050722A (en) |
| CN (1) | CN2562364Y (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100442482C (en) * | 2003-12-09 | 2008-12-10 | 万国半导体股份有限公司 | Inverted J-lead package for power devices |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4453498B2 (en) | 2004-09-22 | 2010-04-21 | 富士電機システムズ株式会社 | Power semiconductor module and manufacturing method thereof |
| JP2007163012A (en) * | 2005-12-13 | 2007-06-28 | Toshiba Kyaria Kk | Outdoor unit of refrigerating cycle device |
| JP5590015B2 (en) * | 2011-12-02 | 2014-09-17 | 三菱電機株式会社 | Inverter device and air conditioner equipped with the same |
| JP5974988B2 (en) | 2013-06-21 | 2016-08-23 | 株式会社デンソー | Electronic equipment |
| JP5999041B2 (en) | 2013-07-23 | 2016-09-28 | 株式会社デンソー | Electronic equipment |
| JP6183314B2 (en) | 2014-07-31 | 2017-08-23 | 株式会社デンソー | Electronic device and drive device including the same |
| CN110462827A (en) * | 2017-04-03 | 2019-11-15 | 三菱电机株式会社 | Switch element driving unit |
| EP4368037A1 (en) * | 2021-07-08 | 2024-05-15 | Japan Tobacco, Inc. | Power supply unit for aerosol generation device |
-
2000
- 2000-08-01 JP JP2000232640A patent/JP2002050722A/en active Pending
-
2001
- 2001-08-01 CN CN 01231200 patent/CN2562364Y/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100442482C (en) * | 2003-12-09 | 2008-12-10 | 万国半导体股份有限公司 | Inverted J-lead package for power devices |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2002050722A (en) | 2002-02-15 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20030723 Termination date: 20090901 |