JP2002050722A - Semiconductor package and application device thereof - Google Patents
Semiconductor package and application device thereofInfo
- Publication number
- JP2002050722A JP2002050722A JP2000232640A JP2000232640A JP2002050722A JP 2002050722 A JP2002050722 A JP 2002050722A JP 2000232640 A JP2000232640 A JP 2000232640A JP 2000232640 A JP2000232640 A JP 2000232640A JP 2002050722 A JP2002050722 A JP 2002050722A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor package
- heat
- control device
- radiator
- package
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/45124—Aluminium (Al) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、トランジスタなど
の表面実装用途の半導体パッケージ構造およびその実装
方法に関するものである。[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor package structure for surface mounting such as a transistor and a mounting method thereof.
【０００２】[0002]
【従来の技術】従来この種の半導体パッケージは、第３
図に示すような内部構造、および第４図に示すような外
形構成である。同図において、表面実装型のトランジス
タパッケージとして、一般的なＴＯ−２２０（ＳＭ）
（ＥＩＡＪ規格）などで代表される表面実装パッケージ
における例を示している。この種のパッケージは、第３
図に示すように、リードフレーム１上にシリコン材料な
どからなるトランジスタチップ２が搭載されている。こ
のトランジスタチップ２がＩＧＢＴ（Insulated gate b
ipolar transistor)の場合には、Ｄ−ＭＯＳプロセスで
実現されており、トランジスタチップ２下面がコレクタ
端子３となり、トランジスタチップ２上面に設けたコン
タクトパッドとエミッタリード端子４およびゲートリー
ド端子５とがアルミ線などの金属ワイヤー６で接続され
ているものである。また、リード端子の固定およびトラ
ンジスタチップ２の信頼性性能保全のために、エポキシ
樹脂などによるパッケージ７が用いられていた。また、
とくに大電力を制御するトランジスタパッケージ７で
は、トランジスタチップ２での損失による放熱を良好に
行う為に、チップコレクタのリードフレーム１を放熱器
として使用する様に、パッケージ７の下面（図上では下
面）にリードフレーム１が露出する構成である。なお、
トランジスタチップ２がＩＧＢＴでなく、ＢＪＴ(bipol
ar junction transistor)やＦＥＴ(field effect trans
istor)を搭載する場合やＦＲＤ（first recovery dio
de）とのマルチチップ搭載の場合であっても、ほぼ同様
の構成となっている。この構成の半導体パッケージで
は、図４に示すように、コレクタ端子３、エミッタ端子
４、ゲート端子５のリード端子が下面にあり、またリー
ドフレーム１による放熱板がコレクタ電極と共用となっ
ていた。リードフレーム１上にシリコン材料などからな
るトランジスタチップ２が搭載されている。2. Description of the Related Art Conventionally, this type of semiconductor package has
It has an internal structure as shown in the figure and an outer configuration as shown in FIG. In the figure, a general TO-220 (SM) is used as a surface mount transistor package.
(EIAJ standard) is shown as an example in a surface mount package represented by, for example. This type of package is
As shown in the figure, a transistor chip 2 made of a silicon material or the like is mounted on a lead frame 1. This transistor chip 2 is an IGBT (Insulated gate b)
In the case of an ipolar transistor, the transistor chip 2 is realized by a D-MOS process, and the lower surface of the transistor chip 2 serves as the collector terminal 3, and the contact pad provided on the upper surface of the transistor chip 2, the emitter lead terminal 4, and the gate lead terminal 5 are made of aluminum. They are connected by metal wires 6 such as wires. Further, a package 7 made of epoxy resin or the like has been used for fixing the lead terminals and maintaining the reliability performance of the transistor chip 2. Also,
In particular, in the transistor package 7 that controls a large amount of power, the lower surface of the package 7 (the lower surface in the drawing) is used so that the lead frame 1 of the chip collector is used as a radiator in order to satisfactorily dissipate heat due to the loss in the transistor chip 2. ), The lead frame 1 is exposed. In addition,
If the transistor chip 2 is not an IGBT but a BJT (bipol
ar junction transistor) or FET (field effect trans)
istor) or FRD (first recovery dio)
Even in the case of multi-chip mounting with de), the configuration is almost the same. In the semiconductor package having this configuration, as shown in FIG. 4, the lead terminals of the collector terminal 3, the emitter terminal 4, and the gate terminal 5 are provided on the lower surface, and the radiator plate of the lead frame 1 is shared with the collector electrode. A transistor chip 2 made of a silicon material or the like is mounted on a lead frame 1.
【０００３】このため、回路基板などに表面実装するに
は、電極が同一の方向にあり、表面実装には適している
が、放熱面とコレクタ電極が共用している為に、電気的
接続系と放熱（伝熱）系を共用することが必要となる。For surface mounting on a circuit board or the like, the electrodes are in the same direction and are suitable for surface mounting. However, since the heat radiation surface and the collector electrode are shared, the electrical connection system is not used. And a heat dissipation (heat transfer) system.
【０００４】[0004]
【発明が解決しようとする課題】しかしながら、図４に
おける従来の構成では、放熱面とコレクタ電極が共用し
ている為に、電気的接続系と放熱（伝熱）系を共用する
ため回路基板における熱伝導性能が要求され、通常の回
路基板材料より高価なアルミ基材やセラミック基材の回
路基板が用いられる事が一般的であった。また、熱伝導
設計と電気接続（大電流の接続）が同一回路基板にて実
施することが必要なために、回路部品実装の設計が放熱
設計優先となり、制御装置として大型化するとともに電
力配線の引き回し長が長くなり回路ロスや発生ノイズ面
で不利となるばかりでなく、実装設計上制約を受けると
いった課題を有していた。However, in the conventional configuration shown in FIG. 4, since the heat dissipation surface and the collector electrode are shared, the electrical connection system and the heat dissipation (heat transfer) system are used in common for the circuit board. Generally, a circuit board made of an aluminum base material or a ceramic base material, which is required to have high heat conduction performance and is more expensive than a normal circuit board material, is used. In addition, since heat conduction design and electrical connection (connection of large current) need to be performed on the same circuit board, the design of circuit component mounting has a priority on heat dissipation design, so that the control device becomes large and power wiring becomes large. In addition to the disadvantage that the length of the wiring is long and disadvantageous in terms of circuit loss and generated noise, there is a problem that there is a restriction in mounting design.
【０００５】本発明はこのような従来の課題を解決する
ものであり、熱伝導系と電気接続を分離することによ
り、前記課題を解決することを目的とする。The present invention has been made to solve such a conventional problem, and an object of the present invention is to solve the above-mentioned problem by separating a heat conduction system from an electric connection.
【０００６】[0006]
【課題を解決するための手段】上記課題を解決するため
に本発明は、複数の端子を有する半導体素子などを内蔵
する表面実装パッケージにおいて、伝熱による放熱経路
と独立する信号経路を設けるものである。SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention provides a surface mount package including a semiconductor element having a plurality of terminals, in which a signal path independent of a heat radiation path by heat transfer is provided. is there.
【０００７】上記、放熱経路と電力経路を分離すること
によって、放熱設計と回路基板設計とが独立となり、放
熱器として安価なものが使用でき、かつ制御基板として
も一般的な基材が使用できるばかりでなく、制御装置が
小型化することが出来るとともに、回路部品レイアウト
が最適化出来るためにロスが低減するとともに、発生ノ
イズの低減といった効果が得られる。By separating the heat radiating path from the power path, the heat radiating design and the circuit board design become independent, an inexpensive radiator can be used, and a general substrate can be used as the control substrate. In addition, the control device can be reduced in size, and the layout of the circuit components can be optimized, so that the effects of reducing the loss and reducing the generated noise can be obtained.
【０００８】[0008]
【発明の実施の形態】第１の発明の実施の形態は、複数
の端子を有する半導体素子をなどを内蔵する表面実装パ
ッケージにおいて、伝熱による放熱経路と独立する信号
（電力）経路（リード端子）を設けたことを特徴とする
半導体パッケージであり、回路基板に実装することが容
易となる。DESCRIPTION OF THE PREFERRED EMBODIMENTS The first embodiment of the present invention relates to a signal (power) path (lead terminal) independent of a heat radiation path by heat transfer in a surface mount package incorporating a semiconductor element having a plurality of terminals or the like. ) Is provided, and can be easily mounted on a circuit board.
【０００９】また、第２の発明の実施の形態は、回路基
板に表面実装のパッケージにおいて複数電極（端子）を
具備し、外部回路との接続において、すべての電極を電
気接続基板面との接続を同一面で接続するように形成
し、なおかつ熱伝導による放熱面を前記電極面とことな
る面から主に行うことにより、回路基板と放熱器と機能
分割でき、制御装置の構成が容易となる。In a second embodiment of the present invention, a circuit board is provided with a plurality of electrodes (terminals) in a surface mount package, and all electrodes are connected to an electric connection board surface in connection with an external circuit. Are formed so as to be connected on the same surface, and the heat radiation surface due to heat conduction is mainly performed from the surface different from the electrode surface, so that the function can be divided into the circuit board and the radiator, and the configuration of the control device becomes easy. .
【００１０】また、第３の発明の実施の形態は、前記半
導体パッケージを実装することにより、回路基板と、前
記パッケージと、放熱器をおおむね平行にかつ、両者間
に前記半導体パッケージを配置することができ、制御装
置の構成が容易となる。In a third embodiment of the present invention, the semiconductor package is mounted, and the circuit board, the package, and the radiator are arranged substantially in parallel with each other, and the semiconductor package is disposed therebetween. And the configuration of the control device becomes easy.
【００１１】また、第４の発明の実施の形態は、前記半
導体パッケージと放熱器との間を低硬度高熱伝導性シー
トにて熱接合したことにより、実装時の寸法変動・傾き
・位置ずれや温度変動による変形時の熱伝導性を確保す
ることができ、制御装置の構成を容易にする事ができ
る。In a fourth embodiment of the present invention, the semiconductor package and the radiator are thermally joined with a low-hardness and high-thermal-conductivity sheet. Thermal conductivity at the time of deformation due to temperature fluctuation can be ensured, and the configuration of the control device can be simplified.
【００１２】また、第５の発明の実施の形態は、前記半
導体パッケージと放熱器との間を熱伝導性コンパウンド
材で充填したことにより、実装時の寸法変動・傾き・位
置ずれや温度変動による変形時の熱伝導性を確保するこ
とができ、制御装置の構成を容易にする事ができる。The fifth embodiment of the present invention is characterized in that the space between the semiconductor package and the radiator is filled with a thermally conductive compound material, so that dimensional fluctuations, inclinations, positional deviations during mounting, and temperature fluctuations are caused. Thermal conductivity at the time of deformation can be ensured, and the configuration of the control device can be simplified.
【００１３】また、第６の発明の実施の形態は、前記半
導体パッケージと放熱器との間を未硬化時にペースト状
の硬化熱伝導性材で充填したことにより、実装時の寸法
変動・傾き・位置ずれや温度変動による変形時の熱伝導
性を確保することができ、制御装置の構成を容易にする
事ができる。In a sixth embodiment of the present invention, the space between the semiconductor package and the radiator is filled with a paste-like cured heat conductive material when uncured, so that the dimensional variation, inclination, Thermal conductivity at the time of deformation due to displacement or temperature fluctuation can be ensured, and the configuration of the control device can be simplified.
【００１４】また、第７の発明の実施の形態は、前記半
導体パッケージと放熱器との間をゲル状の熱伝導性材で
充填したことにより、実装時の寸法変動・傾き・位置ず
れや温度変動による変形時の熱伝導性を確保することが
でき、制御装置の構成を容易にする事ができる。According to a seventh embodiment of the present invention, the space between the semiconductor package and the radiator is filled with a gel-like heat conductive material, so that dimensional fluctuation, inclination, displacement and temperature during mounting can be improved. Thermal conductivity at the time of deformation due to fluctuation can be ensured, and the configuration of the control device can be simplified.
【００１５】また、第８の発明の実施の形態は、前記半
導体パッケージを実装した回路基板と前記パッケージと
熱接合された放熱器とからなる制御装置である。An eighth embodiment of the present invention is a control device comprising a circuit board on which the semiconductor package is mounted and a radiator thermally bonded to the package.
【００１６】また、第９の発明の実施の形態は、前記半
導体パッケージを実装した回路基板と前記パッケージと
熱接合された放熱器とからなる制御装置を具備した空気
調和機である。A ninth embodiment of the present invention is an air conditioner including a control device including a circuit board on which the semiconductor package is mounted and a radiator thermally bonded to the package.
【００１７】[0017]
【実施例】以下本発明の実施例について図面を参照して
説明する。Embodiments of the present invention will be described below with reference to the drawings.
【００１８】（実施例１）図１は、本発明の第１の実施
例を示す構成図である。同図に示すように、リードフレ
ーム１上にシリコン材料などからなるトランジスタチッ
プ２が搭載されている。このトランジスタチップがＩＧ
ＢＴ（Insulated gate bipolar transistor)の場合に
は、Ｄ−ＭＯＳプロセスで実現されており、チップ下面
がコレクタ３となり、チップ上面のコンタクトパッドと
エミッタリード端子４およびゲートリード端子５とが金
属ワイヤー６で接続されているものである。外部回路と
接続するコレクタ端子３、エミッタ端子４およびゲート
端子５は、従来例を示す図３では、図中でのパッケージ
下面とほぼ同一面に形成されていたが、本発明の実施例
では、それぞれ図１に示すように図中のパッケージ上面
とほぼ同一面になるようにフォーミングされている。ま
た、各リード端子の固定およびトランジスタチップ２の
性能保全のために、エポキシ樹脂などによるパッケージ
７を用いている。また、とくに大電力を制御するトラン
ジスタパッケージでは、トランジスタチップでの損失に
よる放熱を良好に行う為に、コレクタのリードフレーム
１を放熱器として使用する様に、パッケージ７の側面
（図中では下面）に露出する構成である。なお、トラン
ジスタがＩＧＢＴでなく、ＢＪＴ(bipolar junction tr
ansistor)やＦＥＴ(field effect transistor)を搭載す
る場合やＦＲＤ（first recovery diode）とのマルチ
チップ搭載の場合であっても、ほぼ同様の構成となって
いる。この構成の半導体パッケージでは、図１に示すよ
うに、コレクタ端子３、エミッタ端子４、ゲート端子５
のリード端子が上面にあり、またリードフレーム１によ
る放熱板がコレクタ電極と共用となっている。(Embodiment 1) FIG. 1 is a block diagram showing a first embodiment of the present invention. As shown in FIG. 1, a transistor chip 2 made of a silicon material or the like is mounted on a lead frame 1. This transistor chip is IG
In the case of a BT (Insulated gate bipolar transistor), it is realized by a D-MOS process, the lower surface of the chip becomes the collector 3, and the contact pad on the upper surface of the chip, the emitter lead terminal 4 and the gate lead terminal 5 are formed by the metal wire 6. What is connected. Although the collector terminal 3, the emitter terminal 4, and the gate terminal 5 connected to the external circuit are formed on substantially the same plane as the lower surface of the package in FIG. 3 showing the conventional example, in the embodiment of the present invention, As shown in FIG. 1, each is formed so as to be substantially flush with the upper surface of the package in the figure. Also, a package 7 made of epoxy resin or the like is used for fixing each lead terminal and maintaining the performance of the transistor chip 2. In particular, in a transistor package that controls a large amount of power, a side surface (a lower surface in the figure) of the package 7 is used such that the lead frame 1 of the collector is used as a radiator in order to satisfactorily dissipate heat due to loss in the transistor chip. It is a configuration to be exposed to. Note that the transistor is not an IGBT but a BJT (bipolar junction tr).
The configuration is almost the same even when an anistor or FET (field effect transistor) is mounted or when a multichip with a FRD (first recovery diode) is mounted. In the semiconductor package having this configuration, as shown in FIG. 1, the collector terminal 3, the emitter terminal 4, the gate terminal 5
Are located on the upper surface, and the heat radiating plate of the lead frame 1 is shared with the collector electrode.
【００１９】そして、この実施例によれば、放熱経路と
電力経路を分離することによって、放熱設計と回路基板
設計とが分離することができ、放熱器として安価なもの
が使用でき、かつ制御基板としても一般的な基材が使用
できるばかりでなく、制御装置が小型化することが出来
るとともに、部品レイアウトが最適化出来るためにロス
が低減するとともに、発生ノイズの低減といった効果を
得ることができる。According to this embodiment, by separating the heat radiation path and the power path, the heat radiation design and the circuit board design can be separated, an inexpensive radiator can be used, and the control board can be used. Not only can a general base material be used, but also the control device can be reduced in size, and the layout can be optimized to reduce the loss and reduce the noise generated. .
【００２０】（実施例２）また、図１を用いて、本発明
の第２の実施例を説明する。同図において、コレクタ端
子３、エミッタ端子４、ゲート端子５などの電極（端
子）を図中上面に具備し、外部回路との接続において、
おおむねすべての電極をパッケージ７の（図中）上面に
もうけ、電気接続基板面との接続を行うように形成して
いる。一方、トランジスタチップ２におけるロスによる
発熱を、リードフレーム１からの熱伝導による放熱を下
面から主に行うように各端子をフォーミングし、かつリ
ードフレームを形成したものである。Embodiment 2 A second embodiment of the present invention will be described with reference to FIG. In the figure, electrodes (terminals) such as a collector terminal 3, an emitter terminal 4, and a gate terminal 5 are provided on the upper surface in the figure, and in connection with an external circuit,
Almost all the electrodes are formed on the upper surface (in the figure) of the package 7 so as to be connected to the surface of the electric connection substrate. On the other hand, each terminal is formed and a lead frame is formed so that heat generated by loss in the transistor chip 2 is mainly released from the lower surface by heat conduction from the lead frame 1.
【００２１】そして、この実施例によれば、外部放熱器
との熱結合をパッケージ下面でおこない、放熱を下面で
主におこない、上面に設けたコレクタ端子３、エミッタ
端子４、ゲート端子５の各端子と外部制御基板間を接続
を上面で行うことができ、制御装置の構成が容易になる
といった効果を得ることができる。According to this embodiment, thermal coupling with the external radiator is performed on the lower surface of the package, heat radiation is mainly performed on the lower surface, and each of the collector terminal 3, the emitter terminal 4, and the gate terminal 5 provided on the upper surface. The connection between the terminal and the external control board can be made on the upper surface, and the effect of simplifying the configuration of the control device can be obtained.
【００２２】（実施例３）図２は、本発明の第３の実施
例を示す構成図である。前記半導体パッケージ８をはん
だなどにより実装した回路基板９と前記パッケージ８と
熱接合した放熱器１０とをおおむね平行に、かつ両者間
に前記半導体パッケージ８を配置したものである。ま
た、回路基板９上には、トランジスタを駆動するために
周辺回路部品１１が実装されており、回路基板９上にお
いてたとえばインバータ駆動機能を実現するものであ
る。(Embodiment 3) FIG. 2 is a block diagram showing a third embodiment of the present invention. A circuit board 9 on which the semiconductor package 8 is mounted by soldering or the like and a radiator 10 thermally bonded to the package 8 are substantially parallel to each other, and the semiconductor package 8 is disposed therebetween. A peripheral circuit component 11 is mounted on the circuit board 9 to drive the transistor, and realizes, for example, an inverter driving function on the circuit board 9.
【００２３】そして、この実施例によれば、電気接続系
と放熱系を分離することが容易に実現できるために、装
置の小型化、配線の短縮による低ノイズ化、低ロス化を
実現することができる。According to this embodiment, since the electrical connection system and the heat radiation system can be easily separated, it is possible to reduce the size of the device and reduce noise and loss by shortening the wiring. Can be.
【００２４】（実施例４）図２を用いて、本発明の第４
の実施例について説明する。同図において、回路基板９
上に実装された（トランジスタ）パッケージ８は、回路
基板９と放熱器１０とに挟まれた構造となっている。こ
のため、パッケージ８や放熱器１０における平面度や平
行度の変動により、パッケージ８と放熱器１０との熱伝
達率が低下することが懸念される。そこで、パッケージ
８と放熱器１０との間に高熱伝達媒体１２を介在させ
て、熱接触の低下を防止するものである。とくに、柔軟
性をもつ低硬度高熱伝導性シート１２にて熱結合するこ
とにより、平面度や平行度の変動を吸収しながら、かつ
放熱特性そして、この実施例によれば、電気接続系と放
熱系を分離することが容易に実現できるために、装置の
小型化、配線の短縮による低ノイズ化、低ロス化を実現
することができる。(Embodiment 4) Referring to FIG.
An example will be described. In FIG.
The (transistor) package 8 mounted thereon has a structure sandwiched between a circuit board 9 and a radiator 10. For this reason, there is a concern that the heat transfer coefficient between the package 8 and the radiator 10 may be reduced due to a change in flatness or parallelism in the package 8 or the radiator 10. Therefore, a high heat transfer medium 12 is interposed between the package 8 and the radiator 10 to prevent a decrease in thermal contact. In particular, by thermally bonding with the low hardness and high thermal conductivity sheet 12 having flexibility, heat dissipation characteristics while absorbing fluctuations in flatness and parallelism, and according to this embodiment, the electric connection system and heat dissipation Since the system can be easily separated, it is possible to reduce the size of the device and reduce noise and loss by shortening the wiring.
【００２５】また、低硬度高熱伝導性シート１２の代り
に半導体パッケージ８と放熱器１０との間および半導体
パッケージ８側面および上面を熱伝導性コンパウンド材
で充填し、熱結合しても可能である。Alternatively, instead of the low hardness and high heat conductive sheet 12, the space between the semiconductor package 8 and the radiator 10, and the side and top surfaces of the semiconductor package 8 may be filled with a heat conductive compound and thermally bonded. .
【００２６】また、低硬度高熱伝導性シート１２の代り
に半導体パッケージ８と放熱器１０との間および半導体
パッケージ８側面および上面をペースト状の硬化熱伝導
性材で充填し、熱結合しても可能である。In place of the low-hardness and high-heat-conductivity sheet 12, the space between the semiconductor package 8 and the radiator 10 and the side and top surfaces of the semiconductor package 8 may be filled with a paste-like cured heat-conductive material and thermally bonded. It is possible.
【００２７】また、低硬度高熱伝導性シート１２の代り
に半導体パッケージ８と放熱器１０との間および半導体
パッケージ８側面および上面をゲル状の熱伝導性材で充
填し、熱結合しても可能である。Also, instead of the low hardness and high thermal conductive sheet 12, the space between the semiconductor package 8 and the radiator 10 and the side and top surfaces of the semiconductor package 8 may be filled with a gel-like thermal conductive material and thermally bonded. It is.
【００２８】なお、上記３端子のトランジスタチップ２
の代わりに、２端子のダイオードやトランジスタとダイ
オードとの複合素子であっても同様の効果を得ることが
できる。The three-terminal transistor chip 2
Instead, the same effect can be obtained even with a two-terminal diode or a composite element of a transistor and a diode.
【００２９】また、リード足タイプのフォーミング処理
で端子を形成したコレクタ端子３、エミッタ端子４、ゲ
ート端子５の代わりに、端子を半導体パッケージの片面
に平面状形成しても同様の効果を得ることができる。The same effect can be obtained by forming terminals on one surface of the semiconductor package in place of the collector terminal 3, the emitter terminal 4, and the gate terminal 5 which are formed by a lead foot type forming process. Can be.
【００３０】また、熱伝導でかつ絶縁性能をもつ樹脂
を、たとえば制御基板が埋まるまでの十分な深さまで充
填することにより、より熱伝導性能を高めることがで
き、小型化できるといった効果を奏する。Further, by filling a resin having heat conduction and insulating properties to a sufficient depth, for example, until the control board is buried, the heat conduction performance can be further improved and the size can be reduced.
【００３１】[0031]
【発明の効果】上記実施例から明らかなように、請求項
１に記載の発明は、複数の端子を有する半導体素子など
を内蔵する表面実装パッケージにおいて、伝熱による放
熱経路と独立する信号（電力）経路（リード端子）を設
けるもので、この構成によれば、放熱経路と電力経路を
分離することができ、放熱設計と回路基板設計とが独立
となり、放熱器として安価なものが使用でき、かつ制御
基板としても一般的な基材が使用できるばかりでなく、
制御装置を小型化することが出来るとともに、部品レイ
アウトが最適化出来るためにロスが低減するとともに、
発生ノイズの低減といった効果を奏する。As is apparent from the above embodiment, the invention according to the first aspect of the present invention provides a signal (power) independent of a heat dissipation path by heat transfer in a surface mount package incorporating a semiconductor element having a plurality of terminals. ) A path (lead terminal) is provided. According to this configuration, the heat radiation path and the power path can be separated, the heat radiation design and the circuit board design become independent, and an inexpensive heat radiator can be used. And not only can a general substrate be used as a control board,
The controller can be miniaturized, and the component layout can be optimized to reduce losses,
This has the effect of reducing generated noise.
【００３２】請求項２に記載の発明は、表面実装のパッ
ケージにおいて複数電極（端子）を具備し、外部回路と
の接続において、すべての電極を電気接続基板面との接
続を同一面で接続をおこない、かつ熱伝導による放熱を
前記電極面側とことなる面から主に行うもので、この構
成によれば、放熱経路と電力経路を分離することがで
き、放熱設計と回路基板設計とが独立となり、放熱器と
して安価なものが使用でき、かつ制御基板としても一般
的な基材が使用できるばかりでなく、制御装置が小型化
することが出来るという効果を奏する。According to a second aspect of the present invention, in a surface mount package, a plurality of electrodes (terminals) are provided, and in connection with an external circuit, all electrodes are connected to the electric connection board surface on the same surface. In this configuration, the heat radiation by heat conduction is mainly performed from the surface different from the electrode surface side. According to this configuration, the heat radiation path and the power path can be separated, and the heat radiation design and the circuit board design are independent. Thus, an inexpensive radiator can be used, and not only a general base material can be used as the control board, but also the control device can be downsized.
【００３３】請求項３に記載の発明は、前記半導体パッ
ケージと電気的接続した回路基板と、前記半導体パッケ
ージと、放熱器とをおおむね平行に、かつ両者間に前記
半導体パッケージを配置したもので、この構成によれば
放熱設計と回路基板設計とが独立となり、放熱器として
安価なものが使用でき、かつ制御基板としても一般的な
基材が使用できるばかりでなく、制御装置が小型化する
ことが出来るとともに、部品レイアウトが最適化出来る
ためにロスが低減するとともに、発生ノイズの低減とい
った効果を奏する。According to a third aspect of the present invention, a circuit board electrically connected to the semiconductor package, the semiconductor package, and a radiator are arranged substantially parallel to each other, and the semiconductor package is disposed between the two. According to this configuration, the heat radiation design and the circuit board design become independent, an inexpensive radiator can be used, and not only a general substrate can be used as the control board, but also the control device can be downsized. And the layout can be optimized, thereby reducing the loss and reducing the generated noise.
【００３４】請求項４に記載の発明は、前記半導体パッ
ケージと放熱器との間を低硬度高熱伝導性シートにて熱
結合したもので、この構成によれば、半導体パッケージ
における平面度や半導体パッケージの傾きを容易に吸収
しながら、良好な熱伝導を実現することが可能であると
いう効果を奏する。According to a fourth aspect of the present invention, the semiconductor package and the radiator are thermally coupled with a low-hardness and high-thermal-conductivity sheet. This makes it possible to achieve good heat conduction while easily absorbing the inclination of.
【００３５】請求項５に記載の発明は、前記半導体パッ
ケージと放熱器との間を熱伝導性コンパウンド材で充填
し熱結合したもので、この構成によれば、半導体パッケ
ージにおける平面度や半導体パッケージの傾きを容易に
吸収しながら、良好な熱伝導を実現することが可能であ
るという効果を奏する。According to a fifth aspect of the present invention, the space between the semiconductor package and the radiator is filled with a thermally conductive compound material and thermally coupled. This makes it possible to achieve good heat conduction while easily absorbing the inclination of.
【００３６】請求項６に記載の発明は、前記半導体パッ
ケージと放熱器との間を未硬化時にペースト状の硬化熱
伝導性材で充填したもので、この構成によれば、半導体
パッケージにおける平面度や半導体パッケージの傾きを
容易に吸収しながら、良好な熱伝導を実現することが可
能であるという効果を奏する。According to a sixth aspect of the present invention, the space between the semiconductor package and the radiator is filled with a paste-like hardened heat conductive material when the semiconductor package is not yet hardened. And good thermal conduction can be realized while easily absorbing the inclination of the semiconductor package.
【００３７】請求項７に記載の発明は、前記半導体パッ
ケージと放熱器との間をゲル状の熱伝導性材で充填した
もので、この構成によれば、半導体パッケージにおける
平面度や半導体パッケージの傾きを容易に吸収しなが
ら、良好な熱伝導を実現することが可能であるという効
果を奏する。According to a seventh aspect of the present invention, the space between the semiconductor package and the radiator is filled with a gel-like heat conductive material. This has the effect that it is possible to realize good heat conduction while easily absorbing the inclination.
【００３８】請求項８に記載の発明は、前記半導体パッ
ケージと放熱器を具備した主にインバータ駆動の制御装
置であり、制御装置の小型化が可能となるとともに、実
装設計が最適化出来るためにロスが低減するとともに、
発生ノイズの低減といった効果を奏する。The invention according to claim 8 is a control device mainly driven by an inverter, which is provided with the semiconductor package and a radiator. The control device can be downsized and the mounting design can be optimized. Loss is reduced,
This has the effect of reducing generated noise.
【００３９】請求項９に記載の発明は、前記半導体パッ
ケージと放熱器を具備した主にインバータ駆動の制御装
置により駆動される圧縮機モータなどを搭載した空気調
和機であり、制御装置の小型化が可能となるとともに、
実装設計が最適化出来るためにロスが低減するととも
に、発生ノイズの低減といった効果を奏する。According to a ninth aspect of the present invention, there is provided an air conditioner equipped with a compressor motor or the like which is mainly driven by an inverter-driven control device and includes the semiconductor package and a radiator. Is possible,
Since the mounting design can be optimized, the loss is reduced and the generated noise is reduced.
【図１】本発明の一実施例を示す半導体パッケージの構
造図FIG. 1 is a structural view of a semiconductor package showing one embodiment of the present invention.
【図２】本発明の他の実施例を示す制御装置の構造図FIG. 2 is a structural diagram of a control device showing another embodiment of the present invention.
【図３】従来の半導体パッケージのの構造図FIG. 3 is a structural diagram of a conventional semiconductor package.
【図４】従来の半導体パッケージの外形図FIG. 4 is an external view of a conventional semiconductor package.
１ リードフレーム ２ トランジスタチップ ３ コレクタ端子 ４ エミッタ端子 ５ ゲート端子 ６ 金属ワイヤー ８ 半導体パッケージ ９ 制御基板 １０ 放熱器 １２ 低硬度高熱伝導性シート DESCRIPTION OF SYMBOLS 1 Lead frame 2 Transistor chip 3 Collector terminal 4 Emitter terminal 5 Gate terminal 6 Metal wire 8 Semiconductor package 9 Control board 10 Heat sink 12 Low hardness high thermal conductive sheet
Claims (9)
内蔵する表面実装パッケージにおいて、伝熱による放熱
経路と信号経路とを独立に設けたことを特徴とする半導
体パッケージ。1. A semiconductor package having a semiconductor device having a plurality of terminals therein, wherein a heat dissipation path for heat transfer and a signal path are provided independently.
を具備し、外部回路との接続を同一面で接続し、かつ熱
伝導による放熱を前記電極面側と異なる面から主に行う
ことを特徴とする請求項１記載の半導体パッケージ。2. A surface-mounted package comprising a plurality of electrodes, connected to an external circuit on the same surface, and radiating heat by heat conduction mainly from a surface different from the electrode surface side. The semiconductor package according to claim 1.
パッケージを電気的接続した回路基板と、前記半導体パ
ッケージと、放熱器とをおおむね平行に、かつ前記半導
体パッケージを前記回路基板と前記放熱器の間に配置し
た事を特徴とする制御装置。3. A circuit board electrically connected with the semiconductor package according to claim 1, the semiconductor package, and a radiator being substantially parallel to each other, and the semiconductor package being connected to the circuit board. A control device characterized by being arranged between radiators.
の間を低硬度高熱伝導性シートにて熱結合したことを特
徴とする請求項３記載の制御装置。4. The control device according to claim 3, wherein the semiconductor package and the radiator are thermally coupled with a low hardness and high thermal conductivity sheet.
の間を熱伝導性コンパウンド材で充填し、熱結合したこ
とを特徴とする請求項３記載の制御装置。5. The control device according to claim 3, wherein a space between the semiconductor package and the radiator is filled with a thermally conductive compound material and thermally coupled.
の間を未硬化時にペースト状の硬化熱伝導性材で充填
し、熱結合したことを特徴とする請求項３記載の制御装
置。6. The control device according to claim 3, wherein a space between the semiconductor package and the radiator is filled with a paste-like cured heat conductive material when not cured and thermally bonded.
の間をゲル状の熱伝導性材で充填し、熱結合したことを
特徴とする請求項３記載の制御装置。7. The control device according to claim 3, wherein a space between the semiconductor package and the radiator is filled with a gel-like heat conductive material and thermally connected.
御装置を具備したインバータ制御装置。8. An inverter control device comprising the control device according to claim 3. Description:
備した空気調和機。9. An air conditioner comprising the inverter control device according to claim 8.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000232640A JP2002050722A (en) | 2000-08-01 | 2000-08-01 | Semiconductor package and application device thereof |
| CN 01231200 CN2562364Y (en) | 2000-08-01 | 2001-08-01 | Semiconductor package shell and installation structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000232640A JP2002050722A (en) | 2000-08-01 | 2000-08-01 | Semiconductor package and application device thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2002050722A true JP2002050722A (en) | 2002-02-15 |
Family
ID=18725290
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2000232640A Pending JP2002050722A (en) | 2000-08-01 | 2000-08-01 | Semiconductor package and application device thereof |
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| Country | Link |
|---|---|
| JP (1) | JP2002050722A (en) |
| CN (1) | CN2562364Y (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
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| JP2007163012A (en) * | 2005-12-13 | 2007-06-28 | Toshiba Kyaria Kk | Outdoor unit of refrigerating cycle device |
| US7723846B2 (en) | 2004-09-22 | 2010-05-25 | Fuji Electric Device Technology Co., Ltd. | Power semiconductor module and method of manufacturing the same |
| JP2013118754A (en) * | 2011-12-02 | 2013-06-13 | Mitsubishi Electric Corp | Inverter device and air conditioner equipped with the same |
| DE102014107703A1 (en) | 2013-06-21 | 2014-12-24 | Denso Corporation | Electronic device |
| DE102014109874A1 (en) | 2013-07-23 | 2015-01-29 | Denso Corporation | Electronic element and electronic device |
| DE102015213781A1 (en) | 2014-07-31 | 2016-02-04 | Denso Corporation | Electronic device and drive device containing the same |
| WO2018185805A1 (en) * | 2017-04-03 | 2018-10-11 | 三菱電機株式会社 | Switching element drive unit |
| WO2023281713A1 (en) * | 2021-07-08 | 2023-01-12 | 日本たばこ産業株式会社 | Power supply unit for aerosol generation device |
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| US7633140B2 (en) * | 2003-12-09 | 2009-12-15 | Alpha And Omega Semiconductor Incorporated | Inverted J-lead for power devices |
-
2000
- 2000-08-01 JP JP2000232640A patent/JP2002050722A/en active Pending
-
2001
- 2001-08-01 CN CN 01231200 patent/CN2562364Y/en not_active Expired - Fee Related
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| US7723846B2 (en) | 2004-09-22 | 2010-05-25 | Fuji Electric Device Technology Co., Ltd. | Power semiconductor module and method of manufacturing the same |
| US8158458B2 (en) | 2004-09-22 | 2012-04-17 | Fuji Electric Co., Ltd. | Power semiconductor module and method of manufacturing the same |
| DE102005040058B4 (en) | 2004-09-22 | 2019-02-21 | Fuji Electric Co., Ltd. | Power semiconductor module and method for producing the same |
| JP2007163012A (en) * | 2005-12-13 | 2007-06-28 | Toshiba Kyaria Kk | Outdoor unit of refrigerating cycle device |
| JP2013118754A (en) * | 2011-12-02 | 2013-06-13 | Mitsubishi Electric Corp | Inverter device and air conditioner equipped with the same |
| US9431318B2 (en) | 2013-06-21 | 2016-08-30 | Denso Corporation | Electronic device |
| DE102014107703A1 (en) | 2013-06-21 | 2014-12-24 | Denso Corporation | Electronic device |
| US9756716B2 (en) | 2013-07-23 | 2017-09-05 | Denso Corporation | Electronic element and electronic device |
| DE102014109874A1 (en) | 2013-07-23 | 2015-01-29 | Denso Corporation | Electronic element and electronic device |
| DE102015213781A1 (en) | 2014-07-31 | 2016-02-04 | Denso Corporation | Electronic device and drive device containing the same |
| US10374490B2 (en) | 2014-07-31 | 2019-08-06 | Denso Corporation | Electronic device and drive device including the same |
| WO2018185805A1 (en) * | 2017-04-03 | 2018-10-11 | 三菱電機株式会社 | Switching element drive unit |
| CN110462827A (en) * | 2017-04-03 | 2019-11-15 | 三菱电机株式会社 | Switch element driving unit |
| US10893610B2 (en) | 2017-04-03 | 2021-01-12 | Mitsubishi Electric Cornoration | Switching device driving unit |
| WO2023281713A1 (en) * | 2021-07-08 | 2023-01-12 | 日本たばこ産業株式会社 | Power supply unit for aerosol generation device |
| JP7551925B2 (en) | 2021-07-08 | 2024-09-17 | 日本たばこ産業株式会社 | Aerosol generator power supply unit |
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