CN217822780U - 多圈引脚扁平封装结构 - Google Patents

多圈引脚扁平封装结构 Download PDF

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CN217822780U
CN217822780U CN202221260068.XU CN202221260068U CN217822780U CN 217822780 U CN217822780 U CN 217822780U CN 202221260068 U CN202221260068 U CN 202221260068U CN 217822780 U CN217822780 U CN 217822780U
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陈永金
林河北
阳小冬
解维虎
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Shenzhen Jinyu Semiconductor Co ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

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Abstract

本实用新型技术方案公开了一种多圈引脚扁平封装结构,包括金属基岛层及设置于金属基岛层一侧的金属引脚层,金属基岛层下方,及金属引脚层背面均设有散热层,金属基岛层及金属引脚层正面均设有电镀层,金属引脚层及与金属基岛层通过连筋错位排列连接,电镀层上贴装设有粘结剂,粘结剂上贴装设有集成电路,集成电路与金属引脚层通过金属线连接,金属引脚层、散热层、金属基岛层、连筋、电镀层、粘结剂、集成电路及金属线外围通过塑封料包封。本实用新型技术方案解决了现有技术中芯片封装的引线框架IO设计数量无法满足芯片IO数量需求的问题。

Description

多圈引脚扁平封装结构
技术领域
本实用新型技术方案涉及封装结构领域,特别涉及一种多圈引脚扁平封装结构。
背景技术
随着芯片设计小型化和功能更丰富,使封装尺寸越来越小,IO数量要求最多。作为集成电路封装主要载体引线框架,受于设计加工尺寸和工作安全间距要求限制,在同等的封装尺寸下,引线框架IO设计数量无法满足芯片IO数量需求。
实用新型内容
本实用新型技术方案旨在至少在一定程度上解决相关技术中的技术问题之一。为此,本实用新型技术方案的主要目的在于提供一种多圈引脚扁平封装结构,旨在解决现有技术中芯片封装的引线框架IO设计数量无法满足芯片IO数量需求的问题。
为实现上述目的,本实用新型技术方案提供一种多圈引脚扁平封装结构,包括金属基岛层及设置于所述金属基岛层一侧的金属引脚层,所述金属基岛层下方,及所述金属引脚层背面均设有散热层,所述金属基岛层及所述金属引脚层正面均设有电镀层,所述金属引脚层及与所述金属基岛层通过连筋错位排列连接,所述电镀层上贴装设有粘结剂,所述粘结剂上贴装设有集成电路,所述集成电路与所述金属引脚层通过金属线连接,所述金属引脚层、散热层、金属基岛层、连筋、电镀层、粘结剂、集成电路及金属线外围通过塑封料包封。
在其中一个实施例中,金属引脚层、金属线及所述连筋均为铜材质结构。
在其中一个实施例中,塑封料为环氧树脂包封结构。
在其中一个实施例中,散热层为锡材及镍钯金散热涂层结构。
在其中一个实施例中,金属线为高导电的铜、银微米细线结构。
在其中一个实施例中,金属引脚层内的引脚可容纳数量至少为28个。
本实用新型技术方案的有益效果如下:
本实用新型技术方案提出的多圈引脚扁平封装结构,采用错位排列的方式,使引脚尽可能的集中排布,从而解决I0数量瓶颈的问题。
附图说明
为了更清楚地说明本实用新型技术方案实施例或现有技术中的实用新型技术方案,下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图仅仅是本实用新型技术方案的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图示出的结构获得其他的附图。
图1为本实用新型技术方案中的集成电路及各金属引脚层和各部件整体剖面示意图。
图2为现有技术引脚排布结构。
图3为本实用新型技术方案的引脚排布结构。
【主要部件/组件附图标记说明表】
标号 名称 标号 名称
1 金属引脚层 5 粘结剂
2 金属线 6 连筋
3 金属基岛层 7 塑封料
4 集成电路 8 电镀层
具体实施方式
为了使本实用新型技术方案的目的、实用新型技术方案的优点更加清楚明白,下面将结合本实用新型技术方案实施例中的附图,对本实用新型技术方案实施例中的实用新型技术方案进行清楚、完整地描述。显然,所描述的实施例仅仅是本实用新型技术方案的一部分实施例,而不是全部的实施例。
基于本实用新型技术方案中的实施例,本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例,都属于本实用新型技术方案保护的范围。
需要说明,本实用新型技术方案实施例中所有方向性指示(例如上、下、左、右、前、后……)仅用于解释在某一特定状态(如附图所示)下各部件之间的相对位置关系、运动情况等,如果该特定姿态发生改变时,则该方向性指示也相应地随之改变。
在本实用新型技术方案中如涉及“第一”、“第二”等的描述仅用于描述目的,而不能理解为指示或暗示其相对重要性或者隐含指明所指示的技术特征的数量。由此,限定有“第一”、“第二”的特征可以明示或者隐含地包括至少一个该特征。
在本实用新型技术方案的描述中,“多个”的含义是至少两个,例如两个,三个等,除非另有明确具体的限定。
在本实用新型技术方案中,除非另有明确的规定和限定,术语“连接”、“固定”等应做广义理解,例如,“固定”可以是固定连接,也可以是可拆卸连接,或一体成型;可以是机械连接,也可以是电连接;可以是直接相连,也可以通过中间媒介间接相连,可以是两个元件内部的连通或两个元件的相互作用关系,除非另有明确的限定。对于本领域的普通技术人员而言,可以根据具体情况理解上述术语在本实用新型技术方案中的具体含义。
另外,本实用新型技术方案中各个实施例之间的实用新型技术方案可以相互结合,但是必须是以本领域普通技术人员能够实现为基础,当实用新型技术方案的结合出现相互矛盾或无法实现时应当认为这种实用新型技术方案的结合不存在,也不在本实用新型技术方案要求的保护范围之内。
本实用新型技术方案的具体实施例如下:
结构包括金属引脚层1,金属引脚层1背面设置有散热层,金属基岛层3,金属基岛层3下设置有散热层,金属引脚层1和金属基岛层3正面设置有表面处理电镀层8,金属引脚层1和金属基岛层3通过连筋6采用空间错位方式连接,表面处理电镀层8上贴装有粘结剂5,粘结剂5上方贴装集成电路4,集成电路4和金属引脚层1通过金属线2连接,金属引脚层1,散热层,金属基岛层3,连筋6,表面处理电镀层8,粘结剂5,集成电路4和金属线2外围包封有塑封料7。
在相同封装尺寸4mmx4mm内,传统设计引脚排布数量只有单排,IO围绕基岛四周排布,可容纳的IO最大数量是28个,通过本技术,引脚采用多排布,成倍提高IO数量。
本实用新型技术方案的工作原理如下:
多圈引脚扁平封装结构,采用错位排列的方式,使引脚尽可能的集中排布,从而解决I0数量瓶颈的问题。
以上仅为本实用新型技术方案的优选实施例,并非因此限制本实用新型技术方案的专利范围,凡是在本实用新型技术方案的实用新型技术方案构思下,利用本实用新型技术方案说明书及附图内容所作的等效结构变换,或直接/间接运用在其他相关的技术领域均包括在本实用新型技术方案的专利保护范围内。

Claims (6)

1.一种多圈引脚扁平封装结构,其特征在于,包括金属基岛层及设置于所述金属基岛层一侧的金属引脚层,所述金属基岛层下方,及所述金属引脚层背面均设有散热层,所述金属基岛层及所述金属引脚层正面均设有电镀层,所述金属引脚层及与所述金属基岛层通过连筋错位排列连接,所述电镀层上贴装设有粘结剂,所述粘结剂上贴装设有集成电路,所述集成电路与所述金属引脚层通过金属线连接,所述金属引脚层、散热层、金属基岛层、连筋、电镀层、粘结剂、集成电路及金属线外围通过塑封料包封。
2.根据权利要求1所述的多圈引脚扁平封装结构,其特征在于,所述金属引脚层、金属线及所述连筋均为铜材质结构。
3.根据权利要求1所述的多圈引脚扁平封装结构,其特征在于,所述塑封料为环氧树脂包封结构。
4.根据权利要求1所述的多圈引脚扁平封装结构,其特征在于,所述散热层为锡材及镍钯金散热涂层结构。
5.根据权利要求1所述的多圈引脚扁平封装结构,其特征在于,所述金属线为高导电的铜、银微米细线结构。
6.根据权利要求1所述的多圈引脚扁平封装结构,其特征在于,所述金属引脚层内的引脚可容纳数量至少为28个。
CN202221260068.XU 2022-05-24 2022-05-24 多圈引脚扁平封装结构 Active CN217822780U (zh)

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