CN204314581U - 一种阵列基板、显示面板和显示装置 - Google Patents

一种阵列基板、显示面板和显示装置 Download PDF

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CN204314581U
CN204314581U CN201520012864.5U CN201520012864U CN204314581U CN 204314581 U CN204314581 U CN 204314581U CN 201520012864 U CN201520012864 U CN 201520012864U CN 204314581 U CN204314581 U CN 204314581U
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electrode
pixel electrode
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李盼
李文波
乔勇
程鸿飞
先建波
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BOE Technology Group Co Ltd
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Abstract

本实用新型公开了一种阵列基板、显示面板和显示装置，以解决现有技术中，亚像素单元所包括的梳状像素电极的尖端放电对周围的数据线、栅线及相邻像素电极放电，从而对相邻的所述亚像素单元造成干扰，影响显示效果的问题。所述阵列基板，包括衬底基板，所述衬底基板上形成有亚像素单元阵列，所述亚像素单元包括至少在边缘处为梳齿结构的像素电极，所述像素电极的至少一个边缘处设置有屏蔽电极，所述屏蔽电极与所述像素电极的梳齿结构的尖端电连接。

Description

一种阵列基板、显示面板和显示装置
技术领域
本实用新型涉及液晶显示技术领域，尤其涉及一种阵列基板、显示面板和显示装置。
背景技术
薄膜晶体管液晶显示器(Thin Film Transistor Liquid Crystal Display，TFT-LCD)具有厚度薄、功耗低、无辐射等特点，近年来得到了迅速地发展，在当前的平板显示器市场中占据了主导地位。目前，TFT-LCD在各种大中小尺寸的产品上得到了广泛的应用，几乎涵盖了当今信息社会的主要电子产品，在较大尺寸的产品上的应用如液晶电视和高清晰度数字电视。
现有技术中，为了实现多畴显示，需要把亚像素单元的像素电极设计成梳齿结构或者于少边缘为梳齿结构。但是，具有该梳齿结构的像素电极会对相邻的亚像素电极、栅线和数据线产生尖端放电，从而对相邻的亚像素单元形成较大的干扰，影响显示面板的显示效果。
实用新型内容
本实用新型的目的是提供一种阵列基板、显示面板和显示装置，以解决现有技术中，亚像素单元所包括的梳状电极的尖端放电对周围的数据线、栅线及相邻的所述亚像素单元造成干扰的问题。
本实用新型的目的是通过以下技术方案实现的：
本实用新型实施例提供一种阵列基板，包括衬底基板，所述衬底基板上形成有亚像素单元阵列，所述亚像素单元包括至少在边缘处为梳齿结构的像素电极，所述像素电极的至少一个边缘处设置有屏蔽电极，所述屏蔽电极与所述像素电极的梳齿结构的尖端电连接。本实施例中，在所述像素电极的至少一个边缘处设置所述屏蔽电极，从而消除所述像素电极的尖端放电对周围的所述数据线、所述栅线及相邻的所述亚像素单元造成的干扰。
优选的，每两行所述亚像素单元为一个亚像素单元组，每一个所述亚像素单元组的两行所述亚像素单元之间设置有两条栅线；
所述亚像素单元组的上一行所述亚像素单元的所述像素电极至少于上边缘处设置所述屏蔽电极，所述亚像素单元组的下一行所述亚像素单元的所述像素电极至少于下边缘处设置所述屏蔽电极。本实施例中，对于双栅驱动的亚像素单元阵列，由于相邻所述亚像素单元组之间所述像素电极距离较近，因此至少在所述亚像素单元组的上下两边设置所述屏蔽电极，从而使相邻所述亚像素单元组之间的干扰被屏蔽。
优选的，所述像素电极包括沿列方向由上至下排布的梳状的第一像素电极和第二像素电极，属于同一行的所述亚像素单元的所述第一像素电极和所述第二像素电极之间设置有一条栅线。
优选的，所述第一像素电极的上边缘处设置所述屏蔽电极，所述第二像素电极的下边缘处设置所述屏蔽电极。本实施例中，列方向上相邻两行所述亚像素单元之间的干扰被屏蔽。
优选的，所述第一像素电极的上边缘处及至少一个侧边缘处设置所述屏蔽电极，所述第二像素电极的下边缘处及至少一个侧边缘处设置所述屏蔽电极。本实施例中，列方向和行方向上相邻两行所述亚像素单元之间的干扰被屏蔽。
优选的，所述第一像素电极和所述第二像素电极的全部边缘处设置所述屏蔽电极。本实施例中，各所述亚像素单元之间、及所述第一像素电极和所述第二像素电极之间的干扰被屏蔽。
优选的，所述屏蔽电极与所述第一像素电极和所述第二像素电极同层设置。本实施例中，在同一层设置所述屏蔽电极、所述第一像素电极和所述第二像素电极，节省工序。
优选的，所述屏蔽电极的材料为ITO或IZO。
本实用新型实施例有益效果如下：在所述像素电极的至少一个边缘处设置所述屏蔽电极，从而消除所述像素电极的尖端放电对周围的所述数据线、所述栅线及相邻的所述亚像素单元造成的干扰，从而提高显示面板的显示效果。
本实用新型实施列提供一种显示面板，包括如上实施例提供的所述阵列基板。
本实用新型实施例有益效果如下：在所述像素电极的至少一个边缘处设置所述屏蔽电极，从而消除所述像素电极的尖端放电对周围的所述数据线、所述栅线及相邻的所述亚像素单元造成的干扰，从而提高显示面板的显示效果。
本实用新型实施列提供一种显示装置，包括如上实施例提供的所述显示面板。
本实用新型实施例有益效果如下：在所述像素电极的至少一个边缘处设置所述屏蔽电极，从而消除所述像素电极的尖端放电对周围的所述数据线、所述栅线及相邻的所述亚像素单元造成的干扰，从而提高显示面板的显示效果。
附图说明
图1为本实用新型提供的亚像素单元的结构示意图；
图2为本实用新型提供的优选的一种阵列基板的结构示意图；
图3为本实用新型提供的优选的另一种阵列基板的结构示意图；
图4为基于图3提供的第一种具体的阵列基板的结构示意图；
图5为基于图3提供的第二种具体的阵列基板的结构示意图；
图6为基于图3提供的第三种具体的阵列基板的结构示意图。
具体实施方式
下面结合说明书附图对本实用新型实施例的实现过程进行详细说明。需要注意的是，自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。下面通过参考附图描述的实施例是示例性的，仅用于解释本实用新型，而不能理解为对本实用新型的限制。
本实用新型实施例提供一种阵列基板，包括衬底基板，衬底基板上形成有亚像素单元阵列，如图1所示的亚像素单元1的结构示意图，亚像素单元1包括像素电极2和屏蔽电极3，像素电极2至少在边缘处为梳齿结构，像素电极2的至少一个边缘处设置屏蔽电极3，且屏蔽电极3与像素电极2的梳齿结构的尖端电连接。需要说明的是，像素电极2可以仅在边缘处为梳齿结构，也可以整体为梳齿结构，屏蔽电极3可以设置于像素电极2的一个边缘，也设置于像素电极2的两个边缘或更多边缘。本实用新型实施例中，在像素电极2的至少一个边缘处设置屏蔽电极3，从而消除像素电极2的尖端放电对周围的数据线、栅线及相邻的亚像素单元1造成的干扰。
参见图2，示出了优选的一种阵列基板的示意图，每两行亚像素单元1为一个亚像素单元组4，每一个亚像素单元组4的两行亚像素单元1之间设置有两条栅线5；亚像素单元组4的上一行亚像素单元1的像素电极2至少于上边缘处设置屏蔽电极3，亚像素单元组4的下一行亚像素单元1的像素电极2至少于下边缘处设置屏蔽电极3。本实施例中，对于双栅驱动的亚像素单元阵列，由于相邻亚像素单元组4之间的像素电极2距离较近，因此至少在亚像素单元组4的上下两边设置屏蔽电极3，从而使相邻亚像素单元组4之间的干扰被屏蔽。
参见图3，示出了优选的另一种阵列基板的示意图，像素电极2包括沿列方向由上至下排布的梳状的第一像素电极21和第二像素电极22，属于同一行的亚像素单元1的第一像素电极21和第二像素电极22之间设置有一条栅线5；第一像素电极21至少于上边缘处设置屏蔽电极3，第二像素电极22至少于下边缘处设置屏蔽电极3。本实施例中，至少在像素电极2的上下两边(例如，第一像素电极21的上边缘和第二像素电极22下边缘)设置屏蔽电极3，从而使相邻两行亚像素单元之间的干扰被屏蔽。例如，第一像素电极21的上边缘处设置屏蔽电极，第二像素电极22的下边缘处设置屏蔽电极。本实施例中，列方向上相邻两行亚像素单元之间的干扰被屏蔽。又例如，第一像素电极21的上边缘处及至少一个侧边缘处设置屏蔽电极，第二像素电极22的下边缘处及至少一个侧边缘处设置屏蔽电极。本实施例中，列方向和行方向上相邻两行亚像素单元之间的干扰被屏蔽。又例如，第一像素电极21和第二像素电极22的全部边缘处设置屏蔽电极。本实施例中，各亚像素单元之间、及第一像素电极21和第二像素电极22之间的干扰被屏蔽。
参见图4，基于图3提供第一种较具体的阵列基板，包括衬底基板10，形成于衬底基板10上的亚像素单元阵列，每一个亚像素单元1包括TFT 6、沿列方向排布的梳状的第一像素电极21和第二像素电极22；属于同一行的亚像素单元1的第一像素电极21和第二像素电极22之间设置有一条栅线5，相邻的两列亚像素单元1之间设置有一条数据线7；所述第一像素电极21的上边缘处设置所述屏蔽电极3，所述第二像素电极22的下边缘处设置所述屏蔽电极3。当然，屏蔽电极3也可以设置于第一像素电极21和第二像素电极22的多个边缘，例如图5所示，基于图3提供的第二种较具体的阵列基板，与图4不同之处在于，所述第一像素电极21的上边缘及一个侧边缘处设置所述屏蔽电极3，所述第二像素电极22的下边缘及一个侧边缘处设置所述屏蔽电极3。又例如图6所示，基于图3提供的第三种较具体的阵列基板，与图4不同之处在于，所述第一像素电极21的上边缘及两个侧边缘处设置所述屏蔽电极3，所述第二像素电极22的下边缘及两个侧边缘处设置所述屏蔽电极3。上述图5和图6提供的阵列基板，屏蔽电极3设置于第一像素电极21和第二像素电极22的至少两个边缘处，能够更好的消除亚像素单元1的梳状的第一像素电极21和第二像素电极22的尖端放电对周围的数据线7、栅线5及相邻的亚像素单元1造成的干扰。
优选的，屏蔽电极3与像素电极2同层设置。本实施例中，在同一层设置屏蔽电极3、像素电极2能够节省工序。
优选的，屏蔽电极3的材料为ITO或IZO。
本实用新型实施例有益效果如下：在像素电极的至少一个边缘处设置屏蔽电极，从而消除像素电极的尖端放电对周围的数据线、栅线及相邻的亚像素单元造成的干扰，从而提高显示面板的显示效果。
本实用新型实施列提供一种显示面板，包括如上实施例提供的阵列基板。
本实用新型实施例有益效果如下：至在像素电极的至少一个边缘处设置屏蔽电极，从而消除像素电极的尖端放电对周围的数据线、栅线及相邻的亚像素单元造成的干扰，从而提高显示面板的显示效果。
本实用新型实施列提供一种显示装置，包括如上实施例提供的显示面板。
本实用新型实施例有益效果如下：在像素电极的至少一个边缘处设置屏蔽电极，从而消除像素电极的尖端放电对周围的数据线、栅线及相邻的亚像素单元造成的干扰，从而提高显示面板的显示效果。
显然，本领域的技术人员可以对本实用新型进行各种改动和变型而不脱离本实用新型的精神和范围。这样，倘若本实用新型的这些修改和变型属于本实用新型权利要求及其等同技术的范围之内，则本实用新型也意图包含这些改动和变型在内。

Claims (10)

1.一种阵列基板，包括衬底基板，所述衬底基板上形成有亚像素单元阵列，其特征在于，所述亚像素单元包括至少在边缘处为梳齿结构的像素电极，所述像素电极的至少一个边缘处设置有屏蔽电极，所述屏蔽电极与所述像素电极的梳齿结构的尖端电连接。
2.如权利要求1所述的阵列基板，其特征在于，每两行所述亚像素单元为一个亚像素单元组，每一个所述亚像素单元组的两行所述亚像素单元之间设置有两条栅线；
所述亚像素单元组的上一行所述亚像素单元的所述像素电极至少于上边缘处设置所述屏蔽电极，所述亚像素单元组的下一行所述亚像素单元的所述像素电极至少于下边缘处设置所述屏蔽电极。
3.如权利要求1所述的阵列基板，其特征在于，所述像素电极包括沿列方向由上至下排布的梳状的第一像素电极和第二像素电极，属于同一行的所述亚像素单元的所述第一像素电极和所述第二像素电极之间设置有一条栅线。
4.如权利要求3所述的阵列基板，其特征在于，所述第一像素电极的上边缘处设置所述屏蔽电极，所述第二像素电极的下边缘处设置所述屏蔽电极。
5.如权利要求3所述的阵列基板，其特征在于，所述第一像素电极的上边缘处及至少一个侧边缘处设置所述屏蔽电极，所述第二像素电极的下边缘处及至少一个侧边缘处设置所述屏蔽电极。
6.如权利要求3所述的阵列基板，其特征在于，所述第一像素电极和所述第二像素电极的全部边缘处设置所述屏蔽电极。
7.如权利要求2至6任一项所述的阵列基板，其特征在于，所述屏蔽电极与所述像素电极同层设置。
8.如权利要求7所述的阵列基板，其特征在于，所述屏蔽电极的材料为ITO或IZO。
9.一种显示面板，其特征在于，包括如权利要求1至8任一项所述的阵 列基板。
10.一种显示装置，其特征在于，包括如权利要求6所述的显示面板。
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