CN203850273U - 半导体装置 - Google Patents
半导体装置 Download PDFInfo
- Publication number
- CN203850273U CN203850273U CN201420082791.2U CN201420082791U CN203850273U CN 203850273 U CN203850273 U CN 203850273U CN 201420082791 U CN201420082791 U CN 201420082791U CN 203850273 U CN203850273 U CN 203850273U
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- Prior art keywords
- touch panel
- soldered
- semiconductor element
- pedestal
- region
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 227
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 abstract 7
- 230000009286 beneficial effect Effects 0.000 abstract 1
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 description 132
- 238000005476 soldering Methods 0.000 description 57
- 238000013461 design Methods 0.000 description 10
- 238000010586 diagram Methods 0.000 description 9
- 238000000034 method Methods 0.000 description 7
- 238000004519 manufacturing process Methods 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 4
- 238000003466 welding Methods 0.000 description 4
- 238000005538 encapsulation Methods 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000000465 moulding Methods 0.000 description 2
- 238000004080 punching Methods 0.000 description 2
- 230000004913 activation Effects 0.000 description 1
- 230000006978 adaptation Effects 0.000 description 1
- 238000004026 adhesive bonding Methods 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 239000012530 fluid Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 238000010561 standard procedure Methods 0.000 description 1
Classifications
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Abstract
本实用新型涉及半导体装置。本实用新型所要解决的技术问题之一是提供一种具有减小的漂移、倾斜或旋转的半导体管芯。提供了一种半导体装置,其包括:引线框架,其包括电耦接至第一引线的第一接触件,其中所述第一接触件包括所述第一接触件的第一侧上的一个或多个抬高区域,其中每个所述抬高区域包括所述第一接触件的所述第一侧上的平坦表面;半导体管芯,其包括一个或多个第一触板、第二触板和第三触板;第二引线,其电耦接至所述半导体管芯的所述第二触板;和第三引线,其电耦接至所述半导体管芯的所述第三触板。本实用新型可用于电子设备。本实用新型的有利技术效果之一是能够提供一种具有减小的漂移、倾斜或旋转的半导体管芯。
Description
技术领域
本申请案大致涉及电子装置,更具体地涉及半导体装置。
背景技术
半导体工业通常利用不同的方法和结构来形成囊封半导体管芯并且提供用于电连接至半导体管芯的引线的封装。在一种类型的半导体封装中,半导体管芯被安装在引线框架与芯片之间。下引线框架具有上方安装管芯的连续平坦表面,随后芯片用于在管芯顶部上完成电路。这种构造可能提供半导体管芯至下引线框架的不准确定位。此外,相同的不准确定位可能发生于与芯片之间。在安装管芯和芯片期间,焊膏通常用在管芯至引线框架与芯片至管芯之间。在回流焊期间,管芯和芯片都可能移动、漂移、倾斜和/或旋转,其可能降低半导体装置的质量和性能。
因此,需要一种具有减小的漂移、倾斜或旋转的半导体管芯。还需要具有不同的半导体装置,其可各利用相同引线框架设计。
实用新型内容
本实用新型所要解决的技术问题之一是提供一种具有减小的漂移、倾斜或旋转的半导体管芯。
根据本实用新型的一个方面,提供一种半导体装置,所述半导体装置包括:引线框架,其包括电耦接至第一引线的第一接触件,其中所述第一接触件包括所述第一接触件的第一侧上的一个或多个抬高区域,其中每个所述抬高区域包括所述第一接触件的所述第一侧上的平坦表面;半导体管芯,其包括一个或多个第一触板、第二触板和第三触板,其中所述第一触板被安置在所述半导体管芯的第一侧上,且其中每个所述第一触板被焊接至至少一个所述抬高区域,使得每个所述第一触板具有两个或更多个线性边缘,所述线性边缘各自与所述抬高区域上的所述平坦表面的至少一个边缘侧向对准且平行;第二引线,其电耦接至所述半导体管芯的所述第二触板;和第三引线,其电耦接至所述半导体管芯的所述第三触板。
在一种实施方式中,所述第一接触件包括至少两个抬高区域。
在一种实施方式中,所述第一接触件上的每个所述抬高区域被焊接至选自所述第一触板的单独触板。
在一种实施方式中,所述第一接触件包括至少10个抬高区域。
在一种实施方式中,所述引线框架的所述第一接触件的所述第一侧上的所述抬高区域的数量大于被焊接至所述半导体管芯的所述第一触板的所述抬高区域的数量。
在一种实施方式中,所述半导体装置还包括导电夹,所述导电夹被焊接至所述第二触板,其中所述引线框架还包括被焊接至所述导电夹的第二接触件,且其中所述第二接触件电耦接至所述第二引线。
根据本实用新型的另一方面,提供一种半导体装置,所述半导体装置包括:引线框架,其包括电耦接至所述半导体装置的第一引线的第一接触件;导电夹,其电耦接至所述半导体装置上的第二引线,其中所述导电夹包括所述导电夹的第一侧上的一个或多个抬高区域,其中每个所述抬高区域包括所述导电夹的所述第一侧上的平坦表面;和半导体管芯,其包括:所述半导体管芯的第一侧上的第一触板,其中所述第一触板被焊接至所述引线框架上的所述第一接触件;所述半导体管芯的第二侧上的一个或多个第二触板,其中每个所述第二触板被焊接至所述导电夹的所述第一侧上的至少一个所述抬高区域,使得每个所述第二触板具有两个或更多个线性边缘,所述线性边缘各自与所述抬高区域上的所述平坦表面的至少一个边缘侧向对准且平行;和所述半导体管芯上的第三触板,其中所述第三触板电耦接至所述半导体装置的第三引线。
在一种实施方式中,所述导电夹包括至少两个抬高区域。
在一种实施方式中,所述导电夹的所述第一侧上的每个所述抬高区域被焊接至选自所述第二触板的单独触板。
在一种实施方式中,所述引线框架的所述第一接触件包括所述第一接触件的第一侧上的一个或多个第二抬高区域,其中每个所述第二抬高区域包括所述第一接触件的所述第一侧上的平坦表面,且其中所述第一触板被焊接至所述第二抬高区域,使得所述第一触板具有两个或更多个线性边缘,所述线性边缘各自与所述第二抬高区域上的所述平坦表面的至少一个边缘侧向对准且平行。
本实用新型可用于电子设备。本实用新型的有利技术效果之一是能够提供一种具有减小的漂移、倾斜或旋转的半导体管芯。
附图说明
将从具体实施方式和附图中更全面地理解本申请案的实施方案,其不旨在限制本申请案的范围。
图1A是图示根据本申请案的一些实施方案的引线框架的一个实例的透视图。
图1B是根据本申请案的一些实施方案的引线框架的一个实例的俯视图。
图1C是根据本申请案的一些实施方案的引线框架的源极触板的横截面图。
图2A和图2B是分别图示根据本申请案的一些实施方案的半导体管芯200的一个实例的仰视图和俯视图。
图3A是图示根据本申请案的一些实施方案的定位在引线框架100上的半导体管芯200的一个实例的俯视图。
图3B是图示根据本申请案的一些实施方案的定位在引线框架100上的半导体管芯200的横截面图。
图3C是图示根据本申请案的一些实施方案的定位在引线框架100上的半导体管芯200的横截面图,其正交于图3B中的横截面图。
图4是图示根据本申请案的一些实施方案的半导体装置400的一个实例的透视图。
图5A是示出根据本申请案的一些实施方案的包括朝向半导体管芯520延伸的多个基座510的通用导电夹500的一个实例的仰视图。
图5B是根据本申请案的一些实施方案的被焊接至通用导电夹500的半导体管芯521的一个实例的仰视图。
图5C是根据本申请案的一些实施方案的被焊接至通用导电夹500的半导体管芯522的一个实例的仰视图。
图5D是根据本申请案的一些实施方案的被焊接至通用导电夹500的半导体管芯523的一个实例的仰视图。
图5E是根据本申请案的一些实施方案的被焊接至通用导电夹500的半导体管芯524的一个实例的仰视图。
图5F是根据本申请案的一些实施方案的被焊接至通用导电夹500的半导体管芯525的一个实例的仰视图。
图5G是根据本申请案的一些实施方案的被焊接至通用导电夹500的半导体管芯526的一个实例的仰视图。
图5H是根据本申请案的一些实施方案的被焊接至通用导电夹500的半导体管芯527的一个实例的仰视图。
图5I是根据本申请案的一些实施方案的被焊接至通用导电夹500的半导体管芯528的一个实例的仰视图。
图5J是根据本申请案的一些实施方案的被焊接至通用导电夹500的半导体管芯529的一个实例的仰视图。
图6示出当根据本申请案的一些实施方案构造半导体管芯系列的通用导电夹时的设计考虑的实例。
具体实施方式
为说明的简要和明了起见,图中的元件不一定按比例绘制,且不同图中的相同参考数字指示相同元件。此外,为描述的简要起见,省略众所周知的步骤和元件的描述及细节。如本文中所使用,载流电极意指携载电流穿过装置的装置元件,诸如MOS晶体管的源极或漏极或双极晶体管的发射极或集电极或二极管的阴极或阳极,且控制电极意指控制穿过装置的电流的装置元件,诸如MOS晶体管的栅极或双极晶体管的基极。虽然装置在本文中被说明为特定N通道或P通道装置或特定N型或P型掺杂区域,但是本领域一般技术人员将了解补充装置根据本实用新型也是可行的。本领域一般技术人员将了解如本文中所使用的词“期间”、“同时”和“当…时”并非意指动作在起始动作时立即发生的精确术语,而是可能存在由初始动作起始的反应之间的一些小的但合理的延迟,诸如传播延迟。词“大约”或“大体”的使用意指元件值具有预期非常接近规定值或位置的参数。但是,如本领域中已知,总是存在微小变化,其阻止值或位置完全如所规定。本领域中公认高达大约百分之十(10%)(以及对于半导体掺杂浓度高达百分之二十(20%))的变化被视作偏离精确如所述的理想目标的合理变化。为图的明了起见,装置结构的掺杂区域被图示为具有大致直线边缘和精确的角度边角。但是,本领域技术人员了解由于掺杂剂的扩散和活化,掺杂区域的边缘通常可能不是直线且边角可能不是精确的角度。
下文实施方案的描述本质上只是说明性的且绝不旨在限制本实用新型、其应用或使用。除其它外,本申请案尤其包括一种制作半导体装置的方法,其包括:提供导电基板,导电基板包括导电基板的第一侧上的一个或多个抬高区域,其中每个抬高区域包括导电基板的第一侧上的平坦表面;将焊膏安置在导电基板上的抬高区域上的至少一个平坦表面与半导体管芯的一个或多个触板之间,使得每个触板具有三个或更多个线性边缘,其各与抬高区域上的平坦表面的至少一个边缘侧向对准且平行;和回流焊接焊膏以将抬高区域的至少一部分焊接至触板。
图1A是图示根据本申请案的一些实施方案的引线框架100的一个实例的透视图。引线框架100包括源极接触件110、栅极接触件120和漏极接触件130。源极接触件110包括基座140(也被称作支座或抬高区域),其被安置在源极接触件110的一侧上。引线框架100可例如通过蚀刻或冲压铜或铜合金片而形成。图1B是引线框架100的俯视图。应了解,在典型的封装过程期间,引线框架和其不同接触件(例如,源极接触件110)可互连为引线框架的阵列,其可在处理期间被分割为个别封装。图1B中的虚线描绘可使用标准技术(诸如切割或冲孔)分离引线框架100的切割线。图1C是引线框架100中的源极触板110的横截面图。基座140可被基座140之间的沟槽150隔离。基座140各在引线框架100的相同侧上具有平坦表面。如下文进一步讨论,基座可被构造成与半导体管芯上的触板对准。
在一些实施方案中,基座(例如,基座140)的高度可以是接触件厚度的至少30%。例如,源极接触件可由具有10密尔厚度的铜片形成,且因此基座的高度可为至少3密尔。在一些实施方案中,基座可具有接触件厚度的至少50%的高度。在一些实施方案中,基座可具有至少3密尔或至少5密尔的高度。在一些实施方案中,基座之间的距离(例如,沟槽150的宽度)可至少为基座的高度。在一些实施方案中,基座之间的距离可为接触件厚度的至少30%或接触件厚度的至少50%。例如,基座之间的距离可为至少3密尔或至少5密尔。
基座的形状未具体限制。基座的顶部表面可例如具有多边形表面,诸如正方形、矩形或三角形。在一些实施方案中,每个基座的顶部表面可包括至少一个线性边缘(例如,一个、两个、三个、四个或更多个线性边缘)。例如,如图1B中所示,基座140可为具有四个线性边缘的矩形。基座还可包括至少一个弯曲边缘,例如以适应邻近的栅极接触件。
图2A和图2B是分别图示根据本申请案的一些实施方案的半导体管芯200的一个实例的仰视图和俯视图。半导体管芯200在一侧上包括源极触板210和栅极触板220。半导体管芯200还包括半导体管芯200相对于源极触板210的一侧上的漏极触板230。半导体管芯200可被构造为例如MOSFET。源极触板210可被构造使得每个触板可被焊接至引线框架的源极接触件上的基座(例如,引线框架100的源极接触件110上的基座140)。例如,每个源极触板210可具有与源极接触件110上的基座140中的相应基座相同的形状和尺寸。半导体管芯200可具有被放置在引线框架100上方的底部表面,使得每个源极触板210与基座140之一对准。类似地,半导体管芯200上的栅极触板210可与引线框架100的栅极接触件120对准。
图3A示出图示根据本申请案的一些实施方案的定位在引线框架100上的半导体管芯200的一个实例的俯视图。半导体管芯200用虚线示出且定位在引线框架100上方,使得源极触板210可在基座140上方对准。来自基座140的每个基座包括四个线性边缘,其与触板210中的每个触板的四个线性边缘侧向对准且平行。(基座140的最右基座还包括弯曲边缘,其与源极触板210的最右源极触板的弯曲边缘侧向对准。)栅极触板220还在栅极接触件120上方对准。基座可被焊接至源极触板以将源极接触件110电耦接至源极触板220。
图3B示出图示根据本申请案的一些实施方案的定位在引线框架100上的半导体管芯200的横截面图。焊膏300可被安置在每个源极触板220与基座140之间。焊膏可被施加使得沟槽150大体无焊膏。例如,可在将半导体管芯200定位在引线框架100上之前将焊膏300选择性地施加至基座140,使得焊膏300被夹置在源极触板210与基座140之间。焊膏可类似地被安置在栅极触板220与栅极接触件120之间。
施加在基座与触板之间的焊膏量未具体限制。通常,所施加的焊膏量有效地将触板电耦接至导电表面(例如,引线框架)并且还有效地使得焊膏不在回流焊期间桥接于基座之间。在一些实施方案中,以一层的形式将焊膏均匀施加至将在回流焊期间被焊接的基座或触板的部分。在一些实施方案中,焊膏被施加为具有0.003英寸至0.006英寸厚度的一层。
可通过加热半导体管芯和引线框架以执行回流焊而将基座140焊接至源极触板210。在一些实施方案中,在回流焊期间,焊膏被维持在基座与触板之间。即,焊膏不流动至围绕基座的沟槽中。类似地,被安置在每对触板与基座之间的焊膏的单独层可在回流焊期间保持分隔开。换句话说,焊膏层不流动至邻近两个层的沟槽中,使得来自单独层的焊膏接触彼此。
申请人已发现通过将基座焊接至触板,回流焊期间的漂移、倾斜或旋转可被减小或消除。在不受任何特定理论约束的情况下,相信通过将基座边缘与触板边缘对准,回流焊期间焊料的表面张力和湿粘合性质可维持基座与触板对准。这接着限制或阻止半导体管芯在回流焊期间旋转、倾斜或漂移。
因此,在一些实施方案中,被焊接至基座的每个触板将具有两个或更多个线性边缘,其各与被焊接至触板的基座的线性边缘侧向对准且平行。在一些实施方案中,被焊接至基座的每个触板将具有三个或更多个线性边缘,其各与被焊接至触板的基座的线性边缘侧向对准且平行。在一些实施方案中,被焊接至基座的每个触板将具有四个或更多个线性边缘,其各与被焊接至触板的基座的线性边缘侧向对准且平行。在一些实施方案中,被焊接至基座的每个触板将具有两个或更多个边角,其各与被焊接至触板的基座的边角侧向对准。在一些实施方案中,被焊接至基座的每个触板将具有三个或更多个边角,其各与被焊接至触板的基座的边角侧向对准。在一些实施方案中,被焊接至基座的每个触板将具有四个或更多个边角,其各与被焊接至触板的基座的边角侧向对准。
如将在下文进一步讨论,单个触板可任选地被焊接至两个或更多个基座(例如,两个、三个、四个、五个、六个或更多个基座)。因此,相同触板的不同线性边缘可与不同基座的边缘侧向对准且平行。作为一个实例,矩形触板可被焊接至两个正方形基座。矩形触板可具有两个线性边缘,其与第一正方形基座的两个线性边缘侧向对准且平行。矩形触板的其它两个线性边缘可与第二正方形基座的两个线性边缘侧向对准且平行。因此,在这个特定实例中,矩形触板的所有四个线性边缘与两个不同基座中的线性边缘侧向对准且平行。此外,每个正方形基座包括两个线性边缘,其不与矩形触板的线性边缘侧向对准。这种示例性构造可提供适当粘着以防止回流焊期间的漂移、倾斜或旋转。在一些实施方案中,至少两个触板各被单独焊接至两个或更多个基座。例如,半导体管芯的第一触板(例如,源极触板)可被焊接至引线框架上的接触件(例如,源极接触件)的第一基座和引线框架上的接触件的第二基座,且半导体管芯的第二触板可被焊接至引线框架上的接触件的第三基座和引线框架上的接触件的第四基座。
可使用不同技术将半导体管芯200上的漏极触板230电耦接至引线框架100上的漏极接触件130。例如,漏极触板230可被丝焊至漏极接触件130。在一些实施方案中,可通过导电夹将漏极触板230电耦接至漏极接触件130。导电夹可被焊接至漏极触板230和漏极接触件130两者。图3C是图示定位在引线框架100与导电夹310之间的半导体管芯200的横截面图。图3C中的横截面图正交于图3B中的横截面图。可使用焊膏320将导电夹310的底面焊接至漏极触板230。导电夹310具有U形构造,使得可使用焊膏330将两个末端焊接至引线框架100中的漏极接触件130。通过将导电夹310焊接至漏极接触件130和漏极触板230两者,可将漏极接触件130电耦接至漏极触板230。如图3C中所示,可使用焊膏340将栅极接触件120焊接至栅极触板210。栅极接触件120可大致在执行回流焊以将源极触板220焊接至源极接触件110的同时被焊接至栅极触板210。
可使用大致与上述相同的技术将导电夹焊接至引线框架上的触板(例如,栅极触板)和接触件(例如,栅极接触件)。例如,可将焊膏施加至栅极触板和栅极接触件,且随后可在执行回流焊之前将导电夹定位为接触焊膏。可在执行回流焊以将半导体管芯焊接至引线框架之前、之后或大致同时执行用于焊接导电夹的回流焊。
如上所讨论,引线框架上的基座可减小或阻止回流焊期间的漂移、倾斜或旋转。基座还可用于在将任意导电基板(例如,导电夹或引线框架)焊接至半导体管芯上的触板时阻止或减小漂移、倾斜或旋转。
图4是图示根据本申请案的一些实施方案的半导体装置400的一个实例的透视图。半导体装置400可包括被焊接至导电夹420的源极接触件410。导电夹420具有基座425,其从导电夹420面向半导体管芯430的一侧开始延伸。基座425可被焊接至半导体管芯430上的源极触板435,使得源极接触件410被电耦接至源极触板435。如所示,被焊接至基座的触板的四个线性边缘各与被焊接至触板的基座的线性边缘侧向对准且平行。导电夹上的基座因此可减小或阻止回流焊期间的漂移、倾斜或旋转。漏极接触件440可被焊接至半导体管芯430相对于源极触板435的一侧上的漏极触板(未示出)。栅极接触件450被焊接至导电夹460。半导体管芯430上的栅极触板470还被焊接至导电夹460,使得栅极接触件470被电耦接至栅极触板470。
导电基板上的基座(例如,导电夹420上的基座425)可大致具有与上文针对引线框架上的基座(例如,引线框架100上的基座140)所讨论的相同特性。例如,基座的高度可为导电夹厚度的一半。作为另一个实例,导电基板上的基座数不受限制且可为例如,一个或多个基座(例如,导电基板上的一个、两个、三个、四个、五个、十个、十五个、二十个或更多个基座)。在一些实施方案中,半导体管芯上的至少一个触板(例如,一个、两个、三个、四个或更多个触板)被焊接至导电基板上的两个或更多个基座(例如,两个、三个、四个、五个或更多个基座)。
半导体装置400可大致使用与上文所述相同的技术组装。可将焊膏施加至漏极接触件且随后通过执行回流焊将漏极接触件焊接至半导体管芯上的漏极触板。随后可在将导电夹定位在半导体管芯和引线框架上方之前将焊膏施加至源极触板、栅极触板、源极接触件和栅极接触件。可执行回流焊以焊接导电夹。在一些实施方案中,半导体管芯的触板大约同时被焊接至引线框架和导电夹。
本申请案中公开的半导体装置(例如,半导体装置400)可至少部分囊封在成型材料(例如,树脂)中。在一些实施方案中,成型材料可填充基座之间的沟槽。引线框架和/或导电夹的部分可被暴露用于将半导体管芯电耦接至例如,印刷电路板。
本文公开的一些实施方案涉及一种导电基板,其被构造成与两个或更多个不同的半导体管芯设计(例如,两个、三个、四个、五个或更多个半导体管芯设计)可操作地耦接。通常,每个引线框架或导电夹被定制用于焊接至特定半导体管芯设计。因此,每个半导体管芯设计需要不同的引线框架设计,其必须在制造厂制造或采购。本申请案包括可结合不同类型的半导体管芯设计使用的通用引线框架和/或通用导电夹。这可减少必须在制造厂制造或采购的不同引线框架的数量。
图5A至图5J是图示根据本申请案的一些实施方案的被焊接至不同半导体管芯的通用导电夹500的一个实例的仰视图。参考图5A,通用导电夹500包括多个基座510,其朝向半导体管芯520延伸。半导体管芯520在一侧上具有触板530,其各被焊接至基座510的两个或更多个基座。左上侧触板被焊接至两个基座。左上侧触板具有两个线性边缘,其各与被焊接至左上侧触板的左上侧基座上的边缘侧向对准且平行。左上侧触板和左上侧基座各具有侧向对准的弯曲边缘。弯曲边缘被成形为适应可被电耦接至单独导电夹(未示出)的触板540。左上侧触板还被焊接至左上侧基座下方的第二基座。仅第二基座的顶部表面的一部分被焊接至左上侧触板。第二基座的两个边缘各与左上侧触板的边缘侧向对准且平行。在制造期间,可在将接触触板的部分上将焊膏选择性地施加至第二基座的顶部表面(和仅顶部表面的一部分被焊接至触板的任意其它基座)。
图5A中的每个触板530具有两个或更多个边缘,其各与基座的边缘侧向对准且平行。被焊接至每个触板的基座数不同:左上触板和左下触板各被焊接至两个基座,右上触板和右下触板各被焊接至四个基座。每个触板仅其表面区域的一部分被焊接至基座。在一些实施方案中,安置在基座之间的沟槽上方的触板的部分可能未被焊接。被焊接至基座的每个触板的总表面积可为例如至少40%、至少50%、至少75%或至少90%。被焊接至基座的每个触板的总表面积可为例如不超过100%、不超过95%、不超过90%、不超过80%或不超过70%。在一些实施方案中,被焊接至基座的每个触板的总表面积为40%至100%或50%至95%。
图5A中描绘的基座510中的八个基座未被焊接至触板。如将在下文进一步讨论,这些未焊接基座被设计用于不同的半导体管芯。四个基座被定位为侧向远离半导体管芯520的覆盖区。换句话说,四个基座不被半导体管芯520覆盖。另外四个基座仅部分被半导体管芯520覆盖。
图5B示出被焊接至通用导电夹500的半导体管芯521。半导体管芯521具有相对于半导体管芯520不同的覆盖区和触板构造。但是,在两个半导体管芯中,触板540(例如,栅极触板)具有相同构造。每个触板531被焊接至基座510的四个基座。如所示,每个触板531具有四个边缘,其各与被焊接至触板的基座上的边缘侧向对准且平行。被焊接的八个基座的每一个的整个顶部表面被焊接至触板。十二个基座保持不焊接至半导体管芯531:十个不被半导体管芯531的覆盖区覆盖,而两个被半导体管芯531的覆盖区部分覆盖。
图5C示出被焊接至通用导电夹500的半导体管芯522。半导体管芯522具有不同的覆盖区和触板构造。但是,触板540(例如,栅极触板)相对于半导体管芯520具有相同构造。触板532的左触板被焊接至基座510的两个基座。触板532的右触板被焊接至基座510的四个基座。被焊接至左触板的基座的整个顶部表面被焊接至左触板。被焊接至右触板的两个基座仅其顶部表面的一部分被焊接至右触板。被焊接至右触板的两个基座的整个顶部表面被焊接至右触板。十四个基座保持不焊接至半导体管芯522:十二个不被半导体管芯522的覆盖区覆盖,而两个被半导体管芯522的覆盖区部分覆盖。
图5D示出被焊接至通用导电夹500的半导体管芯523。半导体管芯523具有不同的覆盖区和触板构造。但是,触板540(例如,栅极触板)相对于半导体管芯520具有相同构造。触板533的最左触板被焊接至基座510的六个基座。被焊接至最左触板的基座的整个顶部表面被焊接至最左触板。触板533的最右触板被焊接至基座510的四个基座。被焊接至最右触板的两个基座的整个顶部表面被焊接至最右触板。被焊接至最右触板的两个基座仅其顶部表面的一部分被焊接至最右触板。十四个基座保持不焊接至半导体管芯523:十二个不被半导体管芯523的覆盖区覆盖,而两个被半导体管芯523的覆盖区部分覆盖。
图5E示出被焊接至通用导电夹500的半导体管芯524。半导体管芯524具有不同的覆盖区和触板构造。但是,触板540(例如,栅极触板)相对于半导体管芯520具有相同构造。半导体管芯524具有触板534中的两个触板,其各被焊接至四个基座。
图5F示出被焊接至通用导电夹500的半导体管芯525。半导体管芯525具有不同的覆盖区和触板构造。但是,触板540(例如,栅极触板)相对于半导体管芯520具有相同构造。半导体管芯525具有触板534中的三个触板。所有二十个基座510被焊接至触板535。在一些实施方案中,半导体管芯535可为最大的半导体管芯,其可被容纳在通用导电夹500上。
图5G示出被焊接至通用导电夹500的半导体管芯526。半导体管芯526具有不同的覆盖区和触板构造。但是,触板540(例如,栅极触板)相对于半导体管芯520具有相同构造。半导体管芯526具有触板536中的两个触板,其各被焊接至两个基座。
图5H示出被焊接至通用导电夹500的半导体管芯527。半导体管芯527具有不同的覆盖区和触板构造。但是,触板540(例如,栅极触板)相对于半导体管芯520具有相同构造。半导体管芯527具有触板537,其被焊接至三个基座。
图5I示出被焊接至通用导电夹500的半导体管芯528。半导体管芯528具有不同的覆盖区和触板构造。但是,触板540(例如,栅极触板)相对于半导体管芯520具有相同构造。半导体管芯528具有触板538中的两个触板:最左触板被焊接至六个基座且最右触板被焊接至九个基座。最左触板和最右触板均被焊接至定位在触板之间的三个共同基座。触板之间的共同基座的部分不被焊接。例如,可选择性地将焊膏仅施加至接触触板的共同基座的顶部表面的部分。随后可通过执行回流焊而焊接被施加焊膏的部分。
图5J示出被焊接至通用导电夹500的半导体管芯529。半导体管芯529具有不同的覆盖区和触板构造。但是,触板540(例如,栅极触板)相对于半导体管芯520具有相同构造。半导体管芯529具有触板539中的三个触板。最左触板被焊接至三个基座,中间触板被焊接至六个基座且最右触板被焊接至六个基座。
导电夹的构造将取决于需被附接的半导体管芯系列而变化。可容易地修改基座的大小、形状及间隔以适应不同半导体的系列。在一些实施方案中,通用导电夹可被构造来对准系列中的每个半导体管芯中的触板上的特定边角。例如,触板上最靠近半导体管芯的边角的边角可与基座上的边角侧向对准。在一些实施方案中,两个、三个或四个最靠近的边角与基座侧向对准。类似地,形成最靠近半导体管芯的边角的边角的触板的边缘可与基座的边缘侧向对准且平行。在一些实施方案中,形成最靠近半导体管芯的边角的边角的触板的两对、三对或四对线性边缘可与基座的边缘侧向对准且平行。图5A至图5J各展现一种构造,其中触板最靠近半导体管芯的边角的四个边角被侧向对准。图5A至图5J各展现具有形成最靠近半导体管芯的边角的边角的触板的三对线性边缘,其与基座的边缘侧向对准且平行(最靠近触板540的边角并非由两个线性边缘形成)。
图6示出当根据本申请案的一些实施方案构造通用导电夹时的设计考虑的实例。导电夹600在基座阵列的外边角上具有第一基座605、第二基座610、第三基座615和第四基座620。可选择定位在外边角上以适应半导体管芯系列中的最大触板覆盖区。外边角上的基座可被构造使得外边缘与触板侧向对准且平行(例如,如图5F中描绘,导电夹500上的外边角基座被焊接至半导体管芯525上的触板535,使得外边缘侧向对准且平行)。
最左列基座(包括第一基座605和第四基座620)的宽度625可基于系列中的触板的最小宽度。例如,通用导电夹500中的最左列基座的宽度对应于半导体管芯535和半导体管芯539中的最左触板的宽度。最上面一行基座的高度630可基于系列中的触板的最小高度。例如,通用导电夹500中最上面一行基座的高度分别对应于半导体管芯536和半导体管芯537中的触板536和触板537的高度。可通过分析系列中的中间尺寸的半导体管芯而确定节距635和高度640(例如,如图5A至图5J描绘,导电夹500的半导体管芯523等)。
上述通用导电夹的通用设计可类似地应用于其它导电基板,诸如引线框架。因此,本文公开的一些实施方案包括通用引线框架,其具有可适应不同尺寸的半导体管芯的两个或更多个基座。通用引线框架可大致具有与上述通用导电夹相同的特性(例如,如图5A至图5J中描绘的通用导电夹500)。在一些实施方案中,半导体管芯可被焊接至引线框架,使得基座的至少一部分不被焊接至触板。在一些实施方案中,半导体管芯可被焊接至引线框架,使得未焊接基座的至少一部分不被半导体管芯的覆盖区覆盖。
本文公开的一些实施方案包括用于制造半导体装置的套件。套件可包括具有不同触板构造的两个或更多个不同的半导体管芯。套件可包括通用导电基板(例如,通用引线框架或通用导电夹),其被构造成焊接至半导体管芯。通用导电基板可包括基座,其被构造使得每个半导体管芯可具有可操作地耦接至基座的触板。作为一个实例,套件可包括如图5A至图5J描绘的导电夹500和半导体管芯520至529。在一些实施方案中,通用导电基板上的基座被构造使得每个半导体管芯的触板上的两个、三个或四个最靠近边角(触板上最靠近半导体管芯上的边角的边角)与基座侧向对准。在一些实施方案中,形成每个半导体管芯的最靠近边角的触板的两对、三对或四对线性边缘可与基座的边缘对侧向对准且平行。
本文公开的一些实施方案包括一种制作半导体管芯的方法。该方法可用于例如制备本申请案中公开的任意半导体装置(例如,如图4中描绘的半导体装置400)。该方法可包括提供导电基板(例如,如图1A中描绘的引线框架100)。导电基板可包括导电基板的第一侧上的一个或多个基座,其中每个基座包括导电基板的第一侧上的平坦表面(例如,如图1A中描绘的基座140)。该方法还可包括将焊膏安置在导电基板上的基座上的至少一个平坦表面与半导体管芯的一个或多个触板之间,使得每个触板具有两个或更多个线性边缘,其各与基座上的平坦表面的至少一个边缘侧向对准且平行(例如,如图3B至图3C中描绘,施加焊膏300和焊膏340)。该方法还可包括将焊膏回流焊接以将基座的至少一部分焊接至触板。
本领域技术人员可从所有上述内容确定根据一个实施方案,一种半导体装置包括:引线框架,其包括被电耦接至第一引线的第一接触件,其中第一接触件包括第一接触件的第一侧上的一个或多个抬高区域,其中每个抬高区域包括第一接触件的第一侧上的平坦表面;半导体管芯,其包括一个或多个第一触板、第二触板和第三触板,其中第一触板被安置在半导体管芯的第一侧上,且其中每个第一触板被焊接至至少一个抬高区域,使得每个第一触板具有两个或更多个线性边缘,其各与抬高区域上的平坦表面的至少一个边缘侧向对准且平行;第二引线,其被电耦接至半导体管芯的第二触板;和第三引线,其被电耦接至半导体管芯的第三触板。
在一些实施方案中,第一接触件包括至少两个抬高区域。
在一些实施方案中,第一接触件上的每个抬高区域被焊接至选自第一触板的单独触板。
在一些实施方案中,第一接触件包括至少10个抬高区域。
在一些实施方案中,引线框架的第一接触件的第一侧上的抬高区域的数量大于被焊接至半导体管芯的第一触板的抬高区域的数量。
在一些实施方案中,装置还包括导电夹,其被焊接至第二触板,其中引线框架还包括被焊接至导电夹的第二接触件,且其中第二接触件被电耦接至第二引线。
本领域技术人员可从所有上述内容确定根据一个实施方案,一种半导体装置包括:引线框架,其包括被电耦接至半导体装置的第一引线的第一接触件;导电夹,其被电耦接至半导体装置上的第二引线,其中导电夹包括导电夹的第一侧上的一个或多个抬高区域,其中每个抬高区域包括导电夹的第一侧上的平坦表面;和半导体管芯,其包括:半导体管芯的第一侧上的第一触板,其中第一触板被焊接至引线框架上的第一接触件;半导体管芯的第二侧上的一个或多个第二触板,其中每个第二触板被焊接至导电夹的第一侧上的至少一个抬高区域,使得每个第二触板具有两个或更多个线性边缘,其各与抬高区域上的平坦表面的至少一个边缘侧向对准且平行;和半导体管芯上的第三触板,其中第三触板被电耦接至半导体装置的第三引线。
在一些实施方案中,导电夹包括至少两个抬高区域。
在一些实施方案中,导电夹的第一侧上的每个抬高区域被焊接至选自第二触板的单独触板。
在一些实施方案中,引线框架的第一接触件包括第一接触件的第一侧上的一个或多个第二抬高区域,其中每个第二抬高区域包括第一接触件的第一侧上的平坦表面,且其中第一触板被焊接至第二抬高区域,使得第一触板具有两个或更多个线性边缘,其各与第二抬高区域上的平坦表面的至少一个边缘侧向对准且平行。
本领域技术人员可从所有上述内容确定根据一个实施方案,一种制作半导体装置的方法包括:提供导电基板,导电基板包括导电基板的第一侧上的一个或多个抬高区域,其中每个抬高区域包括导电基板的第一侧上的平坦表面;将焊膏安置在导电基板上的抬高区域上的至少一个平坦表面与半导体管芯的一个或多个触板之间,使得每个触板具有两个或更多个线性边缘,其各与抬高区域上的平坦表面的至少一个边缘侧向对准且平行;和将焊膏回流焊接以将抬高区域的至少一部分焊接至触板。
在一些实施方案中,导电基板的第一侧上的抬高区域的数量等于被安置在被施加至抬高区域的焊膏上的触板的数量。
在一些实施方案中,每个触板被焊接至单独的抬高区域。
在一些实施方案中,每个触板的表面积的至少60%被焊接至抬高区域。
在一些实施方案中,将焊膏安置在导电基板上的抬高区域上的至少一个平坦表面与半导体管芯的触板之间包括将焊膏安置在导电基板上的抬高区域上的两个或更多个平坦表面与触板之间。
在一些实施方案中,导电基板的第一侧上的抬高区域的数量大于被焊接至半导体管芯的触板的抬高区域的数量。
在一些实施方案中,导电基板的第一侧上的抬高区域的数量至少为10。
在一些实施方案中,导电基板的第一侧上的抬高区域的数量至少为二,且其中导电基板的第一侧上的抬高区域的至少一部分具有不同尺寸。
在一些实施方案中,导电基板的第一侧上的抬高区域的数量至少为二,且其中抬高区域沿着第一方向均匀分隔。
在一些实施方案中,提供导电基板包括提供引线框架,其包括被电耦接至第一引线的导电基板。
在一些实施方案中,导电基板的第一侧上的抬高区域被布置为具有行和列的格栅,每行具有相同数量的抬高区域且每列具有相同数量的抬高区域。
鉴于所有上述内容,明显公开了一种新颖装置和方法。除其它特征外,尤其包括导电基板,诸如引线框架或导电夹,其具有可减小或阻止回流焊期间的漂移、倾斜或旋转的抬高区域。此外,公开了可被构造成可操作地焊接至不同半导体管芯的通用导电基板。
虽然结合特定优选实施方案和示例性实施方案描述了本实用新型的主题,但是上述图和其描述仅描绘主题的典型实施方案且因此不得被视作限制其范围,明显地,本领域技术人员将了解许多替代例和变化例。例如,已参考半导体管芯的特定晶体管构造描述了主题,但是也可使用各种不同的集成电路。作为另一个实例,已参考将触板焊接至导电基板描述了主题,但是也可使用将触板电耦接至导电基板的其它技术。
如下文权利要求反映,实用新型方面的范围可能小于单个上文公开实施方案的所有特征。因此,上文明示的权利要求在此明确并入该具体实施方式中,各权利要求独立作为本实用新型的单独实施方案。此外,如本领域技术人员将了解,虽然本文所述的一些实施方案包括一些但非其它实施方案中包括的其它特征,但是不同实施方案的特征的组合意在属于本实用新型的范畴且形成不同的实施方案。
Claims (10)
1.一种半导体装置,其特征在于,所述半导体装置包括:
引线框架,其包括电耦接至第一引线的第一接触件,其中所述第一接触件包括所述第一接触件的第一侧上的一个或多个抬高区域,其中每个所述抬高区域包括所述第一接触件的所述第一侧上的平坦表面;
半导体管芯,其包括一个或多个第一触板、第二触板和第三触板,其中所述第一触板被安置在所述半导体管芯的第一侧上,且其中每个所述第一触板被焊接至至少一个所述抬高区域,使得每个所述第一触板具有两个或更多个线性边缘,所述线性边缘各自与所述抬高区域上的所述平坦表面的至少一个边缘侧向对准且平行;
第二引线,其电耦接至所述半导体管芯的所述第二触板;和
第三引线,其电耦接至所述半导体管芯的所述第三触板。
2.根据权利要求1所述的半导体装置,其特征在于,所述第一接触件包括至少两个抬高区域。
3.根据权利要求2所述的半导体装置,其特征在于,所述第一接触件上的每个所述抬高区域被焊接至选自所述第一触板的单独触板。
4.根据权利要求1所述的半导体装置,其特征在于,所述第一接触件包括至少10个抬高区域。
5.根据权利要求4所述的半导体装置,其特征在于,所述引线框架的所述第一接触件的所述第一侧上的所述抬高区域的数量大于被焊接至所述半导体管芯的所述第一触板的所述抬高区域的数量。
6.根据权利要求1所述的半导体装置,其特征在于,所述半导体装置还包括导电夹,所述导电夹被焊接至所述第二触板,其中所述引线框架还包括被焊接至所述导电夹的第二接触件,且其中所述第二接触件电耦接至所述第二引线。
7.一种半导体装置,其特征在于,所述半导体装置包括:
引线框架,其包括电耦接至所述半导体装置的第一引线的第一接触件;
导电夹,其电耦接至所述半导体装置上的第二引线,其中所述导电夹包括所述导电夹的第一侧上的一个或多个抬高区域,其中每个所述抬高区域包括所述导电夹的所述第一侧上的平坦表面;和
半导体管芯,其包括:
所述半导体管芯的第一侧上的第一触板,其中所述第一触板被焊接至所述引线框架上的所述第一接触件;
所述半导体管芯的第二侧上的一个或多个第二触板,其中每个所述第二触板被焊接至所述导电夹的所述第一侧上的至少一个所述抬高区域,使得每个所述第二触板具有两个或更多个线性边缘,所述线性边缘各自与所述抬高区域上的所述平坦表面的至少一个边缘侧向对准且平行;和
所述半导体管芯上的第三触板,其中所述第三触板电耦接至所述半导体装置的第三引线。
8.根据权利要求7所述的半导体装置,其特征在于,所述导电夹包括至少两个抬高区域。
9.根据权利要求8所述的半导体装置,其特征在于,所述导电夹的所述第一侧上的每个所述抬高区域被焊接至选自所述第二触板 的单独触板。
10.根据权利要求7所述的半导体装置,其特征在于,所述引线框架的所述第一接触件包括所述第一接触件的第一侧上的一个或多个第二抬高区域,其中每个所述第二抬高区域包括所述第一接触件的所述第一侧上的平坦表面,且其中所述第一触板被焊接至所述第二抬高区域,使得所述第一触板具有两个或更多个线性边缘,所述线性边缘各自与所述第二抬高区域上的所述平坦表面的至少一个边缘侧向对准且平行。
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US10727170B2 (en) | 2015-09-01 | 2020-07-28 | Semiconductor Components Industries, Llc | Semiconductor devices and methods of making the same |
US10998256B2 (en) | 2018-12-31 | 2021-05-04 | Texas Instruments Incorporated | High voltage semiconductor device lead frame and method of fabrication |
US11543453B2 (en) * | 2019-01-25 | 2023-01-03 | Texas Instruments Incorporated | In-wafer reliability testing |
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US7394150B2 (en) * | 2004-11-23 | 2008-07-01 | Siliconix Incorporated | Semiconductor package including die interposed between cup-shaped lead frame and lead frame having mesas and valleys |
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