CN203733783U - 一种引线框架 - Google Patents
一种引线框架 Download PDFInfo
- Publication number
- CN203733783U CN203733783U CN201420072897.4U CN201420072897U CN203733783U CN 203733783 U CN203733783 U CN 203733783U CN 201420072897 U CN201420072897 U CN 201420072897U CN 203733783 U CN203733783 U CN 203733783U
- Authority
- CN
- China
- Prior art keywords
- pin
- bonding region
- bonding
- region
- slide glass
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000011521 glass Substances 0.000 claims description 37
- 239000004020 conductor Substances 0.000 claims description 29
- 239000005022 packaging material Substances 0.000 claims description 12
- 230000001788 irregular Effects 0.000 claims description 3
- 239000000463 material Substances 0.000 abstract description 5
- 239000002184 metal Substances 0.000 abstract description 2
- 210000000746 body region Anatomy 0.000 abstract 1
- 239000004065 semiconductor Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 2
- 238000010030 laminating Methods 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000002146 bilateral effect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/4901—Structure
- H01L2224/4903—Connectors having different sizes, e.g. different diameters
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/494—Connecting portions
- H01L2224/4943—Connecting portions the connecting portions being staggered
- H01L2224/49431—Connecting portions the connecting portions being staggered on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
本实用新型公开一种引线框架,包含框架本体区、载片基岛区、键合区和引脚,第二引脚顶端与载片基岛区断开,第三引脚顶端的第二键合区向第二引脚顶端上方横向扩展,第一引脚顶端的第一键合区向远离第三引脚顶端的第二键合区的方向横向收缩,从而大幅增加第二键合区的面积,使得在第二键合区上键合的源极金属导线根数有效增加,增加器件的最大熔断电流能力,提升器件性能。载片基岛区背面未被塑封料包裹,器件在工作时在芯片背面需要施加的电压可以直接施加在载片基岛区的背面,不影响器件的实际使用。本实用新型广泛适用于TO-220、TO-247、TO-3P、TO-252、TO-263等直插类型或贴片类型的封装种类。
Description
技术领域
本实用新型涉及作为集成电路芯片载体的引线框架,是一种借助于键合材料实现芯片内部电路引出端与外引线的电气连接并形成电气回路的结构件,是电子信息产业的基础材料。
背景技术
半导体分立功率器件的封装外形包括直插类型和贴片类型,其中直插类型包含应用较为广泛的TO-220、TO-220F、TO-247、TO-3P、TO-251等种类,
贴片类型包含应用较为广泛的TO-252、TO-263等种类。无论是直插类型还是贴片类型,一个完整的分立器件都包含引线框架、塑封料和芯片三个主要的组成部分。如图2至图4所示,其中引线框架又包含框架本体区1、载片基岛区2、键合区3、4和引脚5、6、7。如图1所示,芯片粘附装载在载片基岛区,
通过把指定规格的金属导线两端分别在芯片表面和键合区表面进行键合,从而将电流由芯片经金属导线引流通过键合区、引脚直至到电路板。
目前半导体分立功率器件以垂直双扩散金属氧化物场效应晶体管(VDMOSFET)为主,VDMOSFET芯片的背面为器件的漏极,芯片的正面包括器件的栅极和源极。如图1所示,芯片装载在载片基岛区2,背面漏极直接与载片基岛区2贴合接触,对于具有较大耗散功率的分立器件,其载片基岛区2的背面是直接裸露在外的,即载片基岛区2的背面没有被塑封料包裹。
VDMOSFET芯片正面包括栅极和源极,栅极上键合的金属导线连接至键合区3,栅极由于流经的驱动电流比较小,所以栅极上键合的金属导线通常较细,
并且只有1根,键合区3也不需要很大的面积;与此相反,芯片源极是器件电流的主要流经区域,通常需要多根较粗的金属导线,金属导线的粗细与根数直接影响器件的电流能力,源极上键合的金属导线连接至键合区4,显然,芯片源极区域的面积和键合区4的面积直接决定了能够键合的金属导线根数与粗细。除此以外,如图1所示,引脚6直接与载片基岛区2相连,引脚6连接器件的漏极,器件在工作时通过引脚6在器件漏极上施加一个漏极电压,不同于引脚5顶端的键合区3和引脚7顶端的键合区4需要键合金属导线,引脚6顶端是没有键合区的,不需要键合金属导线。
另一类主要的半导体分立功率器件是绝缘栅双极型晶体管(IGBT),IGBT芯片的背面为器件的集电极,芯片的正面包括器件的栅极和发射极。如图1所示,芯片装载在载片基岛区2,背面集电极直接与载片基岛区2贴合接触,对于具有较大耗散功率的分立器件,其载片基岛区2的背面是直接裸露在外的,即载片基岛区2的背面没有被塑封料包裹。IGBT芯片正面包括栅极和发射极,栅极上键合的金属导线连接至键合区3,栅极由于流经的驱动电流比较小,所以栅极上键合的金属导线通常较细,并且只有1根,键合区3也不需要很大的面积;与此相反,芯片发射极是器件电流的主要流经区域,通常需要多根较粗的金属导线,金属导线的粗细与根数直接影响器件的电流能力,发射极上键合的金属导线连接至键合区4,显然,芯片发射极区域的面积和键合区4的面积直接决定了能够键合的金属导线根数与粗细。除此以外,如图1所示,引脚6直接与载片基岛区相连,引脚6连接器件的集电极,器件在工作时通过引脚6在器件集电极上施加一个集电极电压,不同于引脚5顶端的键合区3和引脚7顶端的键合区4需要键合金属导线,引脚6顶端是没有键合区的,不需要键合金属导线。
由此可见,现有直插类型或贴片类型引线框架的键合区4面积受旁边引脚6的影响,通常面积都比较有限,如图1所示的TO-220引线框架,其键合区4上通常只能键合3根20mil线径的Al丝,因此器件的最大熔断电流能力经常会受限于键合区4上能够键合的Al线根数与Al线粗细。
实用新型内容
本实用新型的主要目的是解决现有直插类型或贴片类型半导体分立功率器件的引线框架的键合区受旁边引脚的影响导致面积有限,致使键合区能够键合的金属导线根数与粗细受限,从而使器件的最大熔断电流能力受限的问题,提供一种能够有效增加键合区上键合的金属导线根数,从而增加器件的最大熔断电流能力,提升了器件性能的引线框架。
本实用新型的技术方案如下:
一种引线框架,包含框架本体区、载片基岛区、键合区和引脚,所述框架本体区和载片基岛区连接,所述键合区包括第一键合区和第二键合区,所述引脚包括第一引脚、第二引脚以及第三引脚,第一键合区和第二键合区分别连接在第一引脚和第三引脚的顶端;
所述第二引脚顶端与载片基岛区断开不连接,所述载片基岛区与VDMOSFET芯片背面的漏极或IGBT芯片背面的集电极连接;所述载片基岛区背面未被塑封料包裹;
所述第三引脚顶端的第二键合区向第二引脚顶端上方横向扩展,所述第二键合区键合由VDMOSFET芯片正面的源极或IGBT芯片正面的发射极键合引出的金属导线;
所述第一引脚顶端的第一键合区向远离第三引脚顶端的第二键合区的方向横向收缩,所述第一键合区键合由VDMOSFET芯片正面的栅极或IGBT芯片正面的栅极键合引出的金属导线。
其进一步的技术方案为:所述第二引脚的底部不长出第一引脚和第三引脚的底部,或者所述第二引脚的长度为零。
以及,其进一步的技术方案为:所述第三引脚顶端的第二键合区向第二引脚顶端上方横向扩展,扩展的形状包括规则的多边形或不规则的多边形。
本实用新型的有益技术效果是:
本实用新型将第二引脚顶端与载片基岛区断开,同时适当减少第一键合区的面积,将第三引脚顶端的第二键合区向第二引脚顶端区域横向扩展,从而大幅增加第二键合区的面积,使得第二键合区的面积比现有引线框架的第二键合区面积大幅增加,使得在第二键合区上键合的源极金属导线根数有效增加,从而增加了器件的最大熔断电流能力,提升了器件的性能。
由于芯片背面直接与金属材质的载片基岛区连接,而绝大多数中大功率的直插类型或贴片类型的载片基岛区背面是裸露在外面的,所以器件在工作时在芯片背面需要施加的电压可以直接施加在载片基岛区的背面,因此本实用新型将第二引脚顶端与载片基岛区断开,不会影响这类封装外形器件的实际使用。
本实用新型结构的引线框架广泛适用于TO-220、TO-247、TO-3P、TO-252、TO-263等直插类型或贴片类型的封装种类。
附图说明
图1是现有TO-220引线框架上的芯片键合示意图。
图2是现有TO-220引线框架60度角立体示意图。
图3是现有TO-220引线框架正面俯视示意图。
图4是现有TO-220引线框架背面俯视示意图。
图5是本实用新型实施例TO-220引线框架上的芯片键合示意图。
图6是本实用新型实施例TO-220引线框架60度角立体示意图。
图7是本实用新型实施例TO-220引线框架正面俯视示意图。
图8是本实用新型实施例TO-220引线框架背面俯视示意图。
图9是本实用新型实施例TO-220引线框架包覆塑封料后的正面立体示意图。
图10是本实用新型实施例TO-220引线框架包覆塑封料后的背面立体示意图。
具体实施方式
下面结合附图对本实用新型的具体实施方式做进一步说明。
如图5所示,以TO-220引线框架键合VDMOSFET芯片为例,引脚5、6、7分别连接的是器件的栅电极、漏电极和源电极,其中引脚5与引脚7的顶端分别有金属导线键合区3和键合区4,通过将金属导线的两端分别在芯片表面与对应的键合区表面进行键合来将栅电极和源电极引出,引脚6顶端是与载片基岛区2相连接的,芯片背面(即器件的漏极)贴附装载于载片基岛区2表面。封装好的VDMOSFET产品在使用时,引脚5上会施加一个栅极电压,引脚6上会施加一个漏极电压,器件导通以后,电流经芯片表面与键合区4之间的金属导线从引脚7流走,因此,芯片表面与键合区4之间的金属导线的根数与线径直接影响了器件流通电流的能力。
如图6、图7、图8所示,本实用新型结构中,将引脚6顶端与载片基岛区2断开,同时减少引脚5顶端的键合区3的面积,即引脚5顶端的键合区3向远离引脚7顶端的键合区4的方向横向收缩,并将引脚7顶端的键合区4的面积向引脚6顶端区域横向进行扩展,扩展的形状包括规则的多边形或不规则的多边形,从而增加了在键合区4表面能够键合金属导线的数量与线径,如图5所示,其键合区4上键合的Al丝达到4根,从而尽可能的提升了器件流通电流的能力。
如图9、图10所示,载片基岛区2与三个引脚的顶端在封装时是需要被绝缘的塑封料8所包覆的,引脚6顶端虽然与载片基岛区2断开,原本需要施加在引脚6上的漏电极电压改为施加在裸露在外的载片基岛区2背面,但是在维持现有塑封料8成型模具不变的前提下,依然需要引脚6顶部来填堵原有结构中由引脚6顶端填堵的塑封料孔,因此,引脚6是需要保留的。引脚2的长度限制为底部不长出引脚1和引脚3的底部。当然,如果更改了现有塑封料成型模具,将所述的塑封料孔直接由塑封料来填堵,那么引脚6就可以去除了,即引脚2的长度可以为零。
如图9、图10所示,由于本实用新型结构中需要在裸露在外面的载片基岛区2背面施加漏极电压,因此,载片基岛区2背面就不能被绝缘的塑封料8所包覆。目前多数的功率器件封装外形均是将载片基岛区2背面直接裸露在外的,因此,本实用新型结构适宜于现有这类将载片基岛区背面直接裸露在外的封装类型,具体包括直插类型的TO-220、TO-251、TO-247、TO-3P等和贴片类型的TO-252、TO-263等。
以上所述的仅是本实用新型的优选实施方式,本实用新型不限于以上实施例。可以理解,本领域技术人员在不脱离本实用新型的精神和构思的前提下直接导出或联想到的其他改进和变化,均应认为包含在本实用新型的保护范围之内。
Claims (3)
1.一种引线框架,包含框架本体区、载片基岛区、键合区和引脚,所述框架本体区和载片基岛区连接,所述键合区包括第一键合区和第二键合区,所述引脚包括第一引脚、第二引脚以及第三引脚,第一键合区和第二键合区分别连接在第一引脚和第三引脚的顶端,其特征在于:
所述第二引脚顶端与载片基岛区断开不连接,所述载片基岛区与VDMOSFET芯片背面的漏极或IGBT芯片背面的集电极连接;所述载片基岛区背面未被塑封料包裹;
所述第三引脚顶端的第二键合区向第二引脚顶端上方横向扩展,所述第二键合区键合由VDMOSFET芯片正面的源极或IGBT芯片正面的发射极键合引出的金属导线;
所述第一引脚顶端的第一键合区向远离第三引脚顶端的第二键合区的方向横向收缩,所述第一键合区键合由VDMOSFET芯片正面的栅极或IGBT芯片正面的栅极键合引出的金属导线。
2.根据权利要求1所述引线框架,其特征在于:所述第二引脚的底部不长出第一引脚和第三引脚的底部,或者所述第二引脚的长度为零。
3.根据权利要求1所述引线框架,其特征在于:所述第三引脚顶端的第二键合区向第二引脚顶端上方横向扩展,扩展的形状包括规则的多边形或不规则的多边形。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201420072897.4U CN203733783U (zh) | 2014-02-19 | 2014-02-19 | 一种引线框架 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201420072897.4U CN203733783U (zh) | 2014-02-19 | 2014-02-19 | 一种引线框架 |
Publications (1)
Publication Number | Publication Date |
---|---|
CN203733783U true CN203733783U (zh) | 2014-07-23 |
Family
ID=51203834
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201420072897.4U Expired - Lifetime CN203733783U (zh) | 2014-02-19 | 2014-02-19 | 一种引线框架 |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN203733783U (zh) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN106409805A (zh) * | 2016-12-06 | 2017-02-15 | 四川富美达微电子有限公司 | 一种五引脚ic结构 |
CN107275405A (zh) * | 2017-06-09 | 2017-10-20 | 郑州云海信息技术有限公司 | 一种功率mos管及其制造方法、使用方法 |
CN114760756A (zh) * | 2022-06-14 | 2022-07-15 | 四川明泰微电子有限公司 | 高频集成封装模块及其封装方法 |
-
2014
- 2014-02-19 CN CN201420072897.4U patent/CN203733783U/zh not_active Expired - Lifetime
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN106409805A (zh) * | 2016-12-06 | 2017-02-15 | 四川富美达微电子有限公司 | 一种五引脚ic结构 |
CN107275405A (zh) * | 2017-06-09 | 2017-10-20 | 郑州云海信息技术有限公司 | 一种功率mos管及其制造方法、使用方法 |
CN107275405B (zh) * | 2017-06-09 | 2019-10-01 | 郑州云海信息技术有限公司 | 一种功率mos管及其制造方法、使用方法 |
CN114760756A (zh) * | 2022-06-14 | 2022-07-15 | 四川明泰微电子有限公司 | 高频集成封装模块及其封装方法 |
CN114760756B (zh) * | 2022-06-14 | 2022-09-06 | 四川明泰微电子有限公司 | 高频集成封装模块及其封装方法 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN203733783U (zh) | 一种引线框架 | |
CN105489571A (zh) | 一种带散热片的半导体封装及其封装方法 | |
CN109935561A (zh) | 一种氮化镓器件及氮化镓器件的封装方法 | |
US9437587B2 (en) | Flip chip semiconductor device | |
US8921986B2 (en) | Insulated bump bonding | |
CN103715161B (zh) | 芯片装置,芯片封装和用于制作芯片装置的方法 | |
CN208336207U (zh) | 一种双基岛引线框架及其sot33-5l封装件 | |
CN203733785U (zh) | 一种具有改进型封装结构的半导体器件 | |
CN104167403A (zh) | 多脚封装的引线框架 | |
CN204375733U (zh) | 一种双引线框架 | |
CN205984972U (zh) | 一种引线框架结构 | |
CN107482108A (zh) | 一种新型smd灯珠 | |
CN105845633A (zh) | 一种多芯片3d封装工艺 | |
CN203800034U (zh) | 一种半导体器件封装引线框架 | |
CN207587727U (zh) | 一种多载体引线框架 | |
CN202495446U (zh) | 一种新型结构晶闸管 | |
CN206098385U (zh) | Ic器件用半导体的引线框架 | |
CN204271072U (zh) | 引线框架封装结构 | |
CN105448746B (zh) | 一种氮化镓器件及封装方法 | |
CN211578746U (zh) | 一种适合大功率to封装的异形不对称框架 | |
CN103441080A (zh) | 一种芯片正装bga封装方法 | |
CN203850289U (zh) | 一种用于小功率电器的塑封引线框架 | |
CN218299797U (zh) | 一种多芯片合封的半导体封装结构 | |
CN204696112U (zh) | 引线框 | |
CN210224022U (zh) | 一种集成芯片及其集成框架 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
CX01 | Expiry of patent term | ||
CX01 | Expiry of patent term |
Granted publication date: 20140723 |