CN203339162U - 八层堆叠式芯片封装结构 - Google Patents

八层堆叠式芯片封装结构 Download PDF

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CN203339162U
CN203339162U CN2013203728717U CN201320372871U CN203339162U CN 203339162 U CN203339162 U CN 203339162U CN 2013203728717 U CN2013203728717 U CN 2013203728717U CN 201320372871 U CN201320372871 U CN 201320372871U CN 203339162 U CN203339162 U CN 203339162U
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chip
substrate
electrically connected
packaging structure
chips
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胡立栋
金若虚
陆春荣
刘鹏
张振燕
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Li Cheng Technology (suzhou) Co Ltd
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Li Cheng Technology (suzhou) Co Ltd
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    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/48147—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked with an intermediate bond, e.g. continuous wire daisy chain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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Abstract

本实用新型公开了一种八层堆叠式芯片封装结构，其特征在于，包括：一基板，具有相对的一顶面和一底面；八个相同厚度的芯片，堆叠配置于所述基板的顶面上，其中四个芯片为一组，两组芯片呈箭头梯子形堆叠；多根导线，电性连接于芯片和芯片之间或芯片和基板之间；封装结构的封装空间内填充的绝缘树脂。本实用新型所述八层堆叠式芯片封装结构采用八层相同厚度的芯片封装形式，整体为4-4梯子型结构,实现了大尺寸、多层芯片等同厚度的封装形式。

Description

八层堆叠式芯片封装结构
技术领域
本实用新型属于半导体内存封装技术领域，具体涉及一种八层堆叠式芯片封装结构。
背景技术
现有封装产品中一般为1～4层芯片，芯片比较厚；部分为8层，但是每一层的厚度不完全一样，通常最底层最厚，以增强其抗压力的能力，但封装芯片层数较低，芯片容量小，而且各芯片厚度不同，封装工艺带来复杂性。
发明内容
本实用新型的目的是提供一种八层堆叠式芯片封装结构。
为实现上述实用新型目的，本实用新型采用了如下技术方案：
一种八层堆叠式芯片封装结构，其特征在于，包括：
一基板，具有相对的一顶面和一底面；
八个相同厚度的芯片，堆叠配置于所述基板的顶面上，其中四个芯片为一组，两组芯片呈箭头梯子形堆叠；
多根导线，电性连接于芯片和芯片之间或芯片和基板之间；导线为金线封装结构的封装空间内填充的绝缘树脂。
进一步的，所述八个芯片由下往上依次为第一组的第一芯片、第二芯片、第三芯片、第四芯片和第二组的第五芯片、第六芯片、第七芯片、第八芯片；其中，第八芯片通过打线结合技术电性连接至第七芯片和基板；第七芯片通过打线结合技术电性连接至第六芯片和基板；第六芯片通过打线结合技术电性连接至第五芯片和基板；第五芯片通过打线结合技术电性连接至基板；第四芯片通过打线结合技术电性连接至第三芯片和基板；第三芯片通过打线结合技术电性连接至第二芯片和基板；第二芯片通过打线结合技术电性连接至第一芯片和基板；第一芯片通过打线结合技术电性连接至基板。
进一步的，所述芯片的厚度为60um，芯片尺寸为9*13mm。
进一步的，所述芯片与芯片、芯片与基板用胶带粘接，胶带厚度为15um
进一步的，所述基板的该底面配置多个用于焊接于PCB板的锡球。
制造上述八层堆叠式芯片封装结构的工艺流程如下：
芯片研磨与切割->芯片堆叠->金线焊接->树脂合成->植球与切割。
首先使用双刀特殊研磨抛光技术，使用细金刚石颗粒的研磨轮，并配合低主轴转数和进给速度，在设备传送方面，需要调低各部件的真空和吹气压力进行配合，要求1～8层芯片厚度为60um，并切割成单个元件，使用10-15um厚度胶带把芯片与芯片，芯片与基板黏贴到一起，为了控制芯片不会出现破裂，要求大于70kpa吸着力道，和10N焊接力，并且每四层要进行一次高温高压（145～155度30～60分钟）烘烤，以保证芯片与胶带之间的粘合力，焊接金线，采用2段的焊线压力输出：较小的初始压力（10至15g）防止焊针接触芯片表面时的晃动而破坏芯片，待芯片晃动趋于稳定后，施加一个合适的压力（20至30g）以帮助焊接金线的结合性。另外，树脂合模时，通常也会需要真空抽气，引导气体可以顺利排出整个腔体之内。连接芯片与芯片，芯片与基板电子线路，树脂合成时，开启真空，引导气体外流，合模压力为35～50t，合模后，需要进行175度5小时的高温高压烘烤，强化树脂的结合，最后植入锡球以便客户端焊接到PCB线路版上。
研磨的时候使用细金刚石颗粒的研磨轮，并配合低主轴转数和进给速度达到每层60um厚度。八层芯片相同厚度，与过去技术相比，有利于封装生产，工艺控制，每两层芯片焊接后需要进行一次高温高压烘烤和焊接金线工艺，焊接金线时，与传统2～4层堆叠芯片产品相比，芯片越薄，芯片则更易碎。使用“表面屈从”功能，它将超音波能量及焊接压力进行缓降的输出，可以确保焊针在接触芯片时，焊接表面能够保持稳定的高度，不会因为芯片过薄而上下晃动，另外采用2段的焊线压力输出：较小的初始压力（10至15g）防止焊针接触芯片表面时的晃动而破坏芯片，待芯片晃动趋于稳定后，施加一个合适的压力（20至30g）以帮助焊接的结合性。另外，过去产品由于不同的芯片厚度，也要搭配不同胶带厚度，通常最底层芯片胶带最厚，工艺控制也就稍微复杂。
实用新型优点：
本实用新型所述八层堆叠式芯片封装结构采用八层相同厚度的芯片封装形式，整体为4-4梯子型结构,实现了小尺寸、多层芯片等同厚度的封装形式。
附图说明
图1为本实用新型八层堆叠式芯片封装结构的剖面图；。
其中，1、第一芯片；2、第二芯片；3、第三芯片；4、第四芯片；5、第五芯片；6、第六芯片；7、第七芯片；8、第九芯片；9、基板；10、金线；11、绝缘树脂；12、锡球。
具体实施方式
以下结合附图及一优选实施例对本实用新型的技术方案作进一步的说明。
实施例：
如图1所示：一种八层堆叠式芯片封装结构，其特征在于，包括：
一基板9，具有相对的一顶面和一底面；
八个相同厚度的芯片，堆叠配置于所述基板9的顶面上，其中四个芯片为一组，两组芯片呈箭头梯子形堆叠；
多根导线，电性连接于芯片和芯片之间或芯片和基板9之间；导线为金线
封装结构的封装空间内填充的绝缘树脂11。
进一步的，所述八个芯片由下往上依次为第一组的第一芯片1、第二芯片2、第三芯片3、第四芯片4和第二组的第五芯片5、第六芯片6、第七芯片7、第八芯片8；其中，第八芯片8通过打金线电性连接至第七芯片7和基板9；第七芯片7通过打金线电性连接至第六芯片6和基板9；第六芯片6通过打金线电性连接至第五芯片5和基板9；第五芯片5通过打金线电性连接至基板9；第四芯片4通过打金线电性连接至第三芯片3和基板9；第三芯片3通过打金线电性连接至第二芯片2和基板9；第二芯片2通过打金线电性连接至第一芯片1和基板9；第一芯片1通过打金线电性连接至基板9。
所述芯片的厚度为60um，芯片尺寸为9*13mm。
所述芯片与芯片、芯片与基板9用胶带粘接，胶带厚度相同，每层都为15um
所述基板9的该底面配置多个用于焊接于PCB板的锡球12。
需要指出的是，以上所述者仅为用以解释本实用新型之较佳实施例，并非企图据以对本实用新型作任何形式上之限制，是以，凡有在相同之实用新型精神下所作有关本实用新型之任何修饰或变更，皆仍应包括在本实用新型意图保护之范畴。

Claims (5)

1.一种八层堆叠式芯片封装结构，其特征在于，包括：
一基板，具有相对的一顶面和一底面；
八个相同厚度的芯片，堆叠配置于所述基板的顶面上，其中四个芯片为一组，两组芯片呈箭头梯子形堆叠；
多根导线，电性连接于芯片和芯片之间或芯片和基板之间；
封装结构的封装空间内填充的绝缘树脂。
2.根据权利要求1所述的八层堆叠式芯片封装结构，其特征在于，所述八个芯片由下往上依次为第一组的第一芯片、第二芯片、第三芯片、第四芯片和第二组的第五芯片、第六芯片、第七芯片、第八芯片；其中，第八芯片通过打线结合技术电性连接至第七芯片和基板；第七芯片通过打线结合技术电性连接至第六芯片和基板；第六芯片通过打线结合技术电性连接至第五芯片和基板；第五芯片通过打线结合技术电性连接至基板；第四芯片通过打线结合技术电性连接至第三芯片和基板；第三芯片通过打线结合技术电性连接至第二芯片和基板；第二芯片通过打线结合技术电性连接至第一芯片和基板；第一芯片通过打线结合技术电性连接至基板。
3.根据权利要求2所述的八层堆叠式芯片封装结构，其特征在于，所述芯片的厚度为60um，芯片尺寸为9*13mm。
4.根据权利要求3所述的八层堆叠式芯片封装结构，其特征在于，所述芯片与芯片、芯片与基板用胶带粘接，胶带厚度为15um。
5.根据权利要求4所述的八层堆叠式芯片封装结构，其特征在于，所述基板的该底面配置多个用于焊接于PCB板的锡球。
CN2013203728717U 2013-06-26 2013-06-26 八层堆叠式芯片封装结构 Expired - Fee Related CN203339162U (zh)

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