CN203339150U - 一种八层堆叠式芯片封装结构 - Google Patents
一种八层堆叠式芯片封装结构 Download PDFInfo
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Abstract
本实用新型公开了一种八层堆叠式芯片封装结构,其特征在于,包括:一基板,具有相对的一顶面和一底面;八个芯片,堆叠配置于所述基板的顶面上,其中二个芯片为一组,四组芯片呈交叉梯子形堆叠;多根导线,电性连接于芯片和芯片之间和芯片和基板之间;封装结构的封装空间内填充的绝缘树脂。本实用新型八层堆叠式芯片封装结构性能稳定,良品率高、层数较高、芯片容量大。
Description
技术领域
本实用新型属于半导体内存封装技术领域,具体涉及一种八层堆叠式芯片封装结构。
背景技术
现有封装产品中一般为1~4层芯片,芯片比较厚,封装芯片层数较低,芯片容量小,而对于4层芯片以上的封装结构,由于封装工艺能力的限制,存在较多问题,如芯片研磨技术、金线键合分段式技术需要特殊控制,才能达到多层封装结构制造工艺的要求。
实用新型内容
本实用新型的目的是提供一种八层堆叠式芯片封装结构。
为实现上述实用新型目的,本实用新型采用了如下技术方案:
一种八层堆叠式芯片封装结构,其特征在于,包括:
一基板,具有相对的一顶面和一底面;
八个芯片,堆叠配置于所述基板的顶面上,其中二个芯片为一组,四组芯片呈交叉梯子形堆叠;
多根导线,电性连接于芯片和芯片之间和芯片和基板之间;
封装结构的封装空间内填充的绝缘树脂。
进一步的,所述八个芯片由下往上依次为第一芯片、第二芯片、第三芯片、第四芯片、第五芯片、第六芯片、第七芯片、第八芯片;其中,第八芯片通过打线结合技术电性连接至第七芯片;第七芯片通过打线结合技术电性连接至基板;第六芯片通过打线结合技术电性连接至第五芯片;第五芯片通过打线结合技术电性连接至基板;第四芯片通过打线结合技术电性连接至第三芯片;第三芯片通过打线结合技术电性连接至基板;第二芯片通过打线结合技术电性连接至第一芯片;第一芯片通过打线结合技术电性连接至基板。
进一步的,所述第一芯片和第五芯片的厚度为75um,所述第二芯片、第三芯片、第四芯片、第六芯片、第七芯片和第八芯片的厚度为55um。
进一步的,所述芯片与芯片、芯片与基板用胶带粘接,胶带厚度为10um。
进一步的,所述基板的该底面配置多个用于焊接于PCB板的锡球。
如上所述的八层堆叠式芯片封装结构的制造工艺,包括如下步骤:
步骤1芯片研磨与切割:使用细金刚石颗粒的研磨轮,并配合低主轴转数和进给速度,调低传送设备各部件的真空和吹气压力,研磨第二芯片、第三芯片、第四芯片、第六芯片、第七芯片和第八芯片的厚度为55um;研磨第一芯片和第五芯片的厚度为75um;并将整个晶圆切割成单个的独立的小芯片;
由于芯片薄,需要慢磨和精磨,低转数情况下,不断循序渐进的过程保证芯片不会破碎。
步骤2贴片:使用10um厚的胶带把芯片与芯片、芯片和基板粘贴在一起,工艺参数为吸着力道大于70Kpa,焊接力为10N,每两层芯片进行一次温度为145~155℃、时间为30~60分钟的烘烤,以保证芯片与胶带之间的粘合力;
步骤3金线键合:通过金线健合的方式来连接芯片与芯片,芯片与基板的之间电路;工艺参数为采用两段的焊线压力输出:较小的初始压力为15-15g,以防止焊针接触芯片表面时晃动而破坏芯片,待芯片晃动趋于稳定后,再施加稍大的压力为20~30g,以帮助焊接金线的结合性;
步骤4塑封:将芯片,金线,胶带,基板的上面用树脂包封在塑封体内,在塑封合膜时,需要抽真空,合膜压力为35~50t;合膜后,进行160~180℃、5小时的高温烘烤,可以强化树脂的结合引导气体顺利排出整个腔体;
步骤5植球:植入锡球在基板的底部,以便元件可以顺利的焊接到PCB线路版上;
步骤6切割:每一条基板根据不同产品的尺寸,包含了几十粒大到几百粒个芯片,通过切割工序,形成若干个独立元器件,以便客户端使用。
本实用新型采用8层芯片堆叠方式,为2-2结构,焊接金线复杂,同时要求2~4,6~8层芯片厚度为55um,第1,5层芯片厚度为75um(以往通常100um以上),为了达到如此薄的厚度需要使用特殊研磨抛光技术,故此使用细金刚石颗粒的研磨轮,并配合低主轴转数和进给速度,在设备传送方面,需要调低各部件的真空和吹气压力进行配合。为了配合薄芯片的使用,需要10um薄的胶带(通常20-25um),并且每2层芯片焊接后,都要高压进行烘烤,确保芯片之间粘合力。为了减少金线倾斜现象,在结构设计上,引线键合中较长金线的位置特殊调整,特殊调整指的是控制弧高,使其位于在塑封合模冲压时,位于受力较小的地方,如使其与模流方向一致,从而减少其变形。与传统1~4层堆叠芯片产品相比,芯片越薄,芯片则更易碎。焊接金线时,使用“表面屈从”功能,它将超音波能量及焊接压力进行缓降的输出,可以确保焊针在接触芯片时,焊接表面能够保持稳定的高度,不会因为芯片过薄而上下晃动,另外采用2段的焊线压力输出:较小的初始压力(10至15g)防止焊针接触芯片表面时的晃动而破坏芯片,待芯片晃动趋于稳定后,施加一个合适的压力(20至30g)以帮助焊接金线的结合性。另外,塑封合模时,最顶端芯片与封装体上面的距离降低到传统极限值200um,(小于这个值,传统传导式塑封在技术上已经处于瓶颈,需要另外一种粉末喷洒式封装合模,但需要投入大量资金。)所以,此处在塑封合模时,需要真空抽气配合,另外控制合模参数,主要在于加快树脂前期流动速度,延长合模包压时间,引导气体可以顺利排出整个腔体之内。
实用新型优点:
本实用新型所述八层堆叠式芯片封装结构较之现有技术具有层数较高、芯片容量大的优点,而且性能稳定,良品率高。
附图说明
图1为本实用新型八层堆叠式芯片封装结构的剖面图;。
其中,1、第一芯片;2、第二芯片;3、第三芯片;4、第四芯片;5、第五芯片;6、第六芯片;7、第七芯片;8、第九芯片;9、基板;10、金线;11、绝缘树脂;12、锡球。
具体实施方式
以下结合附图及优选实施例对本实用新型的技术方案作进一步的说明。
实施例:
如图1所示:一种八层堆叠式芯片封装结构,包括:
一基板9,具有相对的一顶面和一底面;
八个芯片,堆叠配置于所述基板9的顶面上,其中二个芯片为一组,四组芯片呈交叉梯子形堆叠;
多根导线,电性连接于芯片和芯片之间和芯片和基板9之间,导线采用金线10;
封装结构的封装空间内填充的绝缘树脂11。
进一步的,所述八个芯片由下往上依次为第一芯片1、第二芯片2、第三芯片3、第四芯片4、第五芯片5、第六芯片6、第七芯片7、第八芯片8;其中,第八芯片8通过打金线电性连接至第七芯片7;第七芯片7通过打金线电性连接至基板9;第六芯片6通过打金线电性连接至第五芯片5;第五芯片5通过打金线电性连接至基板9;第四芯片4通过打金线电性连接至第三芯片3;第三芯片3通过打金线连接至基板9;第二芯片2通过打金线电性连接至第一芯片1;第一芯片1通过打金线电性连接至基板9。
所述第一芯片1和第五芯片5的厚度为75um,所述第二芯片2、第三芯片3、第四芯片4、第六芯片6、第七芯片7和第八芯片8的厚度为55um。
所述芯片与芯片、芯片与基板9用胶带粘接,胶带厚度为10um。
所述基板的该底面配置多个用于焊接于PCB板的锡球12。
需要指出的是,以上所述者仅为用以解释本实用新型之较佳实施例,并非企图据以对本实用新型作任何形式上之限制,是以,凡有在相同之实用新型精神下所作有关本实用新型之任何修饰或变更,皆仍应包括在本实用新型意图保护之范畴。
Claims (5)
1.一种八层堆叠式芯片封装结构,其特征在于,包括:
一基板,具有相对的一顶面和一底面;
八个芯片,堆叠配置于所述基板的顶面上,其中二个芯片为一组,四组芯片呈交叉梯子形堆叠;
多根导线,电性连接于芯片和芯片之间和芯片和基板之间;
封装结构的封装空间内填充的绝缘树脂。
2.根据权利要求1所述的八层堆叠式芯片封装结构,其特征在于,所述八个芯片由下往上依次为第一芯片、第二芯片、第三芯片、第四芯片、第五芯片、第六芯片、第七芯片、第八芯片;其中,第八芯片通过打线结合技术电性连接至第七芯片;第七芯片通过打线结合技术电性连接至基板;第六芯片通过打线结合技术电性连接至第五芯片;第五芯片通过打线结合技术电性连接至基板;第四芯片通过打线结合技术电性连接至第三芯片;第三芯片通过打线结合技术电性连接至基板;第二芯片通过打线结合技术电性连接至第一芯片;第一芯片通过打线结合技术电性连接至基板。
3.根据权利要求2所述的八层堆叠式芯片封装结构,其特征在于,所述第一芯片和第五芯片的厚度为75um,所述第二芯片、第三芯片、第四芯片、第六芯片、第七芯片和第八芯片的厚度为55um。
4.根据权利要求3所述的八层堆叠式芯片封装结构,其特征在于,所述芯片与芯片、芯片与基板用胶带粘接,胶带厚度为10um。
5.根据权利要求4所述的八层堆叠式芯片封装结构,其特征在于,所述基板的该底面配置多个用于焊接于PCB板的锡球。
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CN103346150A (zh) * | 2013-06-26 | 2013-10-09 | 力成科技(苏州)有限公司 | 一种八层堆叠式芯片封装结构及其制造工艺 |
CN109755182A (zh) * | 2017-11-07 | 2019-05-14 | 中芯国际集成电路制造(上海)有限公司 | 芯片堆叠封装结构及其形成方法 |
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---|---|---|---|---|
CN103346150A (zh) * | 2013-06-26 | 2013-10-09 | 力成科技(苏州)有限公司 | 一种八层堆叠式芯片封装结构及其制造工艺 |
CN103346150B (zh) * | 2013-06-26 | 2015-12-02 | 力成科技(苏州)有限公司 | 一种八层堆叠式芯片封装结构及其制造工艺 |
CN109755182A (zh) * | 2017-11-07 | 2019-05-14 | 中芯国际集成电路制造(上海)有限公司 | 芯片堆叠封装结构及其形成方法 |
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