CN203013708U - 一种半导体管芯封装 - Google Patents

一种半导体管芯封装 Download PDF

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CN203013708U
CN203013708U CN2012204723025U CN201220472302U CN203013708U CN 203013708 U CN203013708 U CN 203013708U CN 2012204723025 U CN2012204723025 U CN 2012204723025U CN 201220472302 U CN201220472302 U CN 201220472302U CN 203013708 U CN203013708 U CN 203013708U
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semiconductor die
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韦泽锋
宋淑伟
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BYD Semiconductor Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48135Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • H01L2924/13055Insulated gate bipolar transistor [IGBT]

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Abstract

本实用新型提供一种半导体管芯封装结构,包括:衬底、半导体管芯、多个引脚以及模塑材料,所述半导体管芯位于衬底上,所述半导体管芯与多个引脚电连接,所述多个引脚上设置有通孔,所述模塑材料包覆衬底、半导体管芯以及多个引脚的一部分,且所述模塑材料填充于所述通孔。本实用新型结构的半导体管芯封装结构引脚底端与模塑材料结合牢固,引脚底端不容易从模塑材料中脱落,半导体管芯封装寿命长。

Description

一种半导体管芯封装
技术领域
本实用新型涉及电子器件领域,尤其涉及一种半导体管芯封装结构。
背景技术
半导体管芯封装例如IPM(Intelligent Power Module,智能功率模块)是一种新型的功率器件,其由高速低功耗的IGBT(Insulated Gate Bipolar Transistor,绝缘栅双极型晶体管)管芯和优化的栅极驱动电路以及快速保护电路组成。即IPM模块不仅把IGBT功率开关器件和驱动电路集成在一起,而且还具有过流、过热保护功能,即使发生负载短路或过热情况,也可以保护IPM模块不受损坏。由于IPM模块具有体积小,功率密度高,保护性能全面,工作可靠性高,使用方便等优点,越来越受到市场的欢迎,尤其适合于驱动电机的变频器和各种逆变电源,是变频调速、冶金机械、电力牵引、伺服驱动、变频家电的一种理想的电力电子器件,因而在市场上得到快速的发展。
但是目前市场上广泛使用的IPM模块,在使用的过程中其引脚容易脱落,由于其引脚的牢固程度是由引脚与模塑材料的接触面积的大小所决定,即与引脚底端与模塑材料接触的长度有关。当引脚底端与模塑材料接触的长度长时,其与模塑材料的接触面积就大,相互的结合力也大,引脚与模塑材料结合稳定,引脚底端不容易从模塑材料中脱落;相反地,当引脚底端与模塑材料接触的长度短时,其与模塑材料的接触面积就小,相互的结合力也小,引脚与模塑材料结合不稳定,引脚底端容易从模塑材料中脱落。
图1是现有技术提供的IPM模块结构图,参考图1,所述IPM模块包括衬底1,形成在衬底1上的半导体管芯2,包括第一端部31和第二端部32的多个引脚3,连接半导体管芯2和多个引脚3的第一端部31的引线4,包覆衬底1、半导体管芯2、引线4以及多个引脚3的第一端部31的模塑材料5。在现有技术的IPM模块结构中,IPM模块的多个引脚3仅靠第一端部31与模塑材料5进行连接,由于第一端部31与模塑材料5接触的长度和面积有限,在使用时间较长或者受到外界的撞击时,容易造成第一端部31的松动,甚至从模塑材料5中脱落。
目前已知的解决办法是尽量加大引脚底端与模塑材料接触的长度,但由于受IPM模块内部的结构布置、体积有限的影响以及成本考虑的因素,引脚底端与模塑材料接触的长度是有限,如此一来势必造成引脚底端和模塑材料的接触面积小,引脚底端与模塑材料的相互结合力小,因此当IPM模块在受到外部撞击或者使用时间较长时,容易造成引脚底端从模塑材料中脱落,从而影响IPM模块的寿命。
实用新型内容
本实用新型为解决上述技术问题,提供一种新型的半导体管芯封装结构。
一种半导体管芯封装,包括:衬底、半导体管芯、多个引脚以及模塑材料,所述半导体管芯位于衬底上,所述半导体管芯与多个引脚电连接,所述多个引脚上设置有通孔,所述模塑材料包覆衬底、半导体管芯以及多个引脚的一部分,且所述模塑材料填充于所述通孔。
进一步地,所述多个引脚环绕设置于衬底的周边上。
进一步地,所述每个引脚上均设有通孔。
进一步地,所述通孔位于所述多个引脚的中心位置上。
进一步地,所述多个引脚的其中一部分具有第一端部,所述通孔位于所述第一端部上。
进一步地,所述多个引脚的第一端部中的通孔呈圆柱形。
与现有技术相比,在本实用新型中,通过在多个引脚的第一端部和/或中心位置上设置通孔,当模塑材料包覆引脚底端时模塑材料填充所述通孔并沿着所述通孔的形状形成一个圆柱体,所述圆柱体与模塑材料形成为一体,这样会增加引脚底端与模塑材料的接触面积,增大引脚底端与模塑材料的相互结合力,提高引脚的抗拉力强度,避免IPM模块引脚底端从模塑材料中脱落,从而延长IPM模块的寿命。
附图说明
图1是本实用新型提供的一个现有技术的IPM模块结构图;
图2是本实用新型一个实施例的IPM模块的正面结构图;
图3是本实用新型一个实施例的IPM模块厚度方向的剖面结构图。
具体实施方式
为了使本实用新型所解决的技术问题、技术方案以及有益效果更加清楚明白,以下结合附图及实施例,对本实用新型进行进一步详细说明。应当理解,此处所描述的具体实施例仅仅用以解释本实用新型,并不用于限定本实用新型。
下面参考图2-3来描述根据本实用新型实施例的半导体管芯封装结构。在本实用新型中,所述半导体管芯封装是以一IPM模块封装为例。
图2是本实用新型一个实施例的IPM模块的正面结构图。一种IPM模块封装,包括:衬底1、半导体管芯2、多个引脚3、引线4以及模塑材料5,所述半导体管芯2位于衬底1上,所述半导体管芯2与多个引脚3电连接,所述多个引脚3上设置有通孔6,所述模塑材料5包覆衬底1、半导体管芯2、引线4和多个引脚3的一部分,且所述模塑材料5填充于所述通孔6。图3是本实用新型一个实施例的IPM模块厚度方向的剖面结构图。参考图3,在本实施例中,所述模塑材料5包覆多个引脚3的第一端部31和多个引脚3的中心位置33。在其他实施例中,也可以使用其他的方式,例如通过焊锡焊接的方式来电连接多个引脚3和半导体管芯2。在本实施例中,优选使用引线4来电连接多个引脚3和半导体管芯2。
在本实用新型中,将衬底1的长度与宽度所形成的平面的第一表面定义为衬底1的正面,将与衬底1的第一表面相对应的另一表面定义为衬底1的背面。将多个引脚3形成的表面的第一表面定义为引脚3的正面,将与多个引脚3的第一表面相对应的另一表面定义为引脚3的背面。应该理解的是,本实用新型所述的“第一表面”、“另一表面”、“正面”、“背面”仅仅用于解释本技术方案,并不用来限制本技术方案。
在具体实施中,所述衬底1可以呈片状、圆柱体、棱柱等形状。在本实施例中,所述衬底1优选呈片状。所述呈片状衬底1具有长度、宽度和厚度,且所述衬底1的厚度小于其长度和宽度。所述衬底1的第一表面(即正面)上设置有半导体管芯2。
在具体实施中,所述多个引脚3环绕设置于衬底1的周边上。也就是说,衬底1的长度与宽度所在平面的延伸方向上分布多个引脚3,所述多个引脚3环绕衬底1。参考图2,所述多个引脚3沿着衬底1的正面的延伸方向上分布,所述多个引脚3环绕衬底1。
参考图2或图3,在具体实施中,所述每个引脚3上均设有通孔6。
参考图3,在具体实施中,所述通孔6位于所述引脚3的中心位置33上。所述通孔6位于多个引脚3的中心位置33上,能够使多个引脚3的底端与模塑材料5的相互结合力均匀,避免IPM模块在受到外力作用下引脚3的底端向一侧移动,使得引脚3与模塑材料5的结合稳定。
在具体实施中,所述多个引脚3的其中一部分具有第一端部31,所述通孔6位于所述第一端部31上。
在具体实施中,所述通孔6可以呈任何形状,比如所述通孔6呈圆柱形、立方体、三棱柱等。在本实用新型中,所述通孔6优选呈圆柱体。参考图3,所述多个引脚3的底端设置通孔6,当模塑材料5包覆多个引脚3的底端时,模塑材料5会填充于多个引脚3的底端的通孔6中并且沿着通孔6的形状形成一个圆柱体,所述圆柱体与模塑材料5形成为一体,这样会增加引脚3的底端与模塑材料5的接触面积,增大引脚3的底端与模塑材料5的相互作用力,提高引脚3的抗拉力强度,避免引脚3的底端从模塑材料5中脱落,延长IPM模块的寿命。
与现有技术相比,在本实用新型中,通过在多个引脚的底端设置通孔,当模塑材料包覆多个引脚底端时,模塑材料填充所述通孔并沿着所述通孔的形状形成一个圆柱体,所述圆柱体与模塑材料形成为一体,这样会增加引脚底端与模塑材料的接触面积,增大引脚底端与模塑材料的相互结合力,提高引脚的抗拉力强度,避免IPM模块的引脚底端从模塑材料中脱落,延长IPM模块的寿命。
以上所述仅为本实用新型的较佳实施例而已,并不用以限制本实用新型,凡在本实用新型的精神和原则之内所作的任何修改、等同替换和改进等,均应包含在本实用新型的保护范围之内。

Claims (6)

1.一种半导体管芯封装,其特征在于,所述封装包括:衬底、半导体管芯、多个引脚以及模塑材料,所述半导体管芯位于衬底上,所述半导体管芯与多个引脚电连接,所述多个引脚上设置有通孔,所述模塑材料包覆衬底、半导体管芯以及多个引脚的一部分,且所述模塑材料填充于所述通孔。
2.如权利要求1所述的半导体管芯封装,其特征在于,所述多个引脚环绕设置于衬底的周边上。
3.如权利要求1所述的半导体管芯封装,其特征在于,所述每个引脚上均设有通孔。
4.如权利要求1所述的半导体管芯封装,其特征在于,所述通孔位于所述引脚的中心位置上。
5.如权利要求1所述的半导体管芯封装,其特征在于,所述多个引脚的其中一部分具有第一端部,所述通孔位于所述第一端部上。
6.如权利要求1-5任意一项所述的半导体管芯封装,其特征在于,所述通孔呈圆柱形。
CN2012204723025U 2012-09-17 2012-09-17 一种半导体管芯封装 Expired - Lifetime CN203013708U (zh)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108063123A (zh) * 2017-10-30 2018-05-22 张延赤 塑封电子器件回流焊时防止开裂的结构设计

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108063123A (zh) * 2017-10-30 2018-05-22 张延赤 塑封电子器件回流焊时防止开裂的结构设计

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