CN202352647U - 一种微电子封装 - Google Patents
一种微电子封装 Download PDFInfo
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Abstract
本实用新型公开了一种微电子封装。该微电子封装包括:半导体芯片,具有第一表面以及与第一表面相对的第二表面,其中在第一表面设置有键合点;引线框架,靠近半导体芯片,具有引脚;电耦接组件,耦接于半导体芯片的键合点与引线框架的引脚之间;以及塑型材料,具有第一表面以及与第一表面相对的第二表面,该塑型材料至少部分地封入半导体芯片、引线框架和电耦接组件;其中至少部分半导体芯片的第二表面通过塑型材料的第二表面暴露出来。
Description
技术领域
本实用新型涉及一种微电子封装。
背景技术
常见的半导体芯片或裸片常常被封入一个封装体中保护起来,以防因外部环境的影响而损坏。封装体还包括引脚和允许被封入芯片电耦接至另外部分(例如印制线路板PCB)的其他连接点。图1所示为现有的微电子封装100的剖视图。该微电子封装100采用芯片上引线封装结构,包括半导体芯片104、引线框架101和塑型材料110。半导体芯片104通过芯片粘着剂105粘附于引线框架101的引脚102上。键合线108把半导体芯片104的部分或全部焊点106与引线框架101的引脚102电连接在一起。彼此连接的半导体芯片104和引线框架101被封入塑型材料110内。
通常,各种微电子封装都要考虑如何将半导体芯片长期工作时聚集的热量散出的问题,不同的封装结构和材料会产生不同的散热效果。图1所示的微电子封装100采用芯片上引线封装结构,具有导热功能的芯片粘着剂105可以提供足够的散热路径将半导体芯片104产生的热量经引脚102传导到塑型材料110的外部。但是,如果微电子封装100采用其他类型的封装结构,如倒装芯片,半导体芯片104只能通过附着于引脚102上的焊料球或者焊料凸块(未画出)来进行散热。这样的封装结构缺乏足够的散热路径来耗散半导体芯片104产生的热量。
实用新型内容
本实用新型要解决的技术问题是提供一种具有增强散热功能的微电子封装。
根据本实用新型一实施例的微电子封装,包括半导体芯片,具有第一表面以及与第一表面相对的第二表面,其中在第一表面设置有键合点;引线框架,靠近半导体芯片,具有引脚;电耦接组件,耦接于半导体芯片的键合点与引线框架的引脚之间;以及塑型材料,具有第一表面以及与第一表面相对的第二表面,该塑型材料至少部分地封入半导体芯片、引线框架和电耦接组件;其中至少部分半导体芯片的第二表面通过塑型材料的第二表面暴露出来。
在一个实施例中,塑型材料具有从其第二表面向半导体芯片延伸的开口,至少部分半导体芯片的第二表面通过塑型材料的开口暴露出来。
在一个实施例中,塑型材料具有从其第二表面向半导体芯片延伸的多个开口,部分半导体芯片的第二表面通过塑型材料的多个开口暴露出来。
在一个实施例中,塑型材料的第二表面与半导体芯片的第二表面共平面。
在一个实施例中,微电子封装进一步包括制作于半导体芯片第二表面的热传导层,至少部分热传导层代替半导体芯片的第二表面从塑型材料的第二表面露出。
在一个实施例中,微电子封装进一步包括位于所述半导体芯片第二表面和热传导层之间的阻隔层。
在一个实施例中,塑型材料的第二表面与热传导层共平面。
在一个实施例中,塑型材料具有从其第二表面向半导体芯片延伸的开口,所述热传导层凹入塑型材料的开口中。
在一个实施例中,塑型材料具有从其第二表面向半导体芯片延伸的开口,至少部分热传导层通过塑型材料的开口暴露出来。
在一个实施例中,热传导层包括钛、镍、银三金属的合金。
在一个实施例中,引脚包括第一部分引脚和第二部分引脚,第一部分引脚通过电耦接组件耦接至半导体芯片的键合点,第二部分引脚暴露于塑型材料的外部。
附图说明
为了更好的理解本实用新型,将根据以下附图对本实用新型进行详细描述:
图1是现有的微电子封装100的剖视图;
图2是根据本实用新型一实施例的微电子封装200的剖视图;
图3A~3F是根据本实用新型一实施例的半导体芯片和引线框架在封装过程中的部分剖视图;
图4是根据本实用新型另一实施例的微电子封装的剖视图;
图5是根据本实用新型又一实施例的微电子封装的剖视图。
具体实施方式
下面参照附图描述本实用新型的实施例。封装有半导体芯片的封装体称为微电子封装,通常微电子封装在对半导体芯片电气性能造成最小化影响的同时对内部芯片和相关的元器件提供保护、供电、冷却,并提供与外部的电气和机械联系。典型的微电子封装包括微电子电路或元器件、薄膜记录头、数据存储单元、微流体装置和形成于微电子基板上的其它元件。微电子基板可包括半导体基片(如掺杂有硅或者砷化镓的晶圆)、绝缘片(如多种陶瓷基片)、或者导电片(如金属或者金属合金)。本文所称“半导体芯片”包括各种场合下使用的产品,包括如单个集成电路的芯片、成像芯片、感应芯片以及任何其它具有半导体特性的芯片。
本实用新型的实施例中,描述了很多关于半导体芯片的细节。本领域技术人员将理解,没有这些具体细节,本实用新型同样可以实施。本领域技术人员还应理解,尽管本实用新型中的详细描述与特定实施例相结合,但本实用新型仍有许多其他实施方式,在实际执行时可能有些变化,但仍然包含在本实用新型主旨范围内,因此,本实用新型旨在包括所有落入本实用新型和所述权利要求范围及主旨内的替代例、改进例和变化例等。
图2是根据本实用新型一实施例的微电子封装200的剖视图。该微电子封装200包括引线框架201、半导体芯片204、电耦接组件208和塑型材料210。其中引线框架201靠近半导体芯片204,半导体芯片204通过电耦接组件208耦接至引线框架201,塑型材料210至少部分地封入引线框架210、半导体芯片204和电耦接组件208。在一些实施例中,微电子封装200还包括转接板(interposer)、散热片和/或其他适合的元器件。
引线框架201包括多个引脚(lead finger)202。如图2所示,每个引脚202包括两部分,即封入塑型材料210内的第一部分202a和暴露于塑型材料210外部的第二部分202b。其中,引脚202的第一部分202a与相应的电耦接组件208耦接在一起,引脚202的第二部分202b用作与外部器件进行电气或机械联系的接口。在图2所示实施例中,引线框架201包括两个引脚202。在其它实施例中,引线框架201可包括任意数目的引脚、芯片焊盘(die paddles)和/或其他适合的部件。
半导体芯片204可包括各种集成电路器件。在一个实施例中,半导体芯片204包括多个金属氧化物半导体场效应晶体管(MOSFET)、结型场效应晶体管(JFET)、绝缘栅双极型晶体管(IGBT)、电容和/或其他元器件。在其它实施例中,半导体芯片204可包括任何其他可用的电气或者机械零件。
如图2所示,半导体芯片204具有第一表面204a以及与第一表面204a相对的第二表面204b。在半导体芯片204的第一表面204a设置有多个键合点206。每个键合点206与相应的电耦接组件208耦接在一起,而电耦接组件208与相应的引脚202顺序耦接。在一个实施例中,电耦接组件208包括附着于键合点206的焊料球。此处所称“焊料”是指熔点在90℃~450℃范围内的一种易熔金属合金。这种焊料可以是铜、锡、铅、银、锌和/或其他适用金属中至少几种金属的合金。在其它实施例中,电耦接组件208包括焊料凸块、金凸块、铜柱凸块和/或其他导电部件。
塑型材料210包括环氧树脂和/或其他热固性聚合物。如图2所示,塑型材料210具有第一表面210a以及与第一表面210a相对的第二表面210b。其中第一表面210a靠近引线框架201,第二表面210b靠近半导体芯片204的第二表面204b,至少部分半导体芯片204的第二表面204b通过塑型材料210的第二表面210b暴露出来。在一个实施例中,塑型材料210的第二表面210b与半导体芯片204第二表面204b是共平面的。在另一个实施例中,塑型材料210具有从其第二表面210b向半导体芯片204延伸的开口,至少部分半导体芯片204的第二表面204b通过塑型材料204的开口暴露出来。在又一个实施例中,塑型材料210具有从其第二表面210b向半导体芯片204延伸的多个开口,部分半导体芯片204的第二表面204b通过塑型材料210的多个开口暴露出来。
在一个实施例中,微电子封装200进一步包括制作于半导体芯片204第二表面204b的热传导层214,至少部分热传导层214代替半导体芯片204的第二表面204b从塑型材料210的第二表面210b露出。在进一步的实施例中,微电子封装200还包括阻隔层212,阻隔层212位于半导体芯片204的第二表面204b和热传导层214之间。在另一实施例中,省去热传导层214,仅在半导体芯片204的第二表面204b形成阻隔层212。
在一些实施例中,阻隔层212包括二氧化硅(SiO2)、氮化硅(Si3O4)和/或其他适合的绝缘材料。在其它实施例中,阻隔层212包括钨(W)、钽(Ta)、铼(Re)、氧化钽(Ta2O5)和/或其他适合的难熔材料及其氧化物。在进一步的实施例中,阻隔层212由前述多种材料均匀混合和/或分层叠加而成。
一般地,热传导层214包括可导热并且可软焊的的材料。这里所称的“可软焊”是指该材料在回流焊中可被迅速地附着上焊料。在一个实施例中,热传导层214包括钛、镍、银三金属的合金。在另一个实施例中,热传导层214包括铜、铝、银和/或其他在回流焊中可附着焊料的金属。在又一个实施例中,热传导层214包括热传导率高于0.5W/(m·k)的金属、金属合金和/或其他适用材料的混合物。
图2所示的实施例中,塑型材料210具有从其第二表面210b向半导体芯片204延伸的开口211,热传导层214通过开口211暴露出来。在一个实施例中,塑型材料210的第二表面210b与热传导层214是共平面的,这样整个热传导层214都通过开口211暴露出来。在其他实施例中,塑型材料210的开口211还有其他结构,将在图4和图5中给出具体说明。在这些实施例中,至少部分热传导层214通过塑型材料210的第二表面210b暴露出来。
与现有的微电子封装相比,微电子封装200具有更好的散热性能。在一些实际应用中,微电子封装200附着于承载基板220(如图2中的虚线所示)上。在一个实施例中,承载基板220包括印制线路板,该印制线路板包括散热焊盘224和多个接触焊盘222。位于半导体芯片204第二表面204b上的热传导层214通过焊锡膏、环氧树脂和/或其他适用的导热胶(未画出)直接接触散热焊盘224。引脚202的第二部分202b通过焊锡膏或者其他可用的导电物质(未画出)接触相应的接触焊盘222。在其它实施例中,承载基板220包括陶瓷基片和/或其他可用的基片。在进一步的实施例中,承载基板220还包括金属层、散热片和/或其他可用的部件。
在实际应用中,功率和/或数据信号从承载基板220经过接触焊盘222和引脚202被提供给半导体芯片204,然后半导体芯片204根据所提供的功率和/或数据信号执行一些预设的功能,如功率切换、信号处理等。在执行这些功能时,半导体芯片204就会产生热量。现有的微电子封装中,半导体芯片204产生的热量只能通过电耦接组件208、第一部分引脚202a和第二部分引脚202b传递到塑型材料210外部,这一散热路径称为第一散热路径。图2所示的微电子封装200中,除了第一散热路径外,半导体芯片204产生的热量还可通过第二散热路径来耗散:即半导体芯片产生的热量还可通过半导体芯片204的第二表面204b、阻隔层212以及接触承载基板220上散热焊盘224的热传导层214来耗散。这样,微电子封装200具有比现有的微电子封装更有效地散热效果。
图3A~3F是根据本实用新型一实施例的半导体芯片204和引线框架201在封装过程中的部分剖视图。如图3A所示,该封装过程的第一步包括采用背面研磨技术和/或其他技术来形成具有所需厚度的半导体芯片204。在一个实施例中,半导体芯片204的所需厚度与下列参数有关:(1)微电子封装200下半个体区的厚度(如图2所示的H);(2)电耦接组件208的支座高度。在其它实施例中,半导体芯片204的所需厚度由其他的参数决定。然后,该封装过程的第二步包括在半导体芯片204的第二表面204b制作阻隔层212。制作工艺可采用包括化学气相淀积(Chemical Vapor Deposition,CVD)工艺、原子层淀积(Atomic LayerDeposition,ALD)工艺和/或其他合适的淀积工艺。
图3B给出了进一步的淀积步骤,该步骤将热传导层214形成于阻隔层212的表面。在一个实施例中,热传导层214包括钛、镍、银三金属的合金,可通过CVD、ALD、溅镀、电淀积和/或其他适用的技术来制作。在其它实施例中,热传导层214可以通过丝网印制、胶粘和/或其他工艺与阻隔层212键合。
配置有阻隔层212和热传导层214的半导体芯片204被翻转,然后通过点焊、局部回流焊、电镀焊料凸块成型、焊球滴和/或其他可用的附着工艺将电耦接组件208附着于半导体芯片204的键合点206。然后,如图3C所示,半导体芯片204再次被翻转,并通过电耦接组件208附着于引线框架201上,如图3C中箭头217的方向所示。接着,半导体芯片204与引线框架201可通过回流焊(例如在回流焊炉中,未画出),以进一步稳固两者间的附着关系。
如图3D所示,该工艺的另一个步骤包括将引线框架201和半导体芯片204封入图2所示的塑型材料210中。塑型材料210通过模具240来制作,模具240包括位于引脚202上方的第一部分240a和位于引脚202下方的第二部分240b。半导体芯片204与引线框架201一起被置于模具240的内部空腔241内。在一个实施例中,热传导层214与模具240的空腔底面242平齐。在另一个实施例中,在模具240的下表面242上和热传导层214之间有缓冲材料,例如橡胶片(未画出)。缓冲材料至少有助于降低后面制作塑型材料210时半导体芯片204破裂和/或注入的塑形材料210掩蔽热传导层214的风险。在其它实施例中,热传导层214凹进内部空腔241的底面242,或者具有其他可用的结构。然后,将塑型材料210注入模具240的内部空腔241内并使之固化以封入引线框架201和半导体芯片204。
在一个实施例中,该封装过程还包括一些额外的后续处理步骤。例如,去除毛边的步骤,包括去除微电子封装200的底面和/或引脚202周围溢出的塑型材料。在其它实施例中,后续处理步骤还包括电镀引脚、截脚与整形、切割成单颗封装和/或其它可用的步骤。
参见图3A-3D,热传导层214淀积于阻隔层212之上。在其它实施例中,可采用其他原理将热传导层214制作或固定于半导体芯片204上。如图3E所示,在一个实施例中,如图3E所示,热传导层214包括经固-固结合或者粘着剂附着于阻隔层212上的热传导箔片216(铜箔或铝箔)。在另一个实施例中,如图3F所示,热传导层214包括构件230,其中构件230包括导热层232和粘结层234。在封装过程中,可在塑型材料210注入前或注入后将构件230附着于半导体芯片204的第二表面204b。
虽然在图2所示的实施例中,塑型材料210的第二表面与热传导层214是共平面的,在其它实施例中,塑型材料210可能凹陷入塑形材料210中。图4是根据本实用新型另一实施例的微电子封装的剖视图。其中塑形材料210具有从其第二表面210b向半导体芯片204延伸的开口231,热传导层214凹入塑型材料的开口231中,几乎整个热传导层214从开口231暴露出来。
在一个实施例中,可采用适当的模具(未画出)在封装过程中制作开口231。在另一个实施例中,可先使塑型材料210封入整个半导体芯片204,然后移除塑型材料210的一部分来制作开口231。在其他实施例中,可采用任何适用的技术来制作开口231。
在一个实施例中,将半导体芯片204安装至承载基板220时,可在开口231内填充焊料膏和/或可用的热传导材料。在另一个实施例中,在开口231内设置导热垫片,该导热垫片与热传导层214相接触。
图5是根据本实用新型又一实施例的微电子封装的剖视图。如图5所示,塑型材料210包括多个开口213,通过每个开口213露出热传导层214的一部分。可采用激光烧蚀、蚀刻和/或其他可用的技术来制作开口213。在安装至承载基板220之前,可在每个开口213中填充焊料膏250和/或其他可用的热传导材料。
上述本实用新型的说明书和实施仅仅以示例性的方式对本实用新型进行了说明,这些实施例不是完全详尽的,并不用于限定本实用新型的范围。对于公开的实施例进行变化和修改都是可能的,其他可行的选择性实施例和对实施例中元件的等同变化可以被本技术领域的普通技术人员所了解。本实用新型所公开的实施例的其他变化和修改并不超出本实用新型的精神和保护范围。
Claims (11)
1.一种微电子封装,包括:
半导体芯片,具有第一表面以及与第一表面相对的第二表面,其中在第一表面设置有键合点;
引线框架,靠近半导体芯片,具有引脚;
电耦接组件,耦接于半导体芯片的键合点与引线框架的引脚之间;以及
塑型材料,具有第一表面以及与第一表面相对的第二表面,该塑型材料至少部分地封入半导体芯片、引线框架和电耦接组件;
其中至少部分半导体芯片的第二表面通过塑型材料的第二表面暴露出来。
2.如权利要求1所述的微电子封装,其特征在于,所述塑型材料具有从其第二表面向半导体芯片延伸的开口,至少部分半导体芯片的第二表面通过塑型材料的开口暴露出来。
3.如权利要求1所述的微电子封装,其特征在于,所述塑型材料具有从其第二表面向半导体芯片延伸的多个开口,部分半导体芯片的第二表面通过塑型材料的多个开口暴露出来。
4.如权利要求1所述的微电子封装,其特征在于,所述塑型材料的第二表面与半导体芯片的第二表面共平面。
5.如权利要求1所述的微电子封装,其特征在于,微电子封装进一步包括制作于半导体芯片第二表面的热传导层,至少部分热传导层代替半导体芯片的第二表面从塑型材料的第二表面露出。
6.如权利要求5所述的微电子封装,其特征在于,微电子封装进一步包括位于所述半导体芯片第二表面和热传导层之间的阻隔层。
7.如权利要求5所述的微电子封装,其特征在于,所述塑型材料的第二表面与热传导层共平面。
8.如权利要求5所述的微电子封装,其特征在于,所述塑型材料具有从其第二表面向半导体芯片延伸的开口,所述热传导层凹入塑型材料的开口中。
9.如权利要求5所述的微电子封装,其特征在于,所述塑型材料具有从其第二表面向半导体芯片延伸的开口,至少部分热传导层通过塑型材料的开口暴露出来。
10.如权利要求5所述的微电子封装,其特征在于,所述热传导层包括钛、镍、银三金属的合金。
11.如权利要求1所述的微电子封装,其特征在于,所述引脚包括第一部分引脚和第二部分引脚,第一部分引脚通过电耦接组件耦接至半导体芯片的键合点,第二部分引脚暴露于塑型材料的外部。
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CN (2) | CN202352647U (zh) |
TW (1) | TWI485817B (zh) |
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US8629539B2 (en) * | 2012-01-16 | 2014-01-14 | Allegro Microsystems, Llc | Methods and apparatus for magnetic sensor having non-conductive die paddle |
US9812588B2 (en) | 2012-03-20 | 2017-11-07 | Allegro Microsystems, Llc | Magnetic field sensor integrated circuit with integral ferromagnetic material |
US9666788B2 (en) | 2012-03-20 | 2017-05-30 | Allegro Microsystems, Llc | Integrated circuit package having a split lead frame |
US10234513B2 (en) | 2012-03-20 | 2019-03-19 | Allegro Microsystems, Llc | Magnetic field sensor integrated circuit with integral ferromagnetic material |
US8810023B2 (en) | 2012-07-06 | 2014-08-19 | Texas Instruments Incorporated | Cantilever packages for sensor MEMS (micro-electro-mechanical system) |
CN103247542B (zh) * | 2012-08-10 | 2015-09-09 | 福建闽航电子有限公司 | 一种集成电路陶瓷封装外壳引出端的制作方法及专用引线框架 |
CN103035604B (zh) | 2012-12-17 | 2014-07-16 | 矽力杰半导体技术(杭州)有限公司 | 一种倒装芯片封装结构及其制作工艺 |
US9076783B2 (en) * | 2013-03-22 | 2015-07-07 | Freescale Semiconductor, Inc. | Methods and systems for selectively forming metal layers on lead frames after die attachment |
US9961798B2 (en) | 2013-04-04 | 2018-05-01 | Infineon Technologies Austria Ag | Package and a method of manufacturing the same |
CN103400819B (zh) | 2013-08-14 | 2017-07-07 | 矽力杰半导体技术(杭州)有限公司 | 一种引线框架及其制备方法和应用其的封装结构 |
US9678109B2 (en) * | 2014-01-09 | 2017-06-13 | Taiwan Semiconductor Manufacturing Co., Ltd. | Probe card |
CN105097727A (zh) * | 2015-06-23 | 2015-11-25 | 苏州日月新半导体有限公司 | 半导体封装结构及其封装方法 |
CN108352364B (zh) * | 2015-09-01 | 2021-07-13 | 马科技术解决方案控股公司 | 空气腔封装 |
US10892210B2 (en) * | 2016-10-03 | 2021-01-12 | Delta Electronics, Inc. | Package structures |
US10679929B2 (en) | 2017-07-28 | 2020-06-09 | Advanced Semiconductor Engineering Korea, Inc. | Semiconductor package device and method of manufacturing the same |
CN109411440A (zh) * | 2018-12-11 | 2019-03-01 | 杰群电子科技(东莞)有限公司 | 一种功率模块和功率模块加工方法 |
US10991644B2 (en) | 2019-08-22 | 2021-04-27 | Allegro Microsystems, Llc | Integrated circuit package having a low profile |
CN110767616A (zh) * | 2019-10-30 | 2020-02-07 | 太极半导体(苏州)有限公司 | 一种分拣倒装芯片的封盖高导热封装结构及其封装工艺 |
CN114615790A (zh) * | 2020-12-09 | 2022-06-10 | 深南电路股份有限公司 | 耦合器及电子设备 |
US20230059142A1 (en) * | 2021-08-17 | 2023-02-23 | Texas Instruments Incorporated | Flip chip packaged devices with thermal interposer |
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KR100209782B1 (ko) * | 1994-08-30 | 1999-07-15 | 가나이 쓰도무 | 반도체 장치 |
US6208513B1 (en) * | 1995-01-17 | 2001-03-27 | Compaq Computer Corporation | Independently mounted cooling fins for a low-stress semiconductor package |
US7572674B2 (en) * | 2002-09-26 | 2009-08-11 | Renesas Technology Corp. | Method for manufacturing semiconductor device |
TWI287275B (en) * | 2005-07-19 | 2007-09-21 | Siliconware Precision Industries Co Ltd | Semiconductor package without chip carrier and fabrication method thereof |
US7705476B2 (en) * | 2007-11-06 | 2010-04-27 | National Semiconductor Corporation | Integrated circuit package |
US7619303B2 (en) * | 2007-12-20 | 2009-11-17 | National Semiconductor Corporation | Integrated circuit package |
US20100252918A1 (en) * | 2009-04-06 | 2010-10-07 | Jiang Hunt H | Multi-die package with improved heat dissipation |
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US20120153446A1 (en) | 2012-06-21 |
US8283758B2 (en) | 2012-10-09 |
TW201240031A (en) | 2012-10-01 |
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