TWI520280B - 改善半導體封裝之散熱的系統和方法 - Google Patents
改善半導體封裝之散熱的系統和方法 Download PDFInfo
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Description
本發明大致上有關半導體封裝,且明確地是有關半導體晶片內之改善的散熱。
散熱在半導體晶片中係需要的。於該極端狀態中,如果半導體晶片被允許變得太熱,其能損壞該晶片。甚至在此極端狀態之外,半導體晶片被設計成在特別之溫度範圍內操作。為了將晶片維持在其操作溫度範圍內,熱必需被由該晶片所抽離。當晶片變成較高性能時,它們造成一較大的挑戰,因它們消耗更多功率及產生更多熱。
圖1說明典型之線接合、單沖切式封裝的橫截面。所製造之晶粒102係以晶粒附著劑104附著至基板106。所製造之晶粒102係經過接合線108經過接合墊110用電力存取。接合線108係亦連接至基板106上之I/O介面。該特定之I/O介面係視該封裝型式而定,但典型包括導通至該基板的底部或邊緣上之接腳或焊料球的一或更多層之金屬跡線。
於高功率應用中,模製化合物130能被附接至外部散熱器,且於該極端狀態中,該散熱器可甚至被耦接至電風扇。然而,為抵達該散熱器,該熱係首先經過該封裝材料抽出。為此目的,先前之解決方法已使用該封裝材料用之更昂貴的模製化合物,該材料具有較高之導熱度。然而,除了該費用以外,這些模製化合物係較不可靠,且於該轉移模製操作中係更難以使用。另一先前解決方法係包括內部散熱件140,如圖1所示。
半導體封裝包括具有I/O接點之基板、具有製造圖案及接合墊且附接至該基板之半導體晶粒、電耦接該等接合墊及該等I/O接點的接合線、及覆蓋該半導體晶粒的模製化合物。散熱件係藉由在該模製化合物接近至該晶粒之頂部表面中形成孔洞及以導熱材料充填該孔洞而內建於該半導體封裝。於一實施例中,該導熱材料亦覆蓋該模製化合物之頂部表面。導熱環氧基樹脂能被用作上述之導熱材料。金屬層能被附接在該封裝之頂部上。此一層能包括諸如焊料、銅、鋁或這些的一些組合之金屬。再者,散熱器能被附接在該封裝之頂部上,其可為具有散熱片的散熱器或金屬結塊、諸如銅或鋁結塊或該二者之組合。該散熱件可被使用於單沖切式及單鋸切式封裝,且該等封裝能包含雙列直插式封裝(DIP)封裝、接腳陣列封裝(PGA)封裝、無引線晶片載具(LCC)封裝、小型塑封積體電路(SOIC)封裝、塑膠引線晶片承載(PLCC)封裝、塑膠四周平面(PQFP)封裝與薄四周平面(TQFP)封裝、薄型小尺寸(TSOP)封裝、基板柵格陣列(LGA)封裝、及四方平面無引腳(QFN)封裝。
對應方法包括將該晶粒附接至具有I/O接點之基板、將接合線附接至接合墊及I/O接點、以模製化合物覆蓋該晶粒、於該模製化合物中形成孔洞、將導熱材料沉積進入該模製化合物中之孔洞、及切割個別之封裝。該方法能另包括將一層導熱材料沉積在該模製化合物之頂部表面上及/或將一層金屬沉積在該模製化合物之頂部表面上。諸如上述之金屬結塊或散熱器亦可被附接。
對於熟諳該技藝者於檢查以下之圖面及詳細敘述時,本揭示內容之其他系統、方法、特色、及優點將為或變得明顯。其係意欲使所有此等額外之系統、方法、特色、及優點被包含在此敘述內、係在本揭示內容之範圍內、及被所附申請專利範圍所保護。
本發明之實施例的詳細敘述被呈現在下面。雖然該揭示內容將關於這些圖面被敘述,在此不意圖將其限制至在此中所揭示之實施例或諸實施例。反而,其意圖涵蓋所有被包含在如藉由所附申請專利範圍所界定的揭示內容之精神及範圍內的另外選擇、修改及同等項。
於現代封裝中,半導體晶粒不再被個別地封裝,反之視該封裝型式而定,複數封裝係呈陣列地配置至大基板或金屬引線框。它們係為被線接合、及封入之群組。額外地,其他封裝之特定步驟亦可對該陣列之晶粒被施行。二差異存在於典型的單沖切式封裝及單鋸切式封裝之間。首先,單沖切式封裝典型具有個別之模套,故於該包覆製程期間,每一晶粒本質上具有離散之模子,反之於單鋸切式封裝中,該整個陣列係在單一模子之下封入。其次,於該單切製程期間(在此該陣列結構被細分成個別之封裝),衝壓機被使用於在單沖切式封裝中擊出每一個別之封裝,反之一鋸子被使用於切出單鋸切式封裝中之每一個別的封裝。因為衝壓機剪開個別封裝間之邊界,其有益的是不需切穿同樣多之材料,因此每一晶粒本質上具有其自身之離散的模套,反之鋸子可輕易地切穿基板及模製化合物。
大致上,半導體封裝之被鋸開的矩陣陣列係較小的封裝(例如具有本體尺寸4毫米-19毫米),反之單沖切式封裝係較大的封裝(例如19毫米-43毫米本體尺寸)。於單沖切式封裝中,散熱件能在該線接合製程之後、但在以模製化合物的包覆製程之前選擇性被加入。因為該較小尺寸之單鋸切式封裝及因為圍繞一整個封裝陣列的實心模子之不可彎曲性,由於在該模製製程期間所招致之翹曲,在包括單鋸切式封裝中之散熱件的企圖已證實不成功的。於對比下,既然每一晶粒在單沖切式封裝中本質上被個別地模製,整個封裝陣列係更撓性,並在該模製製程之後招致更少之翹曲,且因此在包含散熱件中不會遭遇同樣多之困難。
圖2顯示具有外加散熱件之單鋸切式半導體封裝的實施例。明確地是,封裝200被顯示為BGA封裝。像在該單沖切式半導體封裝中,所製造之晶粒202係以晶粒附著劑204附著至基板206。接合線208經過接合墊210將所製造之晶粒202電耦接至金屬跡線212。於所示之BGA範例中,基板206能包括多數層,且包含用於選路之額外的金屬跡線。金屬跡線212係經過通孔214連接至接合指部、諸如金屬跡線216。該基板的底部上之金屬跡線、諸如金屬跡線216包括焊料墊、諸如焊料墊218,在此焊料球、諸如焊料球220能在該製造廠被附著。焊料罩222覆蓋該基板的底部上之金屬跡線,但留下暴露該等焊料墊、諸如焊料墊218的開口。於一實施例中,模製化合物230覆蓋所製造之晶粒202、接合線208、及金屬跡線212。於另一實施例中(未示出),模製化合物230可大體上或完全地覆蓋所製造之晶粒202,但不須覆蓋接合線208及/或金屬跡線212。
模製化合物230具有形成進入該頂部表面之孔洞陣列、諸如藉由雷射鑽孔,該等孔洞被充填,且該表面以導熱材料240、諸如Dupont之CB100或Epotek H20E導熱材料所覆蓋。典型之導熱環氧基樹脂具有3-6W/m-K之導熱度。該等孔洞將導熱材料帶至極接近所製造之半導體晶粒。於一些實施例中,在異於直接在所製造晶粒202上方之區域的區域中形成孔洞係選擇性的。該層導熱材料能有助於將熱散逸進入該環境。用於該導熱材料之典型的厚度之範圍可約由2至10密爾。
為改善該散熱能力,金屬結塊或具有散熱片的散熱器可被附著至該導熱黏接劑。圖3顯示具有外加散熱件之單鋸切式半導體封裝的另一實施例。明確地是,封裝300被顯示為QFN封裝。再一次,所製造之晶粒302係以晶粒附著劑304附著至基板306。於此案例中,基板306係包括I/O墊312及熱墊314之金屬引線框。接合線308經過接合墊310電耦接所製造之晶粒302至I/O墊312。於一實施例中,模製化合物330覆蓋所製造之晶粒302、接合線308、及I/O墊312。於另一實施例中(未示出),模製化合物330可大體上或完全地覆蓋所製造之晶粒302,但不須接合線308及/或及I/O墊312。像在封裝200中,孔洞例如藉由雷射鑽孔被形成進入模製化合物330,且導熱材料340充填那些孔洞,並亦可覆蓋模製化合物330之表面。於一些實施例中,在異於直接在所製造晶粒302上方之區域的區域中形成孔洞係選擇性的。此外,散熱器350係以導熱材料340附接至該封裝。散熱器350可為如金屬結塊般簡單,或可為具有散熱片的散熱器。於一實施例中,散熱器350可為具有裝上發動機的風扇之散熱器。
圖4係流程圖,說明用於依照本發明之實施例封裝半導體晶粒的製程。在步驟402,所製造半導體晶粒的一陣列被附接至基板。如先前所論及,該特定基板視封裝之型式而定。譬如BGA封裝通常使用具有金屬層之多層基板,以選定電信號至其個別之輸出介面的路線。當另一範例,QFN封裝使用金屬引線框,且典型非多層式。在步驟404,每一製造半導體晶粒上之接合墊係線接合至該基板上之I/O接點。I/O接點之特定型式再一次視封裝之型式而定。譬如,BGA封裝通常具有在該表面上之金屬接合指部,其導通至被使用於選定信號至該外部I/O介面的路線之通孔,但於QFN封裝中具有I/O墊,其係單一件金屬。在步驟406,每一封裝被封入模製化合物中。於單鋸切式封裝之案例中,該整個封裝陣列可被以單一模子形式封入。於一實施例中,該模製化合物可僅只大體上或完全地覆蓋所製造之晶粒。
在步驟408,孔洞之陣列被形成於該模製化合物中、諸如藉由鑽孔。於一實施例中,該等孔洞被形成在每一製造半導體晶粒之上。使用雷射來鑽出該等孔洞利用在大部份封裝廠房中業已為標準之設備,且提供在所使用之比例所想要的深度及直徑控制。二氧化碳(CO2)或鐿鋁石榴石(YAG)雷射(釹或鉺YAG雷射的其中之一)能被使用來鑽出該等孔洞。於100加入及500微米間之孔洞直徑的範圍能被使用。該等孔洞之深度係視該晶粒上方之模製化合物的數量而定,但深度典型於50及200微米之間。
在步驟410,該陣列之孔洞被以導熱材料所充填。此外,一層導熱材料亦可被加入,以覆蓋該模製化合物之表面。模版印刷係將導熱材料施加至該模製化合物之表面的一常見之方式。
選擇性地在步驟412,額外之金屬層能被施加在該導熱材料之頂部上。譬如,一層金屬、諸如銅或焊料能被電鍍至該導熱材料上。另一選擇係在該導熱材料的頂部上模版印刷焊料。另一選項係橫越該整個封裝陣列施加金屬結塊。此增加之金屬層改善該封裝之散熱能力。
在步驟414,需要完成該封裝之額外步驟被施行。譬如,於BGA中,焊料球能被附接至該基板的底部上之焊料墊。在步驟416,該封裝陣列被單切成個別之封裝。用於單鋸切式封裝,此操作係藉由鋸子所執行。用於單沖切式封裝,衝壓機分開該等個別之封裝。
視該應用而定,其可為想要的是以顛倒順序施行步驟414及416。譬如,於一些高端應用中,BGA焊料球可在單切之後被附接。
圖5係流程圖,說明用於依照本發明之替代實施例封裝半導體晶粒的製程。步驟402、404、406、408、410、414及416係如上面敘述於圖4中者。然而,無加入額外金屬層之選擇性步驟。在步驟502,於單切之後,一些種類之散熱器係附接該模製化合物之表面。其可為金屬結塊,包括諸如銅或鋁之金屬。不論金屬結塊是否在單切之前被附接,諸如於圖4中之步驟412,或在單切之後,如於步驟502中,在此所敘述者視包含可用的結塊之尺寸及該目前可用設備的許多因素而定。另一選擇係,該散熱器可為具有散熱片的散熱器,在此該等散熱片增加用於散熱之額外表面。其甚至可具有裝上發動機的風扇之散熱器。
圖6-14進一步詳細地說明所敘述之製程。圖6顯示在步驟402之後的示範封裝陣列之橫截面視圖。半導體晶粒602被附接至基板606。圖7顯示在步驟402之後的示範封裝陣列之俯視圖。除了半導體晶粒602被附接至基板606以外,虛線702顯示個別封裝之範圍。為清楚故,它們被包含於該圖解中,且不須在該基板上表示任何物理標記。
圖8顯示在步驟404之後的示範封裝陣列之橫截面視圖。接合線802被使用來將每一製造半導體晶粒上之接合墊連接至該基板上之其個別的I/O接點。
圖9顯示在步驟406之後的示範封裝陣列之橫截面視圖。該整個封裝陣列係封入模製化合物902中。模製化合物902如所顯示延伸越過多數封裝。如上述,於一些實施例中(未示出),而非以模製化合物902覆蓋該整個封裝陣列,模製化合物902可僅只大體上或完全地覆蓋所製造之晶粒。
圖10顯示在步驟408之後的示範封裝陣列之橫截面視圖。諸如藉由參考箭頭1002所示之孔洞係形成於該模製化合物之表面中,如上面用於步驟408所更詳細地敘述者。在一些實施例中,異於直接該等晶粒上方之孔洞的孔洞係選擇性的。圖11顯示在步驟408之後的示範封裝陣列之俯視圖。再一次,虛線顯示每一個別封裝之範圍,但不須表示任何實際的物理標記。
圖12顯示在步驟410之後的示範封裝陣列之橫截面視圖。圖10及11所示孔洞係以導熱材料1202充填,如上面所述。此外,該模製化合物之表面係以一層典型於2及10密爾厚度之間的導熱材料所覆蓋。
圖13顯示在選擇性步驟412之後的示範封裝陣列之橫截面視圖。額外之金屬層1302被加至該導熱層之頂部。此額外之金屬層可為附接至該導熱層的金屬結塊或金屬箔片。另一選擇係,其可為電鍍在該導熱層的頂部上之金屬層。又另一選項為焊料層能被印刷在該導熱層之頂部上。雖然在上述圖4及5中有數個選項,圖13中所描述者係額外金屬層1302係在單切之前加入的製程。於該另一選擇中,沒有額外之金屬層1302被加入,或散熱器係在單切之後加入。
最後,圖14顯示在步驟414之後的示範封裝陣列之橫截面視圖。在步驟414,個別之封裝被單切所建立。間隙1402代表被使用於單切該封裝的鋸子之鋸溝。雖然該揭示內容主要使用單鋸切式封裝當作範例,個別之封裝亦可藉由單沖切所分開。
圖15顯示具有外加散熱件的單沖切式半導體封裝之實施例。於此範例中,封裝1500係包括附接至金屬引線框1506的所製造之晶粒1502的QFN封裝,該金屬引線框1506被裝在模製化合物1520中。金屬引線框1506包括I/O墊1510及熱墊1512。孔洞被鑽入模製化合物1520之頂部,並以導熱材料1504充填。此封裝能使用圖4中所敘述之方法被製成。選擇性地,額外之金屬層或散熱器能被放置在該導熱材料之頂部上。這是被顯示在以下之範例中。
圖16顯示具有外加散熱件的單沖切式半導體封裝之另一實施例。於此範例中,封裝1600係BGA封裝,包括附接著至裝在模製化合物1620內之基板1606的所製造之晶粒1602。基板1606能包括數層及如上面所述之金屬跡線。孔洞被鑽入模製化合物1620之頂部,並以導熱材料1604充填。此外,該散熱係藉由散熱器1630所輔助。此散熱器可僅只包括藉由附接金屬結塊、電鍍金屬或焊料層、或印刷焊料層的任一者所形成之金屬層。另一選擇係,該散熱器可為具有散熱片之散熱器或具有額外之冷卻機構、諸如風扇的散熱器。
尤其沉積進入該模製化合物中之孔洞的導熱黏接劑之外部散熱能力的使用可在很多狀態中被使用,在此內部散熱件係不可施行或沒有成本效益的。
應強調的是該等上述實施例係僅只可能的措失之範例。可對該等上述實施例作成很多變化及修改,而未由本揭示內容之原理脫離。譬如,該等上述實施例被給與用在BGA及QFN封裝,但可被適用於其他型式之封裝,包含、但不限於雙列直插式封裝(DIP)封裝、接腳陣列封裝(PGA)封裝、無引線晶片載具(LCC)封裝、小型塑封積體電路(SOIC)封裝、塑膠引線晶片承載(PLCC)封裝、塑膠四周平面(PQFP)封裝與薄四周平面(TQFP)封裝、薄型小尺寸(TSOP)封裝、基板柵格陣列(LGA)封裝、及二方平面無引腳(DFN)封裝。所有此等修改及變化係意欲在此中被涵括在此揭示內容之範圍內。
102...晶粒
104...晶粒附著劑
106...基板
108...接合線
110...接合墊
130...模製化合物
140...散熱件
200...封裝
202...晶粒
204...晶粒附著劑
206...基板
208...接合線
210...接合墊
212...金屬跡線
214...通孔
216...金屬跡線
218...焊料墊
220...焊料球
222...焊料罩
230...模製化合物
240...導熱材料
300...封裝
302...晶粒
304...晶粒附著劑
306...基板
308...接合線
310...接合墊
312...I/O墊
314...熱墊
330...模製化合物
340...導熱材料
350...散熱器
602...晶粒
606...基板
702...虛線
802...接合線
902...模製化合物
1002...箭頭
1202...導熱材料
1302...金屬層
1402...間隙
1500...封裝
1502...晶粒
1504...導熱材料
1506...金屬引線框
1510...I/O墊
1512...熱墊
1520...模製化合物
1600...封裝
1602...晶粒
1604...導熱材料
1606...基板
1620...模製化合物
1630...散熱器
該揭示內容之很多態樣可參考以下之圖面被更好了解。該圖面中之組件係不須按照一定比例,反之強調清楚地說明本揭示內容之原理,再者,於該等圖面中,遍及該數個圖面之類似參考數字標示對應的零件。
圖1說明傳統線接合、單沖切式封裝之橫截面;
圖2顯示具有外加散熱件之單鋸切式半導體封裝的實施例;
圖3顯示具有外加散熱件之單鋸切式半導體封裝的另一實施例;
圖4係流程圖,說明用於按照本發明之實施例來封裝半導體晶粒的製程;
圖5係流程圖,說明用於按照本發明之替代實施例來封裝半導體晶粒的製程;
圖6顯示在該等晶粒被附接之後的示範封裝陣列之橫截面視圖;
圖7顯示在該等晶粒被附接之後的示範封裝陣列之俯視圖;
圖8顯示在線接合之後的示範封裝陣列之橫截面視圖;
圖9顯示在包覆之後的示範封裝陣列之橫截面視圖;
圖10顯示在鑽孔之後的示範封裝陣列之橫截面視圖;
圖11顯示在鑽孔之後的示範封裝陣列之俯視圖;
圖12顯示在鑽孔之後的示範封裝陣列之橫截面視圖;
圖13顯示在選擇性沉積額外金屬層之後的示範封裝陣列之橫截面視圖;
圖14顯示在單切(singulation)之後的示範封裝陣列之橫截面視圖;
圖15顯示具有外加散熱件之單沖切式半導體封裝的實施例;及
圖16顯示具有外加散熱件之單沖切式半導體封裝的另一實施例。
200...封裝
202...晶粒
204...晶粒附著劑
206...基板
208...接合線
210...接合墊
212...金屬跡線
214...通孔
216...金屬跡線
218...焊料墊
220...焊料球
222...焊料罩
230...模製化合物
240...導熱材料
Claims (21)
- 一種半導體封裝,包括:基板;半導體晶粒,具有製造圖案及接合墊,該半導體晶粒附接至該基板;接合線,將該等接合墊附接至該基板;模製化合物,覆蓋該半導體晶粒和該基板的上表面,該模製化合物具有頂部表面與形成在該頂部表面中的複數孔洞,其中形成在該半導體晶粒上方的至少兩個孔洞比只形成在該基板上方的孔洞延伸進入該模製化合物更深;導熱材料,其充填該模製化合物的頂部表面中之該複數孔洞;及該導熱材料覆蓋該模製化合物的該頂表面,其中該模製化合物使該導熱材料和該基板分離。
- 如申請專利範圍第1項之半導體封裝,其中該導熱材料包括導熱環氧基樹脂。
- 如申請專利範圍第1項之半導體封裝,更包含在覆蓋該模製化合物之該頂表面的該導熱材料之頂部上的一層金屬。
- 如申請專利範圍第3項之半導體封裝,其中該層金屬包括焊料、銅、鋁、或其組合。
- 如申請專利範圍第1項之半導體封裝,另包括附接在覆蓋該模製化合物之該頂表面的該導熱材料的頂部上之散熱器。
- 如申請專利範圍第5項之半導體封裝,其中該散熱器係具有散熱片的散熱器。
- 如申請專利範圍第1項之半導體封裝,另包括附接在覆蓋該模製化合物之該頂表面的該導熱材料的頂部上之金屬結塊。
- 如申請專利範圍第7項之半導體封裝,其中該金屬結塊包括銅、鋁、或其組合。
- 如申請專利範圍第1項之半導體封裝,其中該半導體封裝係一種選自於由雙列直插式封裝(DIP)封裝、接腳陣列封裝(PGA)封裝、無引線晶片載具(LCC)封裝、小型塑封積體電路(SOIC)封裝、塑膠引線晶片承載(PLCC)封裝、塑膠四周平面(PQFP)封裝與薄四周平面(TQFP)封裝、薄型小尺寸(TSOP)封裝、基板柵格陣列(LGA)封裝、及四方平面無引腳(QFN)封裝所組成的群組之類型。
- 一種封裝複數半導體晶粒之方法,每一晶粒具有接合墊,該方法包括:將該複數半導體晶粒附接至基板;將接合線附接至該複數半導體晶粒之每一上的接合墊及該基板;以模製化合物覆蓋該複數半導體晶粒,該覆蓋步驟產生該模製化合物之頂部表面;於該模製化合物中形成複數孔洞,其中形成在該複數半導體晶粒之每一者上方的至少兩個孔洞比只形成在該基 板上方的孔洞延伸進入該模製化合物更深;將導熱材料沉積進入該模製化合物中之該複數孔洞內;及沉積該導熱材料,以覆蓋該模製化合物的該頂表面,其中該模製化合物使該導熱材料和該基板分離。
- 如申請專利範圍第10項封裝複數半導體晶粒之方法,另包括:將一層金屬沉積在該模製化合物之頂部表面上。
- 如申請專利範圍第11項封裝複數半導體晶粒之方法,其中該層金屬包括銅、鋁、焊料或其組合。
- 如申請專利範圍第10項封裝複數半導體晶粒之方法,另包括:將金屬結塊附接在覆蓋該模製化合物之該頂表面的該導熱材料的頂部上。
- 如申請專利範圍第13項封裝複數半導體晶粒之方法,其中該金屬結塊包括銅、鋁或其組合。
- 如申請專利範圍第10項封裝複數半導體晶粒之方法,另包括:將散熱器附接在覆蓋該模製化合物之該頂表面的該導熱材料的頂部上。
- 一種封裝半導體晶粒之方法,該半導體晶粒具有接合墊,該方法包括:將該半導體晶粒附接至基板;將接合線附接至該半導體晶粒上之接合墊及該基板; 以模製化合物覆蓋該半導體晶粒,該覆蓋步驟產生該模製化合物之頂部表面;於該模製化合物的頂部表面中形成複數孔洞,其中形成在該半導體晶粒上方的至少兩個孔洞比只形成在該基板上方的孔洞延伸進入該模製化合物更深;將導熱材料沉積進入該模製化合物中之該複數孔洞內;及沉積該導熱材料,以覆蓋該模製化合物的該頂表面,其中該模製化合物使該導熱材料和該基板分離。
- 如申請專利範圍第16項封裝半導體晶粒之方法,另包括:將一層金屬沉積在覆蓋該模製化合物之該頂表面的該導熱材料之頂部上。
- 如申請專利範圍第17項封裝半導體晶粒之方法,其中該層金屬包括銅、鋁、焊料或其組合。
- 如申請專利範圍第16項封裝半導體晶粒之方法,另包括:將金屬結塊附接在覆蓋該模製化合物之該頂表面的該導熱材料的頂部上。
- 如申請專利範圍第19項封裝半導體晶粒之方法,其中該金屬結塊包括銅、鋁或其組合。
- 如申請專利範圍第16項封裝半導體晶粒之方法,另包括:將散熱器附接在覆蓋該模製化合物之該頂表面的該導熱材料的頂部上。
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US12/925,828 US20120104591A1 (en) | 2010-10-29 | 2010-10-29 | Systems and methods for improved heat dissipation in semiconductor packages |
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US9232630B1 (en) * | 2012-05-18 | 2016-01-05 | Flextronics Ap, Llc | Method of making an inlay PCB with embedded coin |
US8721359B1 (en) | 2012-10-19 | 2014-05-13 | John O. Tate | Heat sink socket |
JP5998033B2 (ja) * | 2012-12-07 | 2016-09-28 | 株式会社ジェイデバイス | 半導体装置及びその製造方法 |
US9801277B1 (en) | 2013-08-27 | 2017-10-24 | Flextronics Ap, Llc | Bellows interconnect |
US9565748B2 (en) | 2013-10-28 | 2017-02-07 | Flextronics Ap, Llc | Nano-copper solder for filling thermal vias |
US20160064299A1 (en) * | 2014-08-29 | 2016-03-03 | Nishant Lakhera | Structure and method to minimize warpage of packaged semiconductor devices |
US9653373B2 (en) * | 2015-04-09 | 2017-05-16 | Samsung Electronics Co., Ltd. | Semiconductor package including heat spreader and method for manufacturing the same |
KR102427092B1 (ko) * | 2015-10-16 | 2022-08-01 | 삼성전자주식회사 | 열 정보 표지를 갖는 반도체 장치 |
US10321560B2 (en) | 2015-11-12 | 2019-06-11 | Multek Technologies Limited | Dummy core plus plating resist restrict resin process and structure |
US10431920B1 (en) | 2018-04-17 | 2019-10-01 | John O. Tate | One-piece parallel multi-finger contact |
WO2019236534A1 (en) * | 2018-06-04 | 2019-12-12 | Nano-Dimension Technologies, Ltd. | Direct inkjet printing of infrastructure for integrated circuits |
KR102554690B1 (ko) * | 2018-11-06 | 2023-07-13 | 삼성전자주식회사 | 반도체 패키지 |
KR20210024362A (ko) * | 2019-08-22 | 2021-03-05 | 삼성전자주식회사 | 반도체 패키지 |
US11482465B2 (en) * | 2019-10-18 | 2022-10-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Thermal interface materials, 3D semiconductor packages and methods of manufacture |
CN113544844A (zh) * | 2020-12-28 | 2021-10-22 | 英诺赛科(苏州)科技有限公司 | 半导体封装及其制造方法 |
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US7361986B2 (en) * | 2004-12-01 | 2008-04-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Heat stud for stacked chip package |
US20060209516A1 (en) * | 2005-03-17 | 2006-09-21 | Chengalva Suresh K | Electronic assembly with integral thermal transient suppression |
US8030755B2 (en) * | 2005-04-22 | 2011-10-04 | Stats Chippac Ltd. | Integrated circuit package system with a heat sink |
US20070108595A1 (en) * | 2005-11-16 | 2007-05-17 | Ati Technologies Inc. | Semiconductor device with integrated heat spreader |
JP5073756B2 (ja) * | 2006-12-21 | 2012-11-14 | アギア システムズ インコーポレーテッド | 回路ダイの熱的性能の高いパッケージング |
US20080315396A1 (en) * | 2007-06-22 | 2008-12-25 | Skyworks Solutions, Inc. | Mold compound circuit structure for enhanced electrical and thermal performance |
JP2010103244A (ja) * | 2008-10-22 | 2010-05-06 | Sony Corp | 半導体装置及びその製造方法 |
US7964951B2 (en) * | 2009-03-16 | 2011-06-21 | Ati Technologies Ulc | Multi-die semiconductor package with heat spreader |
US7863100B2 (en) * | 2009-03-20 | 2011-01-04 | Stats Chippac Ltd. | Integrated circuit packaging system with layered packaging and method of manufacture thereof |
US7875970B2 (en) * | 2009-06-10 | 2011-01-25 | Green Arrow Asia Limited | Integrated circuit package having a castellated heatspreader |
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US20120104591A1 (en) | 2012-05-03 |
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