CN202339911U - 带双凸点的四边扁平无引脚双ic芯片封装件 - Google Patents

带双凸点的四边扁平无引脚双ic芯片封装件 Download PDF

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CN202339911U
CN202339911U CN201120273639.9U CN201120273639U CN202339911U CN 202339911 U CN202339911 U CN 202339911U CN 201120273639 U CN201120273639 U CN 201120273639U CN 202339911 U CN202339911 U CN 202339911U
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chip
carrier
pin
pins
bonding
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郭小伟
慕蔚
何文海
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Tianshui Huatian Technology Co Ltd
Huatian Technology Xian Co Ltd
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Tianshui Huatian Technology Co Ltd
Huatian Technology Xian Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32135Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors

Abstract

本实用新型是一种带双凸点的四边扁平无引脚双IC芯片封装件。包括引线框架载体、粘片胶、IC芯片、内引脚、键合线、及塑封体,内引脚向内延伸靠近所述的载体,载体缩小,载体上粘接有第一IC芯片,第一IC芯片上端粘接第二IC芯片,内引脚底部的凹坑长度加长,每只内引脚在靠近载体一侧底面形成一外露的凸点,每只内引脚的外侧形成一外露的柱形外引脚,外露凸点上面的内引脚呈柱形内引脚,柱形内引脚上打接第一键合线和第三键合线,第一键合线另一端与第一IC芯片焊接,第三键合线另一端与所述第二IC芯片焊接。本实用新型的特点载体缩小,提高了芯片和载体匹配性。缩小了IC芯片上的焊盘与内引脚间的距离引脚不悬空,减少了引线长度,节约焊线成本,还可提高频率特性。

Description

带双凸点的四边扁平无引脚双IC芯片封装件
技术领域
本实用新型涉及电子信息自动化元器件制造技术领域,特别是一种带双凸点的四边扁平无引脚双IC芯片封装件。
背景技术    
近年来,移动通信和移动计算机领域的便捷式电子机器市场火爆,直接推动了小型封装和高密度组装技术的发展。同时,也对小型封装技术提出了一系列严格要求,诸如,要求封装外形尺寸尽量缩小,尤其是封装高度小于1㎜;封装后的产品可靠性尽可能提高,为了保护环境适应无铅化焊接,并力求降低成本等。QFN(Quad Flat Non-Leaded Package方形扁平无引脚封装)由于具有良好的电和热性能、体积小、重量轻、其应用正在快速增长。但是目前如QFN(0505×0.75-0.50)~QFN(0909×0.75-0.50)载体较大,通常内引脚长度固定,靠近载体的内引脚底面已被蚀刻成凹坑,而当IC芯片较小时,从芯片焊盘到引脚部分的距离较大,由于靠近载体的引脚底面悬空,打线时会晃动,焊球打不牢,只能在靠近外露引脚部分打线,致使焊线长度长,造成焊线成本较高,制约了产品的利润空间。
实用新型内容
本实用新型所要解决的技术问题就是针对上述QFN缺点,提供一种缩小了载体尺寸,所有的内引脚向内延伸靠近载体,从芯片上的焊盘(PAD)到内引脚的距离缩短,从而缩短从芯片焊盘到内引脚的焊线长度,降低焊线成本,适合于小芯片的一种带双凸点的四边扁平无引脚双IC芯片封装件。
本实用新型的技术问题通过下述技术方案解决:
一种带双凸点的四边扁平无引脚双IC芯片封装件,包括引线框架载体、粘片胶、IC芯片、内引脚、键合线、及塑封体,所述的内引脚向内延伸靠近所述的载体,载体缩小,所述内引脚底部的凹坑长度加长,每只内引脚在靠近载体一侧底面形成一外露的凸点,每只内引脚的外侧形成一外露的柱形外引脚,所述外露凸点上面的内引脚呈柱形内引脚,柱形内引脚上打接第一键合线和第三键合线,第一键合线另一端与第一IC芯片焊接,所述第三键合线另一端与所述第二IC芯片焊接,所述的第二IC芯片粘接在第一IC芯片上端。
所述第一IC芯片与第二IC芯片之间连接有第二键合线。
所述的内引脚向内延伸0.2mm~0.8mm。
所述的载体缩小0.4mm~1.6mm。
所述凹坑长度加长0.2mm~0.5mm,凹坑的内侧是所述的外露凸点,凹坑的外侧是所述的外露的柱形外引脚。
本实用新型的特点是载体缩小,内引脚向内延伸靠近载体,并且延伸部分的底部外露形成一个小凸点,引脚底部的凹坑较大,凹坑外侧是外露的柱形外引脚,而柱形外引脚的外露部分同普通引脚框架。这样,载体缩小,提高了芯片和载体的匹配性,同时提高了产品封装质量和可靠性。内引脚延伸并露出凸点,缩小了IC芯片上的焊盘与内引脚间的距离,并且可以将焊线打在外露凸点上面的引脚上,此时引脚不悬空,减少了引线长度,不仅可以节约焊线成本,而且还可提高频率特性。
附图说明
图1为本实用新型外露凸点的压焊平面示意图。
图2为本实用新型芯片堆叠封装剖面示意图。
图3为本实用新型外露凸点底面示意图。
图中标号说明:1—载体,2—粘片胶,3—第一IC芯片,4—内引脚,5—第一键合线,6—塑封料,7—第二粘片胶 ,8—第二IC芯片,9—第二键合线,10—柱形外引脚12—第三键合线,15—外露凸点,16—凹坑。
具体实施方式
下面结合附图对本实用新型进行详细说明:
本实用新型包括引线框架载体、粘片胶、IC芯片、内引脚、键合线、及塑封体,内引脚4向内延伸靠近载体1,载体1缩小,内引脚底部凹坑16长度加长,每只内引脚4在靠近载体一侧底面形成一外露的凸点15,外露凸点15上面的内引脚呈柱形引脚,柱形引脚的底面有一凹坑16,凹坑16的外侧是外露的柱形引脚10。柱形内引脚4上打接第一键合线5和第三键合线12,第一键合线5另一端与第一IC芯片焊接,第三键合线12另一端与第二IC芯片8焊接。第一IC芯片3上端通过绝缘胶7粘接第二IC芯片8。第二IC芯片8与第一IC芯片3之间连接有第二键合线9。塑封体6包围了引线框架载体1,粘片胶(绝缘胶或导电胶)2,第一IC芯片3,内引脚4,第一键合线5,绝缘胶7, 第二IC芯片8,第二键合线9,第三键合线12,凸点15,凹坑16构成了电路整体,并对其起到了保护作用。本实用新型的内引脚4向内延伸0.2mm~0.8mm;载体1缩小0.4mm~1.6mm;内引脚底部的凹坑16长度加长0.2mm~0.5mm。
本实用新型的生产方法如下:
a.减薄
8〞~12〞晶圆厚度减薄机,下层芯片减薄厚度200μm,粗糙度Ra 0.10mm,同常规QFN减薄;上层芯片减薄厚度100μm,粗糙度Ra 0.05mm,采用防翘曲、抛光工艺; 
b.划片
8〞~12〞划片机,下层芯片减薄厚度200μm,采用普通QFN划片工艺,
上层芯片减薄厚度100μm,采用防碎片划片工艺;
 c.上芯
粘片材料: 底层粘片采用膨胀系数80~195PPM/℃、低吸水率<0.15%的导电胶或绝缘胶,上层芯片采用绝缘胶,引线框架选用带双凸点的四面扁平无引脚框架,分别采用防分层烘烤工艺;
d.压焊
焊线材料选用金线,压焊采用低弧度压焊工艺,高低弧正反打线方式,焊线温度150℃~210℃;先在金线键合机上给第二IC芯片8和第一IC芯片3间焊线的焊盘上各植1 个金球,然后给第二IC芯片8和第一IC芯片3已植金球间打第二键合线9,最后给第一IC芯片3、第二IC芯片8和对应的内引脚间打第一键合线5和第三键合线12;
e.塑封
采用通用QFN自动包封系统,选用低应力、低吸水率的塑封料, 模温165℃~180℃,注塑压力30~35Kgf/C㎡;
f.电镀和打印
同普通QFN工艺;
g.切割
将矩阵式框架封装产品按产品设计规格切割成单个电路,经检查后,放入料盘。

Claims (5)

1.一种带双凸点的四边扁平无引脚双IC芯片封装件,包括引线框架载体、粘片胶、IC芯片、内引脚、键合线、及塑封体,其特征在于所述的内引脚(4)向内延伸靠近所述的载体(1),载体(1)缩小,载体(1)上粘接有第一IC芯片(3),第一IC芯片(3)上端粘接第二IC芯片(8),所述内引脚底部的凹坑(16)长度加长,每只内引脚(4)在靠近载体一侧底面形成一外露的凸点(15),每只内引脚(4)的外侧形成一外露的柱形外引脚(10),所述外露凸点(15)上面的内引脚呈柱形内引脚(4),柱形内引脚(4)上打接第一键合线(5)和第三键合线(12),第一键合线(5)另一端与第一IC芯片(3)焊接,所述第三键合线(12)另一端与所述第二IC芯片(8)焊接。
2.根据权利要求1所述的一种带双凸点的四边扁平无引脚双IC芯片封装件,其特征在于所述第一IC芯片(3)与第二IC芯片(8)之间连接有第二键合线(9)。
3.根据权利要求1或2所述的一种带双凸点的四边扁平无引脚双IC芯片封装件,其特征在于所述的内引脚(4)向内延伸0.2mm~0.8mm。
4.根据权利要求1所述的带双凸点的四边扁平无引脚双IC芯片封装件,其特征在于所述的载体(1)缩小0.4mm~1.6mm。
5.根据权利要求1所述的带双凸点的四边扁平无引脚双IC芯片封装件,其特征在于所述凹坑(16)长度加长0.2mm~0.5mm,凹坑(16)的内侧是所述的外露凸点(15),凹坑(16)的外侧是所述的外露的柱形外引脚(20)。
CN201120273639.9U 2011-07-29 2011-07-29 带双凸点的四边扁平无引脚双ic芯片封装件 Expired - Fee Related CN202339911U (zh)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102263081A (zh) * 2011-07-29 2011-11-30 天水华天科技股份有限公司 带双凸点的四边扁平无引脚双ic芯片封装件及其生产方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102263081A (zh) * 2011-07-29 2011-11-30 天水华天科技股份有限公司 带双凸点的四边扁平无引脚双ic芯片封装件及其生产方法

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