CN201708157U - 结型场效应晶体管结构 - Google Patents

结型场效应晶体管结构 Download PDF

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CN201708157U
CN201708157U CN2010202427371U CN201020242737U CN201708157U CN 201708157 U CN201708157 U CN 201708157U CN 2010202427371 U CN2010202427371 U CN 2010202427371U CN 201020242737 U CN201020242737 U CN 201020242737U CN 201708157 U CN201708157 U CN 201708157U
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layer
injection
substrate
jfet
jfet structure
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余荣伟
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IPGoal Microelectronics Sichuan Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
    • H01L29/808—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a PN junction gate, e.g. PN homojunction gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure
    • H01L29/7832—Field effect transistors with field effect produced by an insulated gate with multiple gate structure the structure comprising a MOS gate and at least one non-MOS gate, e.g. JFET or MESFET gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

一种结型场效应晶体管结构，其包括一栅极、一源极、一漏极及一衬底，所述栅极包括一多晶硅层及一P注入层，所述源极包括一N注入层、一N阱层及一深注入N阱层，所述漏极包括所述N注入层、所述N阱层及所述深注入N阱层，一衬底连接端通过所述P注入层、一P阱层、一深注入P阱层及一P型埋层连接所述衬底。该结构在现有工艺上无须增加任何掩摸步骤即可制作出来，且该结构具有耐高压特性的优点，不但满足了实际应用中的要求，而且结构紧凑，工艺兼容。

Description

结型场效应晶体管结构
技术领域
本实用新型涉及一种晶体管结构，尤指一种具有耐高压特性的结型场效应晶体管结构。
背景技术
在电源芯片中，常常用到结型场效应晶体管(JFET，Junction Field Effect Transistor)结构。JFET为一种单极的三层晶体管，它是一种控制极是由PN组成的场效应晶体管，工作依赖于一种载流子-电子或空穴的运动。对于一个“正常接通”器件，每当N沟道JFET的漏极电压相对于源极为正时，或是当P沟道JFET的漏极电压相对于源极为负时，都有电流在沟道中流过。在JFET沟道中的电流受栅极电压的控制，为了“夹断”电流的流动，在N沟道JFET中栅极相对源极的电压必须是负的；或者在P沟道JFET中栅极相对源极的电压必须是正的。栅极电压被加在横跨PN结的沟道上，与此相反，在MOSFET中则是加在绝缘体上。
在实际应用中，往往需要一种耐高压的JFET结构，因此有必要针对实际应用中的需求提供一种具有耐高压特性的新颖的JFET结构。
发明内容
鉴于以上内容，有必要提供一种具有耐高压特性的结型场效应晶体管结构。
一种结型场效应晶体管结构，其包括一栅极、一源极、一漏极及一衬底，所述栅极包括一多晶硅层及一P注入层，所述源极包括一N注入层、一N阱层及一深注入N阱层，所述漏极包括所述N注入层、所述N阱层及所述深注入N阱层，一衬底连接端通过所述P注入层、一P阱层、一深注入P阱层及一P型埋层连接所述衬底。
优选地，所述漏极位于所述结型场效应晶体管结构的中心，所述源极位于所述漏极的四周，所述栅极位于所述漏极与所述源极之间。
优选地，所述结型场效应晶体管结构还包括一场氧层及一与所述场氧层相邻的N型外延层。
优选地，所述衬底为P型衬底，所述衬底连接端为P型衬底连接端。
优选地，所述结型场效应晶体管结构为一种N沟道的结型场效应晶体管结构。
相对现有技术，本实用新型结型场效应晶体管结构在现有工艺上无须增加任何掩摸步骤即可制作出来，且该结构具有耐高压特性的优点，不但满足了实际应用中的要求，而且结构紧凑，工艺兼容。
附图说明
图1为本实用新型结型场效应晶体管结构较佳实施方式的平面示意图。
图2为本实用新型结型场效应晶体管结构较佳实施方式的剖面示意图。
图3为本实用新型结型场效应晶体管结构较佳实施方式的电学特性曲线。
具体实施方式
请参阅图1，本实用新型结型场效应晶体管结构较佳实施方式包括一漏极D、一源极S、一栅极G及一P型衬底PSUB。其平面电极关系如图1所示，该漏极D位于中心，该源极S位于漏极D的四周，该栅极G位于漏极D与源极S之间。
请同时参阅图2，图2为沿图1的45度对角方向切割的剖面示意图，即沿箭头所示方向进行切割后的一剖面示意图。由图中可以看出，该结型场效应晶体管的剖面结构包括一场氧层FOX、一P注入层P+、一P阱层LVPW、一深注入P阱层HVPW、一N型外延层NEPI、一N注入层N+、一N阱层LVNW、一深注入N阱层HVNW、一P型埋层PBL、一多晶硅层POLY、P型衬底PSUB、漏极D、源极S、栅极G及一P型衬底连接端SUB。
其中，源极S包括该N注入层N+、该N阱层LVNW及该深注入N阱层HVNW；漏极D包括该N注入层N+、该N阱层LVNW及该深注入N阱层HVNW；栅极G包括该多晶硅层POLY及该P注入层P+；P型衬底连接端SUB通过P注入层P+、P阱层LVPW、深注入P阱层HVPW及P型埋层PBL连接该P型衬底PSUB。
请参阅图3，图3为本实用新型结型场效应晶体管结构较佳实施方式的电学特性曲线。其电学特性与普通场效应管的电学特性相似，其中Vp为夹断电压，Id为漏极电流，Vds为漏源电压。
本发明是基于N型外延BiCMOS工艺设计出的JFET器件结构。图1所示为N沟道JFET版图。N沟道JFET为采用深注入N阱层HVNW为沟道的耗尽形管，漏极S与源极D采用低压N阱层LVNW扩散，再注入N型杂质。栅用P型杂质注入加多晶硅层POLY覆盖。背栅用P埋层推入。整个器件放在P型隔离岛内。N深阱JFET的沟道宽度越小，夹断电压就越小。本结构在电源管理与模拟电路中给电路设计人员提供了一种设计选择，例如在模拟开关电路、偏置电路和替代启动电路中的高值电阻及需要耐高压的地方等。
本实用新型基于BiCMOS工艺提出了一种新颖的JFET结构，这种结构在现有工艺上无须增加任何掩摸步骤即可制作出来，且具有该结构的JFET具有耐高压特性等优点，不但满足了实际应用中的要求，而且结构紧凑，工艺兼容。

Claims (5)

1.一种结型场效应晶体管结构，其包括一栅极、一源极、一漏极及一衬底，其特征在于：所述栅极包括一多晶硅层及一P注入层，所述源极包括一N注入层、一N阱层及一深注入N阱层，所述漏极包括所述N注入层、所述N阱层及所述深注入N阱层，一衬底连接端通过所述P注入层、一P阱层、一深注入P阱层及一P型埋层连接所述衬底。
2.如权利要求1所述的结型场效应晶体管结构，其特征在于：所述漏极位于所述结型场效应晶体管结构的中心，所述源极位于所述漏极的四周，所述栅极位于所述漏极与所述源极之间。
3.如权利要求1所述的结型场效应晶体管结构，其特征在于：所述结型场效应晶体管结构还包括一场氧层及一与所述场氧层相邻的N型外延层。
4.如权利要求1所述的结型场效应晶体管结构，其特征在于：所述衬底为P型衬底，所述衬底连接端为P型衬底连接端。
5.如权利要求1所述的结型场效应晶体管结构，其特征在于：所述结型场效应晶体管结构为一种N沟道的结型场效应晶体管结构。
CN2010202427371U 2010-06-30 2010-06-30 结型场效应晶体管结构 Expired - Fee Related CN201708157U (zh)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102299183A (zh) * 2011-09-22 2011-12-28 上海先进半导体制造股份有限公司 Jfet晶体管及其形成方法
CN102610656A (zh) * 2011-01-19 2012-07-25 上海华虹Nec电子有限公司 耐高压的结型场效应管
CN103094124A (zh) * 2011-11-04 2013-05-08 上海华虹Nec电子有限公司 高压结型场效应管的结构及制造方法

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US9087920B2 (en) * 2012-06-01 2015-07-21 Taiwan Semiconductor Manufacturing Company, Ltd. Vertical power MOSFET and methods of forming the same
US9190536B1 (en) * 2014-06-05 2015-11-17 Macronix International Co., Ltd. Junction field effect transistor
US9543452B1 (en) 2015-07-01 2017-01-10 Macronix International Co., Ltd. High voltage junction field effect transistor
CN105679820B (zh) * 2016-03-16 2018-08-21 上海华虹宏力半导体制造有限公司 Jfet及其制造方法

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DE102004018153B9 (de) * 2004-04-08 2012-08-23 Austriamicrosystems Ag Hochvolt-Sperrschicht-Feldeffekttransistor mit retrograder Gatewanne und Verfahren zu dessen Herstellung
KR100847306B1 (ko) * 2007-02-14 2008-07-21 삼성전자주식회사 반도체 장치 및 이의 제조 방법

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102610656A (zh) * 2011-01-19 2012-07-25 上海华虹Nec电子有限公司 耐高压的结型场效应管
CN102610656B (zh) * 2011-01-19 2014-04-16 上海华虹宏力半导体制造有限公司 耐高压的结型场效应管
CN102299183A (zh) * 2011-09-22 2011-12-28 上海先进半导体制造股份有限公司 Jfet晶体管及其形成方法
CN102299183B (zh) * 2011-09-22 2013-10-09 上海先进半导体制造股份有限公司 Jfet晶体管及其形成方法
CN103094124A (zh) * 2011-11-04 2013-05-08 上海华虹Nec电子有限公司 高压结型场效应管的结构及制造方法
CN103094124B (zh) * 2011-11-04 2015-08-19 上海华虹宏力半导体制造有限公司 高压结型场效应管的结构及制造方法

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