CN1959970A - 半导体装置 - Google Patents

半导体装置 Download PDF

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CN1959970A
CN1959970A CNA2006101432012A CN200610143201A CN1959970A CN 1959970 A CN1959970 A CN 1959970A CN A2006101432012 A CNA2006101432012 A CN A2006101432012A CN 200610143201 A CN200610143201 A CN 200610143201A CN 1959970 A CN1959970 A CN 1959970A
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CN100492626C (zh
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松浦和良
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Renesas Electronics Corp
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Abstract

一种即使为了保持压接时的平衡而设置了加强用的假端子，也能在芯片上设置更多的电路元件的半导体装置。它是用于COG实装的半导体装置(10)，具备：在芯片的一端部的近旁按第1图形配置了的输出端子群(12f)；以及配置在与所述芯片的一端部的近旁，即配置了输出端子群(12f)的区域分开的区域，并且按与第1图形不同的第2图形配置了的假端子(12d)。第2图形构成为，宽度比第1图形窄。在假端子(12d)的近旁，在输出端子群(12f)的长度方向旁边配置了电路元件部(14)。

Description

半导体装置
技术领域
本发明涉及半导体装置，特别涉及用于COG实装的半导体装置。
背景技术
近几年，液晶面板不仅用于电视、个人电脑监视器这样的比较大型的显示器，而且用于手机等小型显示器等各种领域，作为显示用显示器起着很大作用。其中，MP3等各种媒体、便携游戏等的增长惊人，与此相伴的小型·轻量化、低成本化的要求越来越强。
然而，驱动液晶显示器的驱动器IC(IC芯片)近几年正在对驱动电路、电源电路等多个电路进行1芯片化。作为驱动器IC的实装方法，不仅有在液晶面板上连接搭载了QFP(Quad flatpackage)型、SOP(SmallOutline Package)型驱动器IC的承载膜的TAB(Tape Automated Bonding)实装，还增加了在液晶面板的玻璃基板上直接实装驱动器IC的COG(Chip on Glass)实装。通过COG实装，可以期待能为了液晶显示器的高清晰化、更薄型、轻量、紧凑化而以管脚连接节距的精细化来对应，并且减少使用材料、工数而实现低成本化。
此处，用附图来说明COG实装。图9是表示现有例1所涉及的半导体装置(IC芯片)的构成的概略图，(a)是背面侧的平面图，(b)是半导体装置的X-X′间的部分剖视图。图10是表示在玻璃基板上按COG实装了现有例1所涉及的半导体装置(IC芯片)时的构成的概略图，(a)是平面图，(b)是Y-Y′间的部分剖视图。
在COG实装中，在COG实装用的IC芯片110的端子112上面形成焊垫113(Au等)(参照图9)，在IC芯片110和玻璃基板130之间夹持在粘着剂121中分散导电粒子122所得的各向异性导电膜120(ACF：Anisotropic Conductive Film)，用工具(未图示)进行加热加压，通过焊垫113及导电粒子122来电连接IC芯片110的端子112和玻璃基板130上面形成了的端子131，由粘着剂121进行端子112、131间的固定保持(参照图10)。在COG实装中，压接时的平衡非常重要。如果实装压接平衡差的东西的话，在用工具(未图示)按住时，就可能引起负荷偏向、芯片损坏、玻璃基板130上面的布线(未图示)的断开，或者各向异性导电膜120均匀性不充分、端子112、131间的电连接不良。在研究端子配置时，必须考虑连接强度及连接电阻等，使得每1芯片的端子面积成为给定的面积以上来决定尺寸、个数，并且以在实装时芯片不会倾斜的平衡进行端子配置。
其次，用附图来说明多个电路被1芯片化了的现有IC芯片。图11～图13是示意地表示现有例2～4所涉及的半导体装置(IC芯片)的构成的背面侧的平面图。
参照图11(现有例2)，此IC芯片110在背面的长度方向(较长方向)的一端部的近旁具有按2列交错配置了的第1输出端子112a和第2输出端子112b，在背面的长度方向(较长方向)的另一端部的近旁具有按1列配置了的输入端子112c。还有，IC芯片110在第2输出端子112b和输入端子112c之间在宽度方向(较短方向)排列配置了逻辑电路部111和追加电路部114。长度方向(较长方向)尺寸根据输出端子数来决定。
参照图12(现有例3)，此IC芯片110，与现有例2同样地配置了第1输出端子112a、第2输出端子112b及输入端子112c，在第2输出端子112b和输入端子112c之间在宽度方向(较短方向)排列配置了逻辑电路部111和追加电路部114。另外，追加电路部114按实际使用制约的范围来配置。在追加电路部114近旁，根据实装上的问题，与第1输出端子112a及第2输出端子112b同样地在输出侧按2列配置了交错配置的加强用的假端子112d，并且与输入端子112c同样地在输入侧配置了追加端子112e。根据现有例3，与现有例2相比，在宽度方向(较短方向)能减小芯片尺寸，并且能增加输入端子数，多获取端子的面积，因而可降低接触电阻。
参照图13(现有例4)，此IC芯片110是专利文献1所披露的事例，是把内侧的第2输出端子112b做成横长的长方形的东西。第2输出端子112b保持连接强度及连接电阻等理由所涉及的给定的面积，一边保持第1输出端子112a们的宽度及间隙间距离一边缩短第2输出端子112b的纵宽度，从而扩大了IC芯片110内的可布置区域。
专利文献1：特开平11-183922号公报
发明内容
发明打算解决的课题
然而，按现有IC芯片那样的构成，因为实装芯片的面积变大，所以能削减部件数，但是面板进行多倒角的成本难以降低，这是其课题。还有，在具有假端子的IC芯片中，由于位于内侧的第2输出端子(图12的112b)，IC芯片内部的可布置区域变窄了。
详细地说明的话，通过进行COG实装，能减少部件数，不过，在玻璃基板上实装芯片的量的面积是必须有的，因而玻璃基板的来自多倒角的面的成本降低很难，这是其问题点。今后，在多个电路的1芯片化不断发展，伴随功能追加而进行电路元件的追加时，如现有例2(参照图11)、现有例4(参照图13)所示，成为在宽度方向(较短方向)的芯片尺寸变大的构成的话，用于实装的玻璃基板上的损失面积就会很大地扩大。对此，如现有例3(参照图12)所示，也可以考虑做成按实际使用制约的范围在较长侧配置追加电路部那样的构造，减少玻璃基板上的损失面积，不过，由于实装上的问题，需要大量地配置端子数。在增加了输入端子数的场合，具有通过端子数的分配来降低接触电阻等这样的好处，不过，输出端子因为各端子有偏差而行不通，所以要增加加强用的假端子。现有例3中在交错配置了输出端子112a、112b的场合，假端子112d也全部交错配置。在此场合，由于假端子112d中配置在内侧的端子而缩小了电路元件的可布置区域(参照图12)。结果，需要增大至追加电路部114以上的芯片尺寸，不能最有效地削减制造成本。
本发明的主要课题是提供一种即使为了保持压接时的平衡而设置了加强用的假端子，也能在芯片上设置更多的电路元件的半导体装置。
用于解决课题的方案
本发明的第1观点是一种半导体装置，其特征在于具备：在芯片的一端部的近旁按第1图形配置了的端子群；以及配置在与上述芯片的一端部的近旁，即配置了上述端子群的区域分开的区域，并且按与上述第1图形不同的第2图形配置了的假端子。
发明效果
根据本发明(权利要求1-10)，不变更芯片尺寸就能追加功能。还有，能使布置的自由度增加，能使能力、功能提高。即，能通过把假端子的排列变更为供给信号的端子的排列，使电路部的面积增加。
附图说明
图1是示意地表示本发明的实施方式1所涉及的半导体装置的构成的背面侧的平面图。
图2是示意地表示本发明的实施方式2所涉及的半导体装置的构成的背面侧的平面图。
图3是示意地表示本发明的实施方式3所涉及的半导体装置的构成的背面侧的平面图。
图4是示意地表示本发明的实施方式4所涉及的半导体装置的构成的背面侧的平面图。
图5是示意地表示本发明的实施方式5所涉及的半导体装置的构成的背面侧的平面图。
图6是示意地表示本发明的实施方式6所涉及的半导体装置的构成的背面侧的平面图。
图7是示意地表示本发明的实施方式7所涉及的半导体装置的构成的背面侧的平面图。
图8是示意地表示本发明的实施方式8所涉及的半导体装置的构成的背面侧的平面图。
图9是表示现有例1所涉及的半导体装置(IC芯片)的构成的概略图，(a)是背面侧的平面图，(b)是半导体装置的X-X′间的部分剖视图。
图10是表示在玻璃基板上按COG实装了现有例1所涉及的半导体装置(IC芯片)时的构成的概略图，(a)是平面图，(b)是Y-Y′间的部分剖视图。
图11是示意地表示现有例2所涉及的半导体装置(IC芯片)的构成的背面侧的平面图。
图12是示意地表示现有例3所涉及的半导体装置(IC芯片)的构成的背面侧的平面图。
图13是示意地表示现有例4所涉及的半导体装置(IC芯片)的构成的背面侧的平面图。
标号说明
10、110  半导体装置(IC芯片)
11、111  栅极驱动器部(逻辑电路部)
12a、112a  第1输出端子
12b、112b  第2输出端子
12c、112c  输入端子
12d、12h、12i、12j、112d  假端子
12e、112e  追加端子
12f、12g、112f  输出端子群
12k、112k  输入端子群
14、114  电源部(追加电路部)
112  端子
113  焊垫
120  各向异性导电膜
121  粘着剂
122  导电粒子
130  玻璃基板
131  端子
132  液晶画面部
具体实施方式
(实施方式1)
用附图来说明本发明的实施方式1所涉及的半导体装置。图1是示意地表示本发明的实施方式1所涉及的半导体装置的构成的背面侧的平面图。
作为半导体装置10，例如，可以列举液晶驱动用电源内置栅极驱动器IC芯片。半导体装置10在长度方向(较长方向)排列配置了栅极驱动器部11和电源部14。半导体装置10在背面侧即栅极驱动器部11的长度方向(较长方向)的一端部的近旁具有按2列交错配置的第1输出端子12a及第2输出端子12b，在背面侧即栅极驱动器部11的长度方向(较长方向)的另一端部的近旁具有按1列配置了的输入端子12c。半导体装置10在背面侧即电源部14的长度方向(较长方向)的一端部的近旁具有与第1输出端子12a同样地按1列配置了的加强用的假端子12d，在背面侧即电源部14的长度方向(较长方向)的另一端部的近旁具有与输入端子12c同样地按1列配置了的追加端子12e。在半导体装置10中，在电源部14的长度方向(较长方向)的一端部的近旁没有与第2输出端子12b同样的假端子，电源部14的布置区域扩大至第2输出端子12b的列的部位。
此处，假端子12d是主要以保持压接时的芯片的平衡为目的而配置的端子。此假端子12d与信号、电源通常所需要的端子相比，尺寸、形状可以不同。此假端子12d通常不与芯片上的电路元件、外部垫连接。但电源也可以经由假端子12d向芯片上的电路元件供给。
根据实施方式1，通过交错配置栅极驱动器部11的输出端子12a、12b，能缩窄在宽度方向(较短方向)的端子配置，所以能减小芯片面积。还有，能使与现有栅极驱动器部11的输出端子12a、12b同样地按2列交错配置了的假端子区域的一部分保持给定的面积来考虑端子尺寸，按1列配置假端子12d，从而能按此前交错配置的第2列的假端子区域的量来扩展可布置区域，减少了玻璃基板的面积损失。
还有，通过扩展布置区域，能进行功能的追加，例如，能在电源部中加大放大器等输出级晶体管的尺寸。结果就能设计不变更芯片尺寸而提高负载电流能力的IC。
再有，由于布置的自由度增加，存在还能实现功能的提高和芯片尺寸的缩小这样的一般是相反的事情的可能性。
(实施方式2)
用附图说明来本发明的实施方式2所涉及的半导体装置。图2是示意地表示本发明的实施方式2所涉及的半导体装置的构成的背面侧的平面图。实施方式2的半导体装置10是改善实施方式1后的方式，考虑到假端子12d保持给定的面积这样的条件，假端子12d与第1输出端子12a相比，做成了基板的宽度方向(较短方向)的宽度窄的形状。根据实施方式2，与实施方式1相比，端子间隔的数变少了，能减小基板的宽度方向(较短方向)的假端子尺寸，因而能进一步扩大芯片内的可布置区域。结果就可以提高电源部14的能力。
(实施方式3)
用附图说明来本发明的实施方式3所涉及的半导体装置。图3是示意地表示本发明的实施方式3所涉及的半导体装置的构成的背面侧的平面图。实施方式3的半导体装置10是改善实施方式2后的方式，考虑到假端子12d保持给定的面积这样的条件，把假端子12d做成在基板的长度方向(较长方向)长的形状的1个端子。根据实施方式3，具有与实施方式2同样的效果。
(实施方式4)
用附图说明来本发明的实施方式4所涉及的半导体装置。图4是示意地表示本发明的实施方式4所涉及的半导体装置的构成的背面侧的平面图。实施方式4半导体装置10按给定量保持假端子12d的面积，电源部14的布置区域也能配置在第1输出端子12a的列的部位。根据实施方式4，在进行布置设计时，能确保最有效性的区域，可以提高电源部的能力。
(实施方式5～7)
用附图说明来本发明的实施方式5～7所涉及的半导体装置。图5～7是示意地表示本发明的实施方式5～7所涉及的半导体装置的构成的背面侧的平面图。
实施方式5所涉及的半导体装置10，尽管是电源内置栅极驱动器IC，但有效地布置设计了电路元件部，从而做成了在基板的长度方向(较长方向)排列了由输出端子12a、12b组成的输出端子群12f和假端子12d的构成(参照图5)。
实施方式6所涉及的半导体装置10，尽管是电源内置栅极驱动器IC，但有效地布置设计了电路元件部，从而做成了在由输出端子12a、12b组成的输出端子群12f和假端子12g之间配置了假端子12d的构成(参照图6)。
实施方式7所涉及的半导体装置10，尽管是电源内置栅极驱动器IC，但有效地布置设计了电路元件部，从而做成了在假端子12d和假端子12h之间配置了由输出端子12a、12b组成的输出端子群12f的构成(参照图7)。
根据实施方式5～7，把靠2列交错配置而有效地布置设计的部分(输出端子群)和靠1列直线配置而有效地布置设计的部分(假端子区域)组合起来，就能不加大芯片尺寸地设计具有各种能力、功能的IC。
(实施方式8)
用附图说明来本发明的实施方式8所涉及的半导体装置。图8是示意地表示本发明的实施方式8所涉及的半导体装置的构成的背面侧的平面图。实施方式8所涉及的半导体装置10还与输出端子群12f侧同样地在输入端子群12k侧，在输入端子群12k的两边配置了假端子12i、12j。根据实施方式8，对于输入端子群12k侧，也做成把芯片平衡、面积考虑在内的形状，从而能进一步扩张功能。

Claims (10)

1.一种半导体装置，其特征在于具备：
在芯片的一端部的近旁按第1图形配置了的端子群；以及
配置在与所述芯片的一端部的近旁，即配置了所述端子群的区域分开的区域，并且按与所述第1图形不同的第2图形配置了的假端子。
2.根据权利要求1所述的半导体装置，其特征在于，所述第2图形构成为，宽度比所述第1图形窄。
3.根据权利要求1所述的半导体装置，其特征在于，在所述假端子的近旁，在所述端子群的长度方向旁边配置了电路元件部。
4.根据权利要求1所述的半导体装置，其特征在于，所述假端子配置在所述端子群的长度方向的一边。
5.根据权利要求1所述的半导体装置，其特征在于，所述假端子配置在所述端子群中的第1端子群和第2端子群之间。
6.根据权利要求1所述的半导体装置，其特征在于，所述假端子配置在所述端子群的长度方向两边。
7.根据权利要求1所述的半导体装置，其特征在于，在所述假端子和所述端子群之间配置了电路元件部。
8.根据权利要求1所述的半导体装置，其特征在于，所述端子群是交错配置的。
9.根据权利要求1所述的半导体装置，其特征在于，所述端子群被分配给输出端子群和输入端子群中的一方或两方。
10.根据权利要求1所述的半导体装置，其特征在于，用于COG实装。
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Free format text: FORMER NAME: NEC CORP.

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Address after: Kanagawa, Japan

Patentee after: Renesas Electronics Corporation

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Granted publication date: 20090527

Termination date: 20131030