CN104704621A - 驱动芯片和显示装置 - Google Patents
驱动芯片和显示装置 Download PDFInfo
- Publication number
- CN104704621A CN104704621A CN201380052057.XA CN201380052057A CN104704621A CN 104704621 A CN104704621 A CN 104704621A CN 201380052057 A CN201380052057 A CN 201380052057A CN 104704621 A CN104704621 A CN 104704621A
- Authority
- CN
- China
- Prior art keywords
- driving chip
- mentioned
- terminal
- space portion
- liquid crystal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1345—Conductors connecting electrodes to cell terminals
- G02F1/13452—Conductors connecting driver circuitry and terminals of panels
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0612—Layout
- H01L2224/0613—Square or rectangular array
- H01L2224/06131—Square or rectangular array being uniform, i.e. having a uniform pitch across the array
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0612—Layout
- H01L2224/0613—Square or rectangular array
- H01L2224/06133—Square or rectangular array with a staggered arrangement, e.g. depopulated array
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0612—Layout
- H01L2224/0613—Square or rectangular array
- H01L2224/06134—Square or rectangular array covering only portions of the surface to be connected
- H01L2224/06135—Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0612—Layout
- H01L2224/06177—Combinations of arrays with different layouts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
- H01L2224/1401—Structure
- H01L2224/1403—Bump connectors having different sizes, e.g. different diameters, heights or widths
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
- H01L2224/141—Disposition
- H01L2224/1412—Layout
- H01L2224/1413—Square or rectangular array
- H01L2224/14131—Square or rectangular array being uniform, i.e. having a uniform pitch across the array
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
- H01L2224/141—Disposition
- H01L2224/1412—Layout
- H01L2224/1413—Square or rectangular array
- H01L2224/14133—Square or rectangular array with a staggered arrangement, e.g. depopulated array
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
- H01L2224/141—Disposition
- H01L2224/1412—Layout
- H01L2224/1413—Square or rectangular array
- H01L2224/14134—Square or rectangular array covering only portions of the surface to be connected
- H01L2224/14135—Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
- H01L2224/141—Disposition
- H01L2224/1412—Layout
- H01L2224/14177—Combinations of arrays with different layouts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
- H01L2224/1451—Function
- H01L2224/14515—Bump connectors having different functions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/29199—Material of the matrix
- H01L2224/2929—Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/29298—Fillers
- H01L2224/29299—Base material
- H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8112—Aligning
- H01L2224/81136—Aligning involving guiding structures, e.g. spacers or supporting members
- H01L2224/81138—Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
- H01L2224/81139—Guiding structures on the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/812—Applying energy for connecting
- H01L2224/81201—Compression bonding
- H01L2224/81203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/8185—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8312—Aligning
- H01L2224/83136—Aligning involving guiding structures, e.g. spacers or supporting members
- H01L2224/83138—Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
- H01L2224/83139—Guiding structures on the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/832—Applying energy for connecting
- H01L2224/83201—Compression bonding
- H01L2224/83203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
- H01L2224/83851—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester being an anisotropic conductive adhesive
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12041—LED
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/38—Effects and problems related to the device integration
- H01L2924/381—Pitch distance
Landscapes
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Crystallography & Structural Chemistry (AREA)
- Optics & Photonics (AREA)
- Chemical & Material Sciences (AREA)
- Mathematical Physics (AREA)
- Geometry (AREA)
- Liquid Crystal (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
一种驱动芯片,具备:基底主体;沿着基底主体的长边方向的相对的边分别配设的2组端子组;在呈交错状配置2列以上的一方端子组中,长边方向的端子的间距窄的窄间距部;长边方向的端子的间距比窄间距部宽的宽间距部;以及在2组端子组之间与宽间距部并列设置的焊盘。
Description
技术领域
本发明涉及驱动芯片和具备该驱动芯片的显示装置。
背景技术
一直以来,便携信息终端等中小型的显示装置使用液晶显示装置。在液晶显示装置中搭载有用于驱动液晶面板的驱动芯片,为了与液晶显示装置的薄型化对应,使用将驱动芯片直接安装于液晶面板上的COG(玻璃上芯片)方式。在COG方式中,通常在驱动芯片与液晶面板之间夹着ACF(各向异性导电膜),以高温压接,由此将驱动芯片与液晶面板电连接。
并且,近年来,要求液晶显示装置进一步薄型化,驱动芯片也被要求薄型化。但是,当减薄驱动芯片时,产生由于压接时的热使驱动芯片挠曲的问题。由此,有可能发生驱动芯片和液晶面板的电连接不良。
在专利文献1中公开了一种驱动芯片,该驱动芯片包含:基底主体,其包含一个面,该一个面具有与长边平行的第1端部和第2端部以及与长边垂直且与短边平行的第3端部和第4端部;多个输入端子,其沿着基底主体的长边形成于第1端部;多个第1输出端子,其沿着长边排列于第2端部;以及虚设端子,其形成于输入端子与第1输出端子之间,虚设端子沿着长边形成1列以上。
现有技术文献
专利文献
专利文献1:特开2005-203758号公报
发明内容
发明要解决的问题
但是,在专利文献1中,在驱动芯片的长边方向将虚设端子排列一列以上,所以当要确保电路区域时,必须增大驱动芯片的尺寸,难以确保电路区域。
本发明的目的在于提供确保电路区域并且通过抑制翘曲来防止接触不良的驱动芯片。另外,目的还在于提供搭载有该驱动芯片的显示装置。
用于解决问题的方案
为了达成上述目的,本发明设为如下驱动芯片,其具备:基底主体;沿着上述基底主体的长边方向的相对的边分别配设的2组端子组;在呈交错状配置2列以上的一方上述端子组中,长边方向的端子的间距窄的窄间距部;长边方向的端子的间距比该窄间距部宽的宽间距部;以及在上述2组端子组之间与上述宽间距部并列设置的焊盘。
发明效果
根据本发明,通过在驱动芯片中设置虚设焊盘,可抑制由于COG工艺中的压接时的热导致的驱动芯片的挠曲。其结果是,可维持驱动芯片和液晶面板平行,可防止驱动芯片和液晶面板的电连接不良。另外,通过将虚设焊盘与电路没有混合的宽间距部并列设置,即使不增大驱动芯片的尺寸也能充分确保电路区域。
附图说明
图1是表示本发明的一实施方式的液晶显示装置的分解立体图。
图2是本发明的第1实施方式的驱动芯片的俯视图。
图3是搭载有第1实施方式的驱动芯片的液晶显示装置中的驱动芯片的短边方向的截面图。
图4是搭载有比较例的驱动芯片的液晶显示装置中的驱动芯片的短边方向的截面图。
图5是本发明的第2实施方式的驱动芯片的俯视图。
图6是本发明的第2实施方式的其它驱动芯片的俯视图。
图7是本发明的第3实施方式的驱动芯片的俯视图。
具体实施方式
以下参照附图说明本发明的实施方式。
图1是表示本发明的一实施方式的液晶显示装置的分解立体图。在图1中,液晶显示装置10在以显示面向上的方式水平放置的状态下被绘制。
该液晶显示装置10能用作电视、计算机的显示器。液晶显示装置10具备背光源底座11、光源单元12、导光板13、光学片14、面板框架15、搭载有驱动芯片20的液晶面板16、以及外框17。并且,将组装背光源底座11、光源单元12、12、导光板13以及光学片14而成的结构称为背光源装置18。
背光源底座11是用于搭载(收纳)光源单元12、导光板13、光学片14等背光源装置18的各构件的成为基座的构件,为箱形。背光源底座11的材料为了确保刚性和散热性,期望使用SECC(钢板)、Al等。
光源单元12包含作为点状光源的LED(Light Emitting Diode:发光二极管)和搭载LED的LED基板。此外,作为光源,除了LED之外,也可以使用作为线状光源的荧光管等。并且,在LED基板上沿着导光板13的一边以规定间隔配设有多个LED。光源单元12的配置采用边光方式。在大型的液晶显示装置中,作为LED基板,考虑到散热性、强度,多数使用Al等金属基板。
另外,作为将光源单元12固定于背光源底座11的固定单元,能使用螺钉、粘接剂。另外,在图1中,2个光源单元12、12分别沿着导光板13的相对的侧面设置,但是也可以设为仅沿着导光板13的一侧面设置光源单元12的构成,并且还可以设为也沿着导光板13的其它侧面设置的构成。即,光源单元12只要设为沿着导光板13的侧面的至少一个设置的构成即可。在此,侧面与LED相对,成为将来自LED的光向导光板13内引导的光入射部(光入射面)。
导光板13具有一对主面(上表面和下表面)和形成于它们之间的多个侧面(在图1中为4面)。导光板13是将从其端面(侧面)入射的LED的光向面光源转换并从上表面导出的构件,作为其材料,从薄型化、轻量化的观点出发,期望使用丙烯酸、PC(聚碳酸酯)等树脂。
光学片14是扩散片、透镜片、增亮片等的总称,是这些片中的任一片或者将多片组合而成的。光学片14重叠在导光板13上,用于向液晶面板16照射均匀的光,所以当片有褶皱、挠曲时,成为显示质量劣化的原因。
面板框架15是以液晶面板16和光学片14不接触的方式保持液晶面板16的边框状的构件,作为其材料,期望使用PC等树脂。另外,面板框架15也有抑制光学片14的翘曲、挠曲的作用。
液晶面板16是在2片透明基板之间注入液晶元件而成的构件,通过控制驱动芯片20来驱动液晶元件,利用背光源装置18对液晶元件进行照明,由此显示视频。
驱动芯片20具备基底主体、多个输入端子以及多个输出端子,以COG方式搭载于液晶面板16。并且,驱动芯片20将从外部输入的图像数据转换为适合液晶面板16的驱动的驱动信号,在最佳的定时向液晶面板施加。
外框17是边框状的按压并固定液晶面板16的构件,以形成盖的方式覆盖于箱形的背光源底座11。作为其材料,除了SECC、Al等之外,为了轻量化,也可以使用PC、ABS树脂、CFRP((carbon fiberreinforced plastics)碳纤维强化塑料)等。为了进一步的轻量化,也可以使用这些材料使成为外壳的箱体(未图示)和外框17一体成型。
以下对这种液晶显示装置10中的作为本发明的特征构成的驱动芯片20的实施方式详细地说明。
<第1实施方式>
图2是本发明的第1实施方式的驱动芯片的俯视图。作为上述的驱动芯片20的一实施方式的第1实施方式的驱动芯片201具有基底主体202、输入端子组203、输出端子组204、虚设焊盘205。
基底主体202是配设端子组的面为矩形的绝缘件,例如,厚度为0.2mm以下,短边方向的长度为1.5mm以上。在基底主体202的内部具备半导体元件(未图示),该半导体元件用于将从外部输入的图像信号转换为驱动所需的驱动信号。
输入端子组203和输出端子组204是沿着基底主体202的长边方向的相对的边分别配设的2组端子组。输入端子组203是矩形的各端子203a以等间隔呈直线状排列成1列而形成的。此外,输入端子组203也可以是2列以上。
输出端子组204是比输入端子小的矩形的各端子204a呈交错状配置2列而形成的。在输出端子组204的长边方向的中央附近,为了确保电路区域,端子204a所配置的长边方向的间距比周围(后述的窄间距部204b、204c)宽,将该部分称为宽间距部204c。另一方面,宽间距部204c的两侧也可以不确保电路区域,因此端子204a以比宽间距部204c窄的间距密集地配置,将该部分称为窄间距部204b、204d。此外,输出端子组204也可以为3列以上。
此外,输入端子组203和输出端子组204也可以调换配置形状,将输入端子组203设为交错状,将输出端子组设为直线状。另外,两端子组203、204均可以设为交错状或者2列以上的直线状。
虚设焊盘205是没有电连接的虚设的焊盘。虚设焊盘205配置于基底主体202的大致中央。即,虚设焊盘205在输入端子组203与输出端子组204之间与宽间距部204c并列设置。虚设焊盘205的高度(厚度)与输入端子组203以及输出端子组204的高度(厚度)相等。并且,虚设焊盘205具有比各端子203a、204a大的面积。此外,也可以取代虚设焊盘205而设为电连接的功能焊盘。
图3是搭载有第1实施方式的驱动芯片201的液晶显示装置中的驱动芯片201的短边方向的截面图。使用形成有导电线30的液晶面板16在驱动芯片201与液晶面板16之间夹着ACF(各向异性导电膜)31,利用COG工艺以高温压接,由此将两端子组203、204和导电线30电连接。在图3中,使用ACF31所含的多个导电粒子示意性地图示出ACF31。虚设焊盘205隔着ACF31压接于液晶面板16。
图4是搭载有比较例的驱动芯片的液晶显示装置中的驱动芯片的短边方向的截面图。比较例的驱动芯片100是从第1实施方式的驱动芯片201省去虚设焊盘205的构成。
如上所述,基底主体的厚度薄至0.2mm以下,基底主体的短边方向的长度长至1.5mm以上,因此,成为由于COG工艺中的压接时的热使驱动芯片100在短边方向挠曲、液晶面板16向反方向挠曲而反翘的状态。其结果是,特别是在输出端子组204的外列的端子204a中,与液晶面板16的间隙变大,ACF31中的导电粒子不能成为充分扁平的粒子,发生驱动芯片100和液晶面板16的电连接不良。
与此相对,在搭载有第1实施方式的驱动芯片201的液晶显示装置中,通过设置虚设焊盘205,可抑制由于COG工艺中的压接时的热导致的驱动芯片201的挠曲。其结果是,可维持驱动芯片201和液晶面板16平行(参照图3),在与全部端子203a、204a接触的ACF31中,导电粒子能成为充分扁平的粒子,可防止驱动芯片201和液晶面板16的电连接不良。
另外,在第1实施方式的驱动芯片201中,虚设焊盘205与电路没有混合的宽间距部204c并列设置,所以即使不增大驱动芯片201的尺寸也能充分确保电路区域。
<第2实施方式>
图5是本发明的第2实施方式的驱动芯片的俯视图。作为上述的驱动芯片20的一实施方式的第2实施方式的驱动芯片206配设有2个第1实施方式的虚设焊盘205。除此之外,对与第1实施方式同样的构成标注相同附图标记,省略其详细的说明。
如图5所示,2个虚设焊盘205在基底主体202的大致中央沿着长边方向排列。即,2个虚设焊盘205在输入端子组203与输出端子组204之间与宽间距部204c并列设置。
图6是本发明的第2实施方式的其它驱动芯片的俯视图。作为上述的驱动芯片20的一实施方式的第2实施方式的驱动芯片207配设有3个第1实施方式的虚设焊盘205。如图6所示,3个虚设焊盘205在基底主体202的大致中央沿着长边方向排列。即,3个虚设焊盘205在输入端子组203与输出端子组204之间与宽间距部204c并列设置。
此外,在第2实施方式中,虚设焊盘205也可以配设4个以上。这样,第2实施方式的驱动芯片配设有多个虚设焊盘205,能确保电路区域并且能更可靠地防止驱动芯片和液晶面板16的电连接不良。此外,与第1实施方式同样,也可以取代虚设焊盘205而设为功能焊盘。
<第3实施方式>
图7是本发明的第3实施方式的驱动芯片的俯视图。作为上述的驱动芯片20的一实施方式的第3实施方式的驱动芯片208是在第1实施方式中将宽间距部204c配置于输出端子组204的长边方向端部而成的。除此之外,对与第1实施方式同样的构成标注相同附图标记,省略其详细的说明。
如图7所示,虚设焊盘205配设于基底主体202的长边方向端部附近。即,虚设焊盘205在输入端子组203与输出端子组204之间与宽间距部204c并列设置。
这样,即使在宽间距部204c位于基底主体202的端部附近的情况下也将虚设焊盘205与宽间距部204c并列设置,由此能确保电路区域并且能防止驱动芯片和液晶面板16的电连接不良。此外,与第1实施方式同样,也可以取代虚设焊盘205而设为功能焊盘。另外,在第3实施方式中,也可以如第2实施方式那样配设多个虚设焊盘205。
工业上的可利用性
本发明的驱动芯片能利用于以液晶显示装置为首的显示装置,特别是能适当利用于便携信息终端等中小型的液晶显示装置。
附图标记说明
10 液晶显示装置
11 背光源底座
12 光源单元
13、21、31、41 导光板
14 光学片
15 面板框架
16 液晶面板
17 外框
18 背光源装置
30 导电线
31 ACF
201、206~208 驱动芯片
202 基底主体
203 输入端子
203a、204a 端子
204 输出端子
204b、204d 窄间距部
204c 宽间距部
205 虚设焊盘
Claims (10)
1.一种驱动芯片,其具备:
基底主体;
沿着上述基底主体的长边方向的相对的边分别配设的2组端子组;
在呈交错状配置2列以上的一方上述端子组中,长边方向的端子的间距窄的窄间距部;长边方向的端子的间距比该窄间距部宽的宽间距部;以及
在上述2组端子组之间与上述宽间距部并列设置的焊盘。
2.根据权利要求1所述的驱动芯片,其特征在于,上述焊盘配设有多个。
3.根据权利要求1或2所述的驱动芯片,其特征在于,上述宽间距部位于上述一方端子组的中央。
4.根据权利要求1或2所述的驱动芯片,其特征在于,上述宽间距部位于上述一方端子组的端部。
5.根据权利要求1~4中的任一项所述的驱动芯片,其特征在于,具有上述宽间距部的端子组是输出端子组。
6.根据权利要求1~5中的任一项所述的驱动芯片,其特征在于,上述焊盘是没有电连接的虚设焊盘。
7.根据权利要求1~5中的任一项所述的驱动芯片,其特征在于,上述焊盘是电连接的功能焊盘。
8.根据权利要求1~7中的任一项所述的驱动芯片,其特征在于,上述2组端子组和上述焊盘的高度相等。
9.根据权利要求1~8中的任一项所述的驱动芯片,其特征在于,上述焊盘具有比上述2组端子组的各端子大的面积。
10.一种显示装置,其以玻璃上芯片方式搭载有权利要求1~9中的任一项所述的驱动芯片。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2012225663 | 2012-10-11 | ||
JP2012-225663 | 2012-10-11 | ||
PCT/JP2013/077238 WO2014057908A1 (ja) | 2012-10-11 | 2013-10-07 | 駆動チップ及び表示装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN104704621A true CN104704621A (zh) | 2015-06-10 |
CN104704621B CN104704621B (zh) | 2017-08-25 |
Family
ID=50477375
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201380052057.XA Active CN104704621B (zh) | 2012-10-11 | 2013-10-07 | 驱动芯片和显示装置 |
Country Status (3)
Country | Link |
---|---|
US (1) | US9318454B2 (zh) |
CN (1) | CN104704621B (zh) |
WO (1) | WO2014057908A1 (zh) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN107068079A (zh) * | 2016-02-10 | 2017-08-18 | 辛纳普蒂克斯日本合同会社 | 显示驱动器以及显示面板模块 |
WO2020043170A1 (en) * | 2018-08-31 | 2020-03-05 | Changxin Memory Technologies, Inc. | Arrangement of bond pads on an integrated circuit chip |
CN111009501A (zh) * | 2019-08-27 | 2020-04-14 | 武汉华星光电半导体显示技术有限公司 | 芯片绑定结构 |
CN113823241A (zh) * | 2021-09-30 | 2021-12-21 | 武汉华星光电技术有限公司 | 驱动芯片及显示面板 |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2015182496A1 (ja) * | 2014-05-30 | 2015-12-03 | シャープ株式会社 | 実装基板、実装基板の製造方法、及び実装基板の製造装置 |
JP2016029698A (ja) * | 2014-07-22 | 2016-03-03 | デクセリアルズ株式会社 | 接続体、及び接続体の製造方法 |
KR102287754B1 (ko) * | 2014-08-22 | 2021-08-09 | 삼성전자주식회사 | 칩 적층 반도체 패키지 |
KR102251231B1 (ko) | 2014-09-16 | 2021-05-12 | 엘지디스플레이 주식회사 | 구동 칩 패키지 및 이를 포함하는 표시장치 |
KR102325643B1 (ko) * | 2015-01-07 | 2021-11-12 | 삼성디스플레이 주식회사 | 표시 장치 |
JP2016134450A (ja) * | 2015-01-16 | 2016-07-25 | デクセリアルズ株式会社 | 接続構造体 |
US20190041685A1 (en) * | 2016-02-10 | 2019-02-07 | Sharp Kabushiki Kaisha | Semiconductor device and display device |
DE102019121371B4 (de) * | 2018-08-08 | 2022-10-06 | Lg Display Co., Ltd. | Integrierte-Schaltung-Baugruppe und diese verwendende Anzeigevorrichtung |
KR20210065580A (ko) * | 2019-11-27 | 2021-06-04 | 엘지디스플레이 주식회사 | 플렉서블 표시장치 |
US11721551B2 (en) * | 2021-01-26 | 2023-08-08 | Tokyo Electron Limited | Localized stress regions for three-dimension chiplet formation |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003263117A (ja) * | 2002-03-08 | 2003-09-19 | Hitachi Ltd | 表示装置 |
US20040169291A1 (en) * | 2001-08-06 | 2004-09-02 | Wen-Chih Yang | [bump layout on silicon chip] |
CN1629926A (zh) * | 2003-12-16 | 2005-06-22 | 三星电子株式会社 | 驱动芯片及具有该驱动芯片的显示装置 |
CN1959970A (zh) * | 2005-10-31 | 2007-05-09 | 恩益禧电子股份有限公司 | 半导体装置 |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI292836B (zh) * | 2001-10-31 | 2008-01-21 | Chi Mei Optoelectronics Corp | |
US6750552B1 (en) * | 2002-12-18 | 2004-06-15 | Netlogic Microsystems, Inc. | Integrated circuit package with solder bumps |
JP4067502B2 (ja) * | 2004-03-11 | 2008-03-26 | シャープ株式会社 | 半導体装置、半導体装置の実装構造およびそれを備える電子機器ならびに表示装置 |
JP4400623B2 (ja) * | 2007-01-24 | 2010-01-20 | エプソンイメージングデバイス株式会社 | 実装構造体、電気光学装置及び電子機器 |
-
2013
- 2013-10-07 WO PCT/JP2013/077238 patent/WO2014057908A1/ja active Application Filing
- 2013-10-07 US US14/433,711 patent/US9318454B2/en active Active
- 2013-10-07 CN CN201380052057.XA patent/CN104704621B/zh active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20040169291A1 (en) * | 2001-08-06 | 2004-09-02 | Wen-Chih Yang | [bump layout on silicon chip] |
JP2003263117A (ja) * | 2002-03-08 | 2003-09-19 | Hitachi Ltd | 表示装置 |
CN1629926A (zh) * | 2003-12-16 | 2005-06-22 | 三星电子株式会社 | 驱动芯片及具有该驱动芯片的显示装置 |
CN1959970A (zh) * | 2005-10-31 | 2007-05-09 | 恩益禧电子股份有限公司 | 半导体装置 |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN107068079A (zh) * | 2016-02-10 | 2017-08-18 | 辛纳普蒂克斯日本合同会社 | 显示驱动器以及显示面板模块 |
CN107068079B (zh) * | 2016-02-10 | 2022-06-24 | 辛纳普蒂克斯日本合同会社 | 显示驱动器以及显示面板模块 |
WO2020043170A1 (en) * | 2018-08-31 | 2020-03-05 | Changxin Memory Technologies, Inc. | Arrangement of bond pads on an integrated circuit chip |
US11450635B2 (en) | 2018-08-31 | 2022-09-20 | Changxin Memory Technologies, Inc. | Arrangement of bond pads on an integrated circuit chip |
CN111009501A (zh) * | 2019-08-27 | 2020-04-14 | 武汉华星光电半导体显示技术有限公司 | 芯片绑定结构 |
CN113823241A (zh) * | 2021-09-30 | 2021-12-21 | 武汉华星光电技术有限公司 | 驱动芯片及显示面板 |
WO2023050494A1 (zh) * | 2021-09-30 | 2023-04-06 | 武汉华星光电技术有限公司 | 驱动芯片及显示面板 |
Also Published As
Publication number | Publication date |
---|---|
CN104704621B (zh) | 2017-08-25 |
US20150279792A1 (en) | 2015-10-01 |
WO2014057908A1 (ja) | 2014-04-17 |
US9318454B2 (en) | 2016-04-19 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN104704621A (zh) | 驱动芯片和显示装置 | |
CN102141701B (zh) | 液晶显示设备 | |
JP4782410B2 (ja) | 駆動チップ及びこれを有する表示装置 | |
CN104412315B (zh) | 显示装置 | |
CN104487759B (zh) | 照明装置、显示装置以及电视接收装置 | |
JP2008096950A (ja) | バックライトアセンブリ及びこれを備える液晶表示装置 | |
CN104471305A (zh) | 照明装置、显示装置以及电视接收装置 | |
US9335012B2 (en) | Light bar structure and light source device | |
KR20150025728A (ko) | 발광다이오드어셈블리 및 그를 포함한 액정표시장치 | |
US11126035B1 (en) | Backlight module and liquid crystal display device | |
CN102958308A (zh) | 显示设备 | |
CN102193227A (zh) | 液晶模块和电子设备 | |
CN105549265A (zh) | 一种背光模组及液晶显示器 | |
CN110989230B (zh) | 显示装置及电子设备 | |
CN1913746B (zh) | 印刷电路板及具有其的液晶显示器 | |
TW200523610A (en) | Driver chip and display apparatus including the same | |
US8794778B2 (en) | Top chassis assembly and display device having the same | |
CN104040413B (zh) | 显示装置和电视接收装置 | |
CN104285093A (zh) | 显示装置和电视接收装置 | |
CN106125385B (zh) | 一种改善基板内缩变形的方法 | |
CN111596487A (zh) | 一种led背光显示面板及其制备方法 | |
CN106908998B (zh) | 背光模组及显示装置 | |
US20160018691A1 (en) | Display apparatus and television receiving apparatus | |
CN216083334U (zh) | 一种背光模组及液晶显示装置 | |
WO1999014630A1 (fr) | Ecran a cristaux liquides |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant |