CN111009501A - 芯片绑定结构 - Google Patents

芯片绑定结构 Download PDF

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CN111009501A
CN111009501A CN201910798072.8A CN201910798072A CN111009501A CN 111009501 A CN111009501 A CN 111009501A CN 201910798072 A CN201910798072 A CN 201910798072A CN 111009501 A CN111009501 A CN 111009501A
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张定伟
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Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
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    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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    • H01L23/00—Details of semiconductor or other solid state devices
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/1451—Function
    • H01L2224/14515—Bump connectors having different functions
    • H01L2224/14517—Bump connectors having different functions including bump connectors providing primarily mechanical bonding
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/171—Disposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/1751—Function
    • H01L2224/17515—Bump connectors having different functions
    • H01L2224/17517—Bump connectors having different functions including bump connectors providing primarily mechanical support

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Abstract

本发明提供一种芯片绑定结构，包括载体和芯片；所述载体和所述芯片上均设置有信号端子；所述信号端子分为输出信号端子和输入信号端子；在所述载体或所述芯片至少一者上设置有虚设端子。在本发明中，为改善普遍存在的IC绑定不良，从IC内部结构设计进行改善，通过增加虚设凸块来提升压痕的稳定性，减少在绑定过程中IC发生形变、凹陷及翘起，并改善绑定不良。

Description

芯片绑定结构
技术领域
本发明涉及显示技术领域，尤其涉及一种芯片绑定结构。
背景技术
显示面板，如有机发光二极管(Organic Light-Emitting Diode，简称：OLED)因其在固态照明和平板显示的方向拥有巨大的发展潜力而得到了学术界和产业界的极大关注。有机发光二极管(OLED)平板可以做的更轻更薄，因而柔性显示技术将是未来的发展趋势。目前，背板工艺有两种方式。第一种方式是：在面板贴膜之后玻璃切割，再在玻璃上电路绑定(Bonding)，再将玻璃取下以及在柔性基板背面贴膜及功能膜的工艺；第二种方式是：在面板贴膜之后，先将大面积的玻璃取下以及并对柔性基板背面贴膜，再切割并在切割之后在柔性基板上进行电路绑定，然后贴附背面功能膜。两种开发方向的不同之处之一是绑定工艺是在玻璃上还是在柔性塑料基板上。
在OLED和LCD的模组工艺中，Bonding为重要的工艺。而在小尺寸Bonding，ICBonding(俗称COG或COP工艺)为核心工艺之一。
IC的绑定面，一般称之为凸块区，因布线需求，整体IC的宽度也随之增加，最大超过2mm，而输入凸块与输出凸块间距会达到1mm左右。在此种情况下，IC Bonding时，因为受压巨大(一般超过50Mpa)，中间区域因为无凸块支撑悬空会发生凹陷问题，中间凹陷会导致两端翘起，中间也会反弹硬力发生浮起，最终造成Bonding压痕不良ACF导电粒子浅，IC凸块与显示面板凸块间隙过大，发生断路。
针对以上的种种不足，以及趋势看，随着屏幕分辨率越来越高，IC本身宽度会越来越宽，输出凸块与输入凸块间距越来越大，故此凹陷风险会大大增加。
发明内容
本发明提供一种芯片绑定结构，可在输入信号端子与输出信号端子之间增设虚设端子，来支撑IC芯片的信号端子，避免中间受力凹陷，以解决在IC绑定时，因为受压巨大，中间区域支撑悬空会发生凹陷，中间凹陷会导致两端翘起，中间也会反弹硬力发生浮起，最终造成绑定压痕不良的问题。
为解决上述问题，本发明提供的技术方案如下：
本发明提供一种芯片绑定结构，所述芯片绑定结构包括载体和芯片；
所述载体和所述芯片上均设置有信号端子，所述载体上的所述信号端子和所述芯片上的所述信号端子电性绑定；所述信号端子分为输出信号端子和输入信号端子；
其中，在所述载体或所述芯片至少一者上设置有虚设端子，所述虚设端子设置在所述载体或所述芯片没有所述信号端子的部位上。
根据本发明实施例所提供的芯片绑定结构，所述载体为显示面板，所述芯片为IC芯片。
根据本发明实施例所提供的芯片绑定结构，所述输出信号端子至少有3排。
根据本发明实施例所提供的芯片绑定结构，所述输入信号端子与所述输出信号端子之间的间距至少大于500微米。
根据本发明实施例所提供的芯片绑定结构，所述虚设端子位于所述输入信号端子与所述输出信号端子中间。
根据本发明实施例所提供的芯片绑定结构，所述虚设端子至少存在一排。
根据本发明实施例所提供的芯片绑定结构，所述虚设端子大小与所述输入信号端子相同。
根据本发明实施例所提供的芯片绑定结构，所述虚设端子高度与所述输入信号端子相同。
根据本发明实施例所提供的芯片绑定结构，所述虚设端子支撑所述载体与所述芯片。
根据本发明实施例所提供的芯片绑定结构，在所述载体的对应位置设置有相应的虚设端子。
本发明的有益效果为：在本发明中，为改善普遍存在的IC芯片绑定不良，从IC芯片内部结构设计进行改善，通过增加虚设端子来提升压痕的稳定性，减少在绑定过程中IC芯片发生形变、凹陷及翘起，并改善绑定不良。
附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本实施例所提供的IC芯片绑定示意图。
图2为本实施例所提供的IC芯片中间增加虚设端子示意图。
图3为本实施例所提供的IC芯片中间增加虚设端子痕示意图。
具体实施方式
以下各实施例的说明是参考附加的图示，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。在图中，结构相似的单元是用以相同标号表示。
下文中的IC芯片端子是指IC芯片上与外界电路(例如，柔性基板的金属引线)的线路引脚。
本发明实施例提供了一种芯片绑定结构，所述芯片绑定结构包括载体和芯片；
所述载体和所述芯片上均设置有信号端子，所述载体上的所述信号端子和所述芯片上的所述信号端子电性绑定；所述信号端子分为输出信号端子和输入信号端子；
其中，在所述载体或所述芯片至少一者上设置有虚设端子，所述虚设端子设置在所述载体或所述芯片没有所述信号端子的部位上。
在本实施例中，所述载体以显示面板为例，所述芯片为IC芯片为例，来说明本发明提案。
如图1所示，在IC芯片的绑定示意图中，显示面板30放置平台10以及背板平台20上，IC芯片40放置在所述显示面板30的绑定连接处。其中，所述IC芯片40通过热压合机50与所述显示面板30绑定在一起。
如图2所示，为本实施例所提供的IC芯片中间增加虚设端子2示意图。所述IC芯片的信号端子区设置有输入信号端子3，输出信号端子1，以及虚设端子2，所述虚设端子2主要用于在所述IC芯片与所述显示面板热压合时，对所述IC芯片起到支撑的作用，避免所述IC芯片中间受力凹陷。
所述输出信号端子1在所述IC芯片的信号端子区至少有3排，本实施例以3排输出信号端子为例说明。所述输入信号端子3在所述IC芯片的信号端子区有1排，而所述输入信号端子3与所述输出信号端子1之间的间距至少大于500微米，本发明实施例在所述输入信号端子3与所述输出信号端子1的间距大于500微米时，效果较优。若所述输入信号端子3与所述输出信号端子1之间的间距较小，则不必要设置所述虚设端子2。
其中，所述虚设端子2位于所述输入信号端子3与所述输出信号端子1的中间位置。所述虚设端子2至少存在一排，若所述输入信号端子3与所述输出信号端子1之间的间距较大，则可视情况增加所述虚设端子2的排数。所述虚设端子2大小与所述输入端子3相同，所述虚设端子2高度与所述输入信号端子3相同，所述虚设端子2的间距可以根据实际情况而调整例如以2到3个所述输出信号端子1设计一个所述虚设端子2。所述虚设端子2无功能特性，在IC芯片绑定中只作为支撑结构，主要起到支撑所述显示面板与所述IC芯片的作用。
如图3所示，在所述IC芯片与所述显示面板绑定热压合时，为了避免中间受力凹陷，在实际操作中，在所述显示面板30上蚀刻与所述IC芯片40的所述虚设端子2相对应的虚设端子2，相互配合。
有益效果为：本发明实施例通过对绑定所用的IC芯片增加虚设端子来改善绑定不良的目的。在本发明中，为改善普遍存在的IC芯片绑定不良，从IC芯片内部结构设计进行改善，通过增加虚设端子来提升压痕的稳定性，减少在绑定过程中IC芯片发生形变、凹陷及翘起，并改善绑定不良。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (10)

1.一种芯片绑定结构，其特征在于，所述芯片绑定结构包括载体和芯片；
所述载体和所述芯片上均设置有信号端子，所述载体上的所述信号端子和所述芯片上的所述信号端子电性绑定；所述信号端子分为输出信号端子和输入信号端子；
其中，在所述载体或所述芯片至少一者上设置有虚设端子，所述虚设端子设置在所述载体或所述芯片没有所述信号端子的部位上。
2.根据权利要求1所述的芯片绑定结构，其特征在于，所述载体为显示面板，所述芯片为IC芯片。
3.根据权利要求1所述的芯片绑定结构，其特征在于，所述输出信号端子至少有3排。
4.根据权利要求1所述的芯片绑定结构，其特征在于，所述输入信号端子与所述输出信号端子之间的间距至少大于500微米。
5.根据权利要求1所述的芯片绑定结构，其特征在于，所述虚设端子位于所述输入信号端子与所述输出信号端子中间。
6.根据权利要求5所述的芯片绑定结构，其特征在于，所述虚设端子至少存在一排。
7.根据权利要求5所述的芯片绑定结构，其特征在于，所述虚设端子大小与所述输入信号端子相同。
8.根据权利要求7所述的芯片绑定结构，其特征在于，所述虚设端子高度与所述输入信号端子相同。
9.根据权利要求8所述的芯片绑定结构，其特征在于，所述虚设端子支撑所述载体与所述芯片。
10.根据权利要求1所述的芯片绑定结构，其特征在于，在所述载体的对应位置设置有相应的虚设端子。
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