WO2014057908A1 - 駆動チップ及び表示装置 - Google Patents

駆動チップ及び表示装置 Download PDF

Info

Publication number
WO2014057908A1
WO2014057908A1 PCT/JP2013/077238 JP2013077238W WO2014057908A1 WO 2014057908 A1 WO2014057908 A1 WO 2014057908A1 JP 2013077238 W JP2013077238 W JP 2013077238W WO 2014057908 A1 WO2014057908 A1 WO 2014057908A1
Authority
WO
WIPO (PCT)
Prior art keywords
driving chip
liquid crystal
terminal group
terminal
chip according
Prior art date
Application number
PCT/JP2013/077238
Other languages
English (en)
French (fr)
Inventor
松井 隆司
武志 堀口
塩田 素二
Original Assignee
シャープ株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by シャープ株式会社 filed Critical シャープ株式会社
Priority to CN201380052057.XA priority Critical patent/CN104704621B/zh
Priority to US14/433,711 priority patent/US9318454B2/en
Publication of WO2014057908A1 publication Critical patent/WO2014057908A1/ja

Links

Images

Classifications

    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333Constructional arrangements; Manufacturing methods
    • G02F1/1345Conductors connecting electrodes to cell terminals
    • G02F1/13452Conductors connecting driver circuitry and terminals of panels
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838Geometry or layout
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601Structure
    • H01L2224/0603Bonding areas having different sizes, e.g. different heights or widths
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061Disposition
    • H01L2224/0612Layout
    • H01L2224/0613Square or rectangular array
    • H01L2224/06131Square or rectangular array being uniform, i.e. having a uniform pitch across the array
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061Disposition
    • H01L2224/0612Layout
    • H01L2224/0613Square or rectangular array
    • H01L2224/06133Square or rectangular array with a staggered arrangement, e.g. depopulated array
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061Disposition
    • H01L2224/0612Layout
    • H01L2224/0613Square or rectangular array
    • H01L2224/06134Square or rectangular array covering only portions of the surface to be connected
    • H01L2224/06135Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061Disposition
    • H01L2224/0612Layout
    • H01L2224/06177Combinations of arrays with different layouts
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/1401Structure
    • H01L2224/1403Bump connectors having different sizes, e.g. different diameters, heights or widths
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141Disposition
    • H01L2224/1412Layout
    • H01L2224/1413Square or rectangular array
    • H01L2224/14131Square or rectangular array being uniform, i.e. having a uniform pitch across the array
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141Disposition
    • H01L2224/1412Layout
    • H01L2224/1413Square or rectangular array
    • H01L2224/14133Square or rectangular array with a staggered arrangement, e.g. depopulated array
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141Disposition
    • H01L2224/1412Layout
    • H01L2224/1413Square or rectangular array
    • H01L2224/14134Square or rectangular array covering only portions of the surface to be connected
    • H01L2224/14135Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141Disposition
    • H01L2224/1412Layout
    • H01L2224/14177Combinations of arrays with different layouts
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/1451Function
    • H01L2224/14515Bump connectors having different functions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/29198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29199Material of the matrix
    • H01L2224/2929Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/29198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298Fillers
    • H01L2224/29299Base material
    • H01L2224/293Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8112Aligning
    • H01L2224/81136Aligning involving guiding structures, e.g. spacers or supporting members
    • H01L2224/81138Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
    • H01L2224/81139Guiding structures on the body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812Applying energy for connecting
    • H01L2224/81201Compression bonding
    • H01L2224/81203Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818Bonding techniques
    • H01L2224/8185Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8312Aligning
    • H01L2224/83136Aligning involving guiding structures, e.g. spacers or supporting members
    • H01L2224/83138Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
    • H01L2224/83139Guiding structures on the body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/832Applying energy for connecting
    • H01L2224/83201Compression bonding
    • H01L2224/83203Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • H01L2224/8385Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83851Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester being an anisotropic conductive adhesive
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/12Passive devices, e.g. 2 terminal devices
    • H01L2924/1204Optical Diode
    • H01L2924/12041LED
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/35Mechanical effects
    • H01L2924/351Thermal stress
    • H01L2924/3511Warping
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/38Effects and problems related to the device integration
    • H01L2924/381Pitch distance

Definitions

  • the present invention relates to a driving chip and a display device including the driving chip.
  • liquid crystal display devices have been used as small and medium display devices such as portable information terminals.
  • the liquid crystal display device is equipped with a drive chip for driving the liquid crystal panel, and a COG (chip on glass) system in which the drive chip is directly mounted on the liquid crystal panel is used to cope with the thinning of the liquid crystal display device. It has been.
  • COG chip on glass
  • an ACF anisotropic conductive film
  • the driving chip and the liquid crystal panel are electrically connected by pressure bonding at a high temperature.
  • Patent Document 1 includes a base body including one surface having a first end and a second end parallel to the long side, and a third end and a fourth end parallel to the short side perpendicular to the long side, A plurality of input terminals formed at the first end along the long side of the base body, a plurality of first output terminals arranged along the long side at the second end, and the input terminal and the first output terminal; There is disclosed a drive chip including a dummy terminal formed between the two, and the dummy terminal formed in one or more rows along the long side.
  • Patent Document 1 since the dummy terminals are arranged in one or more rows in the long side direction of the driving chip, it is difficult to secure the circuit area because it is necessary to increase the size of the driving chip if the circuit area is to be secured.
  • An object of the present invention is to provide a drive chip that prevents a connection failure by suppressing warpage while securing a circuit area. It is another object of the present invention to provide a display device on which the driving chip is mounted.
  • the present invention is arranged in a staggered manner in a base body, two sets of terminal groups respectively disposed along opposite sides of the base body in the longitudinal direction, and two or more rows.
  • a narrow pitch portion having a narrow terminal pitch in the longitudinal direction
  • a rough pitch portion having a pitch in the longitudinal direction wider than the narrow pitch portion
  • a driving chip including bumps arranged in parallel in the rough pitch portion is provided.
  • the present invention by providing dummy bumps on the driving chip, the bending of the driving chip due to heat during crimping in the COG process is suppressed. As a result, the driving chip and the liquid crystal panel are maintained in parallel, and poor electrical connection between the driving chip and the liquid crystal panel is prevented. Further, by arranging the dummy bumps in parallel in the rough pitch portion where the circuit is not crowded, a sufficient circuit area can be secured without increasing the size of the driving chip.
  • FIG. 1 is an exploded perspective view showing a liquid crystal display device according to an embodiment of the present invention.
  • the liquid crystal display device 10 is drawn in a state where it is placed horizontally so that the display surface faces upward.
  • the liquid crystal display device 10 can be used as a television or computer display.
  • the liquid crystal display device 10 includes a backlight chassis 11, a light source unit 12, a light guide plate 13, an optical sheet 14, a panel frame 15, a liquid crystal panel 16 on which a driving chip 20 is mounted, and a bezel 17.
  • An assembly of the backlight chassis 11, the light source units 12 and 12, the light guide plate 13, and the optical sheet 14 is referred to as a backlight device 18.
  • the backlight chassis 11 is a box-shaped member that is a base for mounting (accommodating) each member of the backlight device 18 such as the light source unit 12, the light guide plate 13, and the optical sheet 14. It is desirable to use SECC (steel plate), Al, or the like as the material of the backlight chassis 11 in order to ensure rigidity and heat dissipation.
  • SECC steel plate
  • Al aluminum
  • the light source unit 12 includes an LED (Light Emitting Diode) which is a point light source and an LED substrate on which the LED is mounted.
  • LED Light Emitting Diode
  • a plurality of LEDs are arranged along the one side of the light guide plate 13 at a predetermined interval on the LED substrate.
  • the arrangement of the light source unit 12 employs an edge light system.
  • a metal substrate such as Al is often used as an LED substrate in consideration of heat dissipation and strength.
  • the two light source units 12 and 12 are provided along the opposite side surfaces of the light guide plate 13, but the light source unit 12 may be provided only along one side surface of the light guide plate 13.
  • the configuration may also be provided along the other side surface of the light guide plate 13. That is, the light source unit 12 may be provided along at least one of the side surfaces of the light guide plate 13.
  • the side faces the LED and serves as a light incident portion (light incident surface) that guides light from the LED into the light guide plate 13.
  • the light guide plate 13 has a pair of main surfaces (upper surface and lower surface) and a plurality of side surfaces (four surfaces in FIG. 1) formed therebetween.
  • the light guide plate 13 is a member that converts the LED light incident from its end face (side face) into a surface light source and derives it from the top face, and its material is acrylic, PC (polycarbonate), etc. from the viewpoint of thickness reduction and weight reduction. It is desirable to use this resin.
  • the optical sheet 14 is a general term for a diffusion sheet, a lens sheet, a brightness enhancement sheet, and the like, and is a combination of any one or a plurality of these sheets. Since the optical sheet 14 is stacked on the light guide plate 13 to irradiate the liquid crystal panel 16 with uniform light, if the sheet has wrinkles or bends, the display quality deteriorates.
  • the panel frame 15 is a frame-like member that holds the liquid crystal panel 16 so that the liquid crystal panel 16 and the optical sheet 14 do not contact each other, and it is desirable to use a resin such as PC as the material.
  • the panel frame 15 also has a role of suppressing warping and bending of the optical sheet 14.
  • the liquid crystal panel 16 is a member in which a liquid crystal element is injected between two transparent substrates.
  • the liquid crystal element is driven under the control of the drive chip 20 and is displayed by being illuminated by the backlight device 18.
  • the drive chip 20 includes a base body, a plurality of input terminals, and a plurality of output terminals, and is mounted on the liquid crystal panel 16 by the COG method. Then, the drive chip 20 converts image data input from the outside into a drive signal suitable for driving the liquid crystal panel 16 and applies it to the liquid crystal panel at an optimal timing.
  • the bezel 17 is a member that holds and holds the liquid crystal panel 16 in a frame shape, and covers the box-shaped backlight chassis 11 so as to cover it.
  • the material may be PC, ABS resin, CFRP (carbon fiber reinforced plastics), etc. for weight reduction. For further weight reduction, these materials may be used to integrally form a casing (not shown) as an exterior and the bezel 17.
  • FIG. 2 is a plan view of the drive chip according to the first embodiment of the present invention.
  • the drive chip 201 of the first embodiment which is an embodiment of the drive chip 20 described above, includes a base body 202, an input terminal group 203, an output terminal group 204, and dummy bumps 205.
  • the base main body 202 is an insulating material having a rectangular surface on which the terminal group is disposed, and has a thickness of 0.2 mm or less and a short-side length of 1.5 mm or more, for example. Inside the base body 202, a semiconductor element (not shown) for converting an image signal input from the outside into a drive signal necessary for driving is provided.
  • the input terminal group 203 and the output terminal group 204 are two sets of terminal groups respectively disposed along opposite sides of the base body 202 in the longitudinal direction.
  • the input terminal group 203 is formed by arranging rectangular terminals 203a in a straight line at equal intervals in one row.
  • the input terminal group 203 may be in two or more rows.
  • the output terminal group 204 is formed by arranging two rectangular terminals 204a smaller than the input terminals in a staggered manner in two rows. In the vicinity of the center of the output terminal group 204 in the longitudinal direction, the pitch in the longitudinal direction in which the terminals 204a are arranged to ensure a circuit area is wider than the surroundings (narrow pitch portions 204b and 204c, which will be described later). This will be referred to as a section 204c. On the other hand, since it is not necessary to secure a circuit area on both sides of the rough pitch portion 204c, the terminals 204a are densely arranged at a pitch narrower than the rough pitch portion 204c, and these portions are referred to as narrow pitch portions 204b and 204d.
  • the output terminal group 204 may have three or more rows.
  • the input terminal group 203 and the output terminal group 204 may be interchanged so that the input terminal group 203 is staggered and the output terminal group is linear. Further, both the terminal groups 203 and 204 may be in a staggered pattern or in a straight line with two or more rows.
  • the dummy bump 205 is a dummy bump that is not electrically connected.
  • the dummy bump 205 is disposed substantially at the center of the base body 202. That is, the dummy bumps 205 are arranged between the input terminal group 203 and the output terminal group 204 and in parallel with the rough pitch portion 204c.
  • the height (thickness) of the dummy bump 205 is equal to the height (thickness) of the input terminal group 203 and the output terminal group 204.
  • the dummy bump 205 has a larger area than the terminals 203a and 204a. Instead of the dummy bump 205, a functional bump that is electrically connected may be used.
  • FIG. 3 is a cross-sectional view in the short direction of the drive chip 201 in the liquid crystal display device on which the drive chip 201 of the first embodiment is mounted.
  • an ACF (anisotropic conductive film) 31 is sandwiched between the driving chip 201 and the liquid crystal panel 16 and the two terminal groups 203 are bonded by high pressure by a COG process. 204 and the conductive line 30 are electrically connected.
  • ACF 31 is schematically illustrated using a large number of conductive particles contained in ACF 31.
  • the dummy bumps 205 are pressure bonded to the liquid crystal panel 16 via the ACF 31.
  • FIG. 4 is a cross-sectional view in the short direction of the driving chip in the liquid crystal display device on which the driving chip of the comparative example is mounted.
  • the driving chip 100 of the comparative example has a configuration in which the dummy bump 205 is omitted from the driving chip 201 of the first embodiment.
  • the driving chip 100 is short due to the heat during the crimping in the COG process.
  • the liquid crystal panel 16 bends in the reverse direction and is bent in the reverse direction.
  • the gap between the output terminal group 204 and the terminals 204a in the outer row is increased with the liquid crystal panel 16, and sufficient flatness of the conductive particles in the ACF 31 cannot be obtained. Connection failure occurs.
  • the driving chip 201 according to the first embodiment by providing the dummy bump 205, the bending of the driving chip 201 due to heat at the time of pressure bonding in the COG process is suppressed. As a result, the driving chip 201 and the liquid crystal panel 16 are maintained in parallel (see FIG. 3), and sufficient flatness of the conductive particles is obtained in the ACF 31 that contacts all the terminals 203a and 204a. A poor electrical connection with the panel 16 is prevented.
  • the driving chip 201 of the first embodiment since the dummy bumps 205 are arranged in parallel to the rough pitch portion 204c where the circuit is not crowded, a sufficient circuit area can be secured without increasing the size of the driving chip 201. Can do.
  • FIG. 5 is a plan view of a driving chip according to the second embodiment of the present invention.
  • the driving chip 206 according to the second embodiment which is an embodiment of the driving chip 20 described above, includes two dummy bumps 205 according to the first embodiment.
  • symbol is attached
  • the two dummy bumps 205 are arranged along the longitudinal direction substantially at the center of the base body 202. That is, the two dummy bumps 205 are arranged in parallel to the rough pitch portion 204c between the input terminal group 203 and the output terminal group 204.
  • FIG. 6 is a plan view of another drive chip according to the second embodiment of the present invention.
  • the drive chip 207 of the second embodiment which is an embodiment of the drive chip 20 described above, is provided with three dummy bumps 205 of the first embodiment.
  • the three dummy bumps 205 are arranged along the longitudinal direction at substantially the center of the base body 202. That is, the three dummy bumps 205 are arranged between the input terminal group 203 and the output terminal group 204 and in parallel with the rough pitch portion 204c.
  • dummy bumps 205 may be provided.
  • the drive chip of the second embodiment is provided with a plurality of dummy bumps 205, and it is possible to more reliably prevent poor electrical connection between the drive chip and the liquid crystal panel 16 while securing a circuit area.
  • a functional bump may be used instead of the dummy bump 205.
  • FIG. 7 is a plan view of a drive chip according to a third embodiment of the present invention.
  • the driving chip 208 according to the third embodiment which is an embodiment of the driving chip 20 described above, has a rough pitch portion 204c arranged at the longitudinal end portion of the output terminal group 204 in the first embodiment.
  • symbol is attached
  • the dummy bumps 205 are disposed in the vicinity of the end of the base body 202 in the longitudinal direction. That is, the dummy bumps 205 are arranged between the input terminal group 203 and the output terminal group 204 and in parallel with the rough pitch portion 204c.
  • the dummy bumps 205 are arranged in parallel with the rough pitch portion 204c, so that the circuit area can be secured and the driving chip and the liquid crystal panel 16 can be secured. It can prevent poor electrical connection.
  • a functional bump may be used instead of the dummy bump 205.
  • a plurality of dummy bumps 205 may be provided as in the second embodiment.
  • the drive chip of the present invention can be used for a display device such as a liquid crystal display device, and can be particularly suitably used for a small-sized liquid crystal display device such as a portable information terminal.

Landscapes

  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Optics & Photonics (AREA)
  • Chemical & Material Sciences (AREA)
  • Mathematical Physics (AREA)
  • Geometry (AREA)
  • Liquid Crystal (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

 駆動チップは、ベース本体と、ベース本体の長手方向の対向する辺に沿ってそれぞれ配設された2組の端子群と、2列以上で千鳥状に配置された一方の端子群において、長手方向の端子のピッチが狭い狭ピッチ部と、長手方向の端子のピッチが狭ピッチ部より広いラフピッチ部と、2組の端子群の間であって、ラフピッチ部に並設されたダミーバンプとを備えた構成とする。

Description

駆動チップ及び表示装置
 本発明は、駆動チップ及びその駆動チップを備えた表示装置に関する。
 従来から、携帯情報端末等の中小型の表示装置として液晶表示装置が用いられている。液晶表示装置には液晶パネルを駆動するための駆動チップが搭載されており、液晶表示装置の薄型化に対応するため、駆動チップを液晶パネル上に直接実装するCOG(チップオングラス)方式が用いられている。COG方式では通常、駆動チップと液晶パネルとの間にACF(異方性導電フィルム)を挟み、高温で圧着することにより、駆動チップと液晶パネルとを電気的に接続している。
 そして近年、液晶表示装置のさらなる薄型化が求められており、駆動チップも薄型化が要求されている。しかし、駆動チップを薄くすると、圧着の際の熱で駆動チップが撓むという問題が生じる。これにより、駆動チップと液晶パネルとの電気的接続不良が発生するおそれがある。
 特許文献1には、長辺と平行な第1端部と第2端部、及び長辺と垂直な短辺と平行な第3端部と第4端部とを有する一面を含むベース本体、ベース本体の長辺に沿って第1端部に形成される多数の入力端子、第2端部に長辺に沿って配列される多数の第1出力端子、及び入力端子と第1出力端子との間に形成されるダミー端子を含み、ダミー端子は、長辺に沿って1列以上で形成される駆動チップが開示されている。
特開2005-203758号公報
 しかしながら、特許文献1では駆動チップの長辺方向に一列以上でダミー端子を並べているので、回路領域を確保しようとすると駆動チップのサイズを大きくしなければならず、回路領域の確保が難しい。
 本発明は、回路領域を確保しつつ、反りを抑制することで接続不良を防止する駆動チップを提供することを目的とする。また、その駆動チップを搭載した表示装置を提供することも目的とする。
 上記目的を達成するために本発明は、ベース本体と、前記ベース本体の長手方向の対向する辺に沿ってそれぞれ配設された2組の端子群と、2列以上で千鳥状に配置された一方の前記端子群において、長手方向の端子のピッチが狭い狭ピッチ部と、長手方向の端子のピッチが該狭ピッチ部より広いラフピッチ部と、前記2組の端子群の間であって、前記ラフピッチ部に並設されたバンプと、を備えた駆動チップとする。
 本発明によると、駆動チップにダミーバンプを設けることにより、COG工程における圧着の際の熱による駆動チップの撓みが抑制される。その結果、駆動チップと液晶パネルとが平行に維持され、駆動チップと液晶パネルとの電気的接続不良が防止される。また、ダミーバンプを回路の混み合っていないラフピッチ部に並設することにより、駆動チップのサイズを大きくしなくても十分に回路領域を確保することができる。
本発明の一実施形態の液晶表示装置を示す分解斜視図である。 本発明の第1実施形態の駆動チップの平面図である。 第1実施形態の駆動チップを搭載した液晶表示装置における駆動チップの短手方向の断面図である。 比較例の駆動チップを搭載した液晶表示装置における駆動チップの短手方向の断面図である。 本発明の第2実施形態の駆動チップの平面図である。 本発明の第2実施形態の他の駆動チップの平面図である。 本発明の第3実施形態の駆動チップの平面図である。
 以下に本発明の実施形態を図面を参照して説明する。
 図1は、本発明の一実施形態の液晶表示装置を示す分解斜視図である。図1において液晶表示装置10は、表示面が上向きになるように水平に置かれた状態で描かれている。
 この液晶表示装置10は、テレビやコンピュータのディスプレイとして利用できる。液晶表示装置10は、バックライトシャーシ11と、光源ユニット12と、導光板13と、光学シート14と、パネルフレーム15と、駆動チップ20を搭載した液晶パネル16と、ベゼル17とを備えている。そして、バックライトシャーシ11と、光源ユニット12、12と、導光板13と、光学シート14とを組み立てたものをバックライト装置18と称する。
 バックライトシャーシ11は、光源ユニット12、導光板13、光学シート14などのバックライト装置18の各部材を搭載(収容)するための土台となる部材であり箱形である。バックライトシャーシ11の材料には、剛性及び放熱性を確保するため、SECC(鋼板)やAlなどを用いることが望ましい。
 光源ユニット12は、点状光源であるLED(Light Emitting Diode)と、LEDを搭載するLED基板とを含んでいる。なお、光源としては、LEDの他に線状光源である蛍光管などを用いてもよい。そして、LED基板上で複数のLEDが導光板13の一辺に沿って所定間隔で配設されている。光源ユニット12の配置は、エッジライト方式を採用している。大型の液晶表示装置においては、LED基板として放熱性や強度を考慮してAlなどの金属基板を用いることが多い。
 また、光源ユニット12をバックライトシャーシ11に固定する固定手段としては、ネジや粘着剤を用いることができる。また、図1では2つの光源ユニット12、12がそれぞれ導光板13の対向する側面に沿って設けられているが、導光板13の一側面に沿ってのみ光源ユニット12を設ける構成としてもよいし、導光板13の他の側面に沿っても設ける構成としてもよい。つまり、光源ユニット12は導光板13の側面の少なくとも1つに沿って設ける構成とすればよい。ここで、側面はLEDに対向し、LEDからの光を導光板13内へ導く入光部(入光面)となる。
 導光板13は、一対の主面(上面及び下面)とその間に形成された複数の側面(図1では4面)とを有する。導光板13は、その端面(側面)から入射したLEDの光を面光源へ変換して上面から導出する部材であり、その材料としては薄型化、軽量化の観点からアクリルやPC(ポリカーボネート)などの樹脂を用いることが望ましい。
 光学シート14は、拡散シート、レンズシート、輝度向上シート等の総称であり、これらのシートの何れか1枚又は複数枚を組み合わせたものである。光学シート14は導光板13上に重ねられ、液晶パネル16に均一な光を照射するためのものであるので、シートに皺や撓みがあると表示品位の悪化原因となる。
 パネルフレーム15は、液晶パネル16と光学シート14とが接触しないように液晶パネル16を保持する額縁状の部材であり、その材料としてはPCなどの樹脂を用いることが望ましい。また、パネルフレーム15には光学シート14の反りや撓みを抑制する役割もある。
 液晶パネル16は、2枚の透明基板の間に液晶素子が注入された部材であり、駆動チップ20の制御によって液晶素子が駆動され、バックライト装置18により照明されることで映像を表示する。
 駆動チップ20は、ベース本体と、複数の入力端子と、複数の出力端子とを備え、液晶パネル16にCOG方式で搭載される。そして、駆動チップ20は外部から入力された画像データを液晶パネル16の駆動に適合した駆動信号に変換し、最適なタイミングで液晶パネルに印加する。
 ベゼル17は、額縁状で液晶パネル16を押さえて固定する部材であり、箱形のバックライトシャーシ11に蓋をするように被せられる。その材料としてはSECCやAlなどの他、軽量化のためにPC、ABS樹脂、CFRP((carbon fiber reinforced plastics)炭素繊維強化プラスチック)などを用いてもよい。さらなる軽量化のためには、これらの材料を用い、外装となる筐体(不図示)とベゼル17とを一体成形してもよい。
 以下、このような液晶表示装置10における本発明の特徴的な構成である駆動チップ20の実施形態について詳しく説明する。
<第1実施形態>
 図2は、本発明の第1実施形態の駆動チップの平面図である。上述した駆動チップ20の一実施形態である第1実施形態の駆動チップ201は、ベース本体202、入力端子群203、出力端子群204、ダミーバンプ205を有している。
 ベース本体202は、端子群が配設される面が矩形の絶縁材であり、例えば、厚みが0.2mm以下、短手方向の長さが1.5mm以上である。ベース本体202の内部には、外部から入力される画像信号を駆動に必要な駆動信号に変換するための半導体素子(不図示)が備えられている。
 入力端子群203と出力端子群204は、ベース本体202の長手方向の対向する辺に沿ってそれぞれ配設された2組の端子群である。入力端子群203は、矩形の各端子203aが1列に等間隔で直線状に並んで形成されている。なお、入力端子群203は2列以上であってもよい。
 出力端子群204は、入力端子より小さな矩形の各端子204aが2列で千鳥状に配置されて形成されている。出力端子群204の長手方向の中央付近は、回路領域を確保するため端子204aが配置される長手方向のピッチが周囲(後述する狭ピッチ部204b、204c)より広くなっており、この部分をラフピッチ部204cと称する。一方、ラフピッチ部204cの両側は回路領域を確保しなくてよいため端子204aがラフピッチ部204cよりも狭いピッチで密に配置されており、この部分を狭ピッチ部204b、204dと称する。なお、出力端子群204は3列以上であってもよい。
 なお、入力端子群203と出力端子群204は配置の形状を入れ替え、入力端子群203を千鳥状、出力端子群を直線状としてもよい。また、両端子群203、204とも千鳥状又は2列以上の直線状としてもよい。
 ダミーバンプ205は、電気的に接続されないダミーのバンプである。ダミーバンプ205はベース本体202のほぼ中央に配設される。つまり、ダミーバンプ205は入力端子群203と出力端子群204の間であって、ラフピッチ部204cに並設される。ダミーバンプ205の高さ(厚み)は、入力端子群203及び出力端子群204の高さ(厚み)と等しい。そして、ダミーバンプ205は各端子203a、204aより大きな面積を有する。なお、ダミーバンプ205に代えて電気的に接続される機能バンプとしてもよい。
 図3は、第1実施形態の駆動チップ201を搭載した液晶表示装置における駆動チップ201の短手方向の断面図である。導電ライン30が形成された液晶パネル16を用い、駆動チップ201と液晶パネル16との間にACF(異方性導電フィルム)31を挟み、COG工程によって高温で圧着することにより、両端子群203、204と導電ライン30とを電気的に接続している。図3ではACF31をACF31に含まれる多数の導電粒子を用いて模式的に図示している。ダミーバンプ205はACF31を介して液晶パネル16に圧着される。
 図4は、比較例の駆動チップを搭載した液晶表示装置における駆動チップの短手方向の断面図である。比較例の駆動チップ100は第1実施形態の駆動チップ201からダミーバンプ205を省いた構成である。
 上述したように、ベース本体の厚みが0.2mm以下と薄く、ベース本体の短手方向の長さが1.5mm以上と長いため、COG工程における圧着の際の熱で駆動チップ100が短手方向に撓み、液晶パネル16が逆方向に撓んで逆反りの状態となる。その結果、特に出力端子群204の外列の端子204aにおいて液晶パネル16との隙間が大きくなり、ACF31中の導電粒子の十分な粒子扁平が得られず、駆動チップ100と液晶パネル16との電気的接続不良が発生する。
 これに対して、第1実施形態の駆動チップ201を搭載した液晶表示装置では、ダミーバンプ205を設けることにより、COG工程における圧着の際の熱による駆動チップ201の撓みが抑制される。その結果、駆動チップ201と液晶パネル16とが平行に維持され(図3の参照)、全ての端子203a、204aに接触するACF31において導電粒子の十分な粒子扁平が得られ、駆動チップ201と液晶パネル16との電気的接続不良が防止される。
 また、第1実施形態の駆動チップ201において、ダミーバンプ205は回路の混み合っていないラフピッチ部204cに並設されるので、駆動チップ201のサイズを大きくしなくても十分に回路領域を確保することができる。
<第2実施形態>
 図5は、本発明の第2実施形態の駆動チップの平面図である。上述した駆動チップ20の一実施形態である第2実施形態の駆動チップ206は、第1実施形態のダミーバンプ205を2つ配設したものである。その他、第1実施形態と同様の構成には同符号を付し、その詳細な説明を省略する。
 図5に示すように、2つのダミーバンプ205は、ベース本体202のほぼ中央に長手方向に沿って並んでいる。つまり、2つのダミーバンプ205は、入力端子群203と出力端子群204の間であって、ラフピッチ部204cに並設される。
 図6は、本発明の第2実施形態の他の駆動チップの平面図である。上述した駆動チップ20の一実施形態である第2実施形態の駆動チップ207は、第1実施形態のダミーバンプ205を3つ配設したものである。図6に示すように、3つのダミーバンプ205は、ベース本体202のほぼ中央に長手方向に沿って並んでいる。つまり、3つのダミーバンプ205は、入力端子群203と出力端子群204の間であって、ラフピッチ部204cに並設される。
 なお、第2実施形態においてダミーバンプ205は4つ以上配設してもよい。このように、第2実施形態の駆動チップはダミーバンプ205を複数配設したものであり、回路領域を確保しつつ、より確実に駆動チップと液晶パネル16との電気的接続不良を防止できる。なお、第1実施形態と同様に、ダミーバンプ205に代えて機能バンプとしてもよい。
<第3実施形態>
 図7は、本発明の第3実施形態の駆動チップの平面図である。上述した駆動チップ20の一実施形態である第3実施形態の駆動チップ208は、第1実施形態においてラフピッチ部204cを出力端子群204の長手方向端部に配置したものである。その他、第1実施形態と同様の構成には同符号を付し、その詳細な説明を省略する。
 図7に示すように、ダミーバンプ205はベース本体202の長手方向端部付近に配設される。つまり、ダミーバンプ205は入力端子群203と出力端子群204の間であって、ラフピッチ部204cに並設される。
 このように、ラフピッチ部204cがベース本体202の端部付近に位置している場合でもダミーバンプ205をラフピッチ部204cに並設することで、回路領域を確保しつつ、駆動チップと液晶パネル16との電気的接続不良を防止できる。なお、第1実施形態と同様に、ダミーバンプ205に代えて機能バンプとしてもよい。また、第3実施形態において第2実施形態のように、ダミーバンプ205を複数配設してもよい。
 本発明の駆動チップは、液晶表示装置をはじめとする表示装置に利用でき、特に携帯情報端末等の中小型の液晶表示装置に好適に利用することができる。
   10  液晶表示装置
   11  バックライトシャーシ
   12  光源ユニット
   13、21、31、41  導光板
   14 光学シート
   15  パネルフレーム
   16  液晶パネル
   17  ベゼル
   18  バックライト装置
   30  導電ライン
   31  ACF
   201、206~208  駆動チップ
   202  ベース本体
   203  入力端子
   203a、204a  端子
   204  出力端子
   204b、204d  狭ピッチ部
   204c  ラフピッチ部
   205  ダミーバンプ

Claims (10)

  1.  ベース本体と、
     前記ベース本体の長手方向の対向する辺に沿ってそれぞれ配設された2組の端子群と、
     2列以上で千鳥状に配置された一方の前記端子群において、長手方向の端子のピッチが狭い狭ピッチ部と、長手方向の端子のピッチが該狭ピッチ部より広いラフピッチ部と、
     前記2組の端子群の間であって、前記ラフピッチ部に並設されたバンプと、を備えた駆動チップ。
  2.  前記バンプが複数配設されたことを特徴とする請求項1記載の駆動チップ。
  3.  前記ラフピッチ部が前記一方の端子群の中央に位置することを特徴とする請求項1又は2記載の駆動チップ。
  4.  前記ラフピッチ部が前記一方の端子群の端に位置することを特徴とする請求項1又は2記載の駆動チップ。
  5.  前記ラフピッチ部を有する端子群が出力端子群であることを特徴とする請求項1~4の何れかに記載の駆動チップ。
  6.  前記バンプは電気的に接続されないダミーバンプであることを特徴とする請求項1~5の何れかに記載の駆動チップ。
  7.  前記バンプは電気的に接続される機能バンプであることを特徴とする請求項1~5の何れかに記載の駆動チップ。
  8.  前記2組の端子群と前記バンプとの高さが等しいことを特徴とする請求項1~7の何れかに記載の駆動チップ。
  9.  前記バンプが前記2組の端子群の各端子より大きな面積を有することを特徴とする請求項1~8の何れかに記載の駆動チップ。
  10.  請求項1~9の何れかに記載の駆動チップがチップオングラス方式で搭載された表示装置。
PCT/JP2013/077238 2012-10-11 2013-10-07 駆動チップ及び表示装置 WO2014057908A1 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN201380052057.XA CN104704621B (zh) 2012-10-11 2013-10-07 驱动芯片和显示装置
US14/433,711 US9318454B2 (en) 2012-10-11 2013-10-07 Drive chip and display apparatus

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2012225663 2012-10-11
JP2012-225663 2012-10-11

Publications (1)

Publication Number Publication Date
WO2014057908A1 true WO2014057908A1 (ja) 2014-04-17

Family

ID=50477375

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2013/077238 WO2014057908A1 (ja) 2012-10-11 2013-10-07 駆動チップ及び表示装置

Country Status (3)

Country Link
US (1) US9318454B2 (ja)
CN (1) CN104704621B (ja)
WO (1) WO2014057908A1 (ja)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2015182496A1 (ja) * 2014-05-30 2015-12-03 シャープ株式会社 実装基板、実装基板の製造方法、及び実装基板の製造装置
JP2016127259A (ja) * 2015-01-07 2016-07-11 三星ディスプレイ株式會社Samsung Display Co.,Ltd. 表示装置
WO2016114381A1 (ja) * 2015-01-16 2016-07-21 デクセリアルズ株式会社 接続構造体
WO2017138443A1 (ja) * 2016-02-10 2017-08-17 シャープ株式会社 半導体装置及び表示装置
TWI663697B (zh) * 2014-07-22 2019-06-21 日商迪睿合股份有限公司 連接體、及連接體之製造方法

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102287754B1 (ko) * 2014-08-22 2021-08-09 삼성전자주식회사 칩 적층 반도체 패키지
KR102251231B1 (ko) * 2014-09-16 2021-05-12 엘지디스플레이 주식회사 구동 칩 패키지 및 이를 포함하는 표시장치
JP6698369B2 (ja) * 2016-02-10 2020-05-27 シナプティクス・ジャパン合同会社 表示ドライバ及び表示パネルモジュール
DE102019121371B4 (de) * 2018-08-08 2022-10-06 Lg Display Co., Ltd. Integrierte-Schaltung-Baugruppe und diese verwendende Anzeigevorrichtung
WO2020043170A1 (en) 2018-08-31 2020-03-05 Changxin Memory Technologies, Inc. Arrangement of bond pads on an integrated circuit chip
CN111009501A (zh) * 2019-08-27 2020-04-14 武汉华星光电半导体显示技术有限公司 芯片绑定结构
KR20210065580A (ko) 2019-11-27 2021-06-04 엘지디스플레이 주식회사 플렉서블 표시장치
US11721551B2 (en) * 2021-01-26 2023-08-08 Tokyo Electron Limited Localized stress regions for three-dimension chiplet formation
CN113823241B (zh) * 2021-09-30 2022-09-27 武汉华星光电技术有限公司 驱动芯片及显示面板

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003263117A (ja) * 2002-03-08 2003-09-19 Hitachi Ltd 表示装置
JP2005203758A (ja) * 2003-12-16 2005-07-28 Samsung Electronics Co Ltd 駆動チップ及びこれを有する表示装置
JP2005259924A (ja) * 2004-03-11 2005-09-22 Sharp Corp 半導体装置、半導体装置の実装構造およびそれを備える電子機器ならびに表示装置
JP2007123709A (ja) * 2005-10-31 2007-05-17 Nec Electronics Corp 半導体装置
JP2008182008A (ja) * 2007-01-24 2008-08-07 Epson Imaging Devices Corp 実装構造体、電気光学装置及び電子機器

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW506103B (en) * 2001-08-06 2002-10-11 Au Optronics Corp Bump layout on a chip
TWI292836B (ja) * 2001-10-31 2008-01-21 Chi Mei Optoelectronics Corp
US6750552B1 (en) * 2002-12-18 2004-06-15 Netlogic Microsystems, Inc. Integrated circuit package with solder bumps

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003263117A (ja) * 2002-03-08 2003-09-19 Hitachi Ltd 表示装置
JP2005203758A (ja) * 2003-12-16 2005-07-28 Samsung Electronics Co Ltd 駆動チップ及びこれを有する表示装置
JP2005259924A (ja) * 2004-03-11 2005-09-22 Sharp Corp 半導体装置、半導体装置の実装構造およびそれを備える電子機器ならびに表示装置
JP2007123709A (ja) * 2005-10-31 2007-05-17 Nec Electronics Corp 半導体装置
JP2008182008A (ja) * 2007-01-24 2008-08-07 Epson Imaging Devices Corp 実装構造体、電気光学装置及び電子機器

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2015182496A1 (ja) * 2014-05-30 2015-12-03 シャープ株式会社 実装基板、実装基板の製造方法、及び実装基板の製造装置
US10136570B2 (en) 2014-05-30 2018-11-20 Sharp Kabushiki Kaisha Mounted substrate, mounted-substrate production method, and mounted-substrate production device
TWI663697B (zh) * 2014-07-22 2019-06-21 日商迪睿合股份有限公司 連接體、及連接體之製造方法
JP2016127259A (ja) * 2015-01-07 2016-07-11 三星ディスプレイ株式會社Samsung Display Co.,Ltd. 表示装置
KR20160085038A (ko) * 2015-01-07 2016-07-15 삼성디스플레이 주식회사 표시 장치
KR102325643B1 (ko) * 2015-01-07 2021-11-12 삼성디스플레이 주식회사 표시 장치
WO2016114381A1 (ja) * 2015-01-16 2016-07-21 デクセリアルズ株式会社 接続構造体
WO2017138443A1 (ja) * 2016-02-10 2017-08-17 シャープ株式会社 半導体装置及び表示装置

Also Published As

Publication number Publication date
CN104704621B (zh) 2017-08-25
US20150279792A1 (en) 2015-10-01
CN104704621A (zh) 2015-06-10
US9318454B2 (en) 2016-04-19

Similar Documents

Publication Publication Date Title
WO2014057908A1 (ja) 駆動チップ及び表示装置
US10353138B2 (en) Display device and method for fabricating the same
JP5162834B2 (ja) 表示モジュール
US9360719B2 (en) Display device
US8885350B2 (en) Display device and television receiver
US9477124B2 (en) Display device and television device
JP6497870B2 (ja) 下部シャーシを含む表示装置
US10705392B2 (en) Display device
JP4665983B2 (ja) 電気光学装置および電子機器
CN107688253B (zh) 显示设备
CN110908180A (zh) 照明装置、显示装置及照明装置的制造方法
US20130027968A1 (en) Illumination apparatus, display apparatus, and electronic device
US20150042898A1 (en) Display device and television reception device
US8794778B2 (en) Top chassis assembly and display device having the same
KR102351509B1 (ko) 디스플레이 장치
WO2016170621A1 (ja) 光源装置、表示装置、基板ユニットの製造方法及び光源装置の製造方法
US20150370120A1 (en) Display device with heat dissipating chassis
JP5705701B2 (ja) 液晶表示装置
US20170315290A1 (en) Display apparatus
US10120221B2 (en) Display apparatus and television receiving apparatus
KR20150037299A (ko) 액정표시장치
US20140125922A1 (en) Backlight device and liquid-crystal display device comprising said backlight device
JP2008209792A (ja) 液晶表示装置
JP2011059339A (ja) 液晶表示装置
KR102046294B1 (ko) 엘이디모듈 및 그 제조방법과 엘이디모듈을 포함하는 액정표시장치

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 13845302

Country of ref document: EP

Kind code of ref document: A1

WWE Wipo information: entry into national phase

Ref document number: 14433711

Country of ref document: US

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 13845302

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: JP