發明說明： 【發明所屬之技術領域】 本發明係關於一種液晶顯示面板線路佈局，尤其是— 種配合晶粒玻璃接合（Chip On Glass, COG)製程之線路 設計。 【先前技術】 近年來’液晶顯示器（Liquid Crystal Display, LCD) 挾其輕薄、省電、無幅射線之優點，而逐漸取代傳統映像 管（Cathode Ray Tube, CRT)顯示器’廣泛應用於桌上型 電腦、個人數位助理器、筆記型電腦、數位相機與行動電 話等電子產品中。 在傳統之液晶顯示面板中，如第一圖所示，驅動晝素 顯示之驅動晶片（LSI chip) 22, 32係封裝於一可挽性印 刷電路薄膜24, 34上。而此封裝之驅動晶片22, 32係採用 捲帶式自動接合（Tape Automatic Bonding, TAB)之方式 應用於接合製程’亦即透過可撓性印刷電路薄膜24, 34將 用以製作走線之印刷電路板20, 30與玻璃基板10作電性連 接。 為了進一步追求顯示面板之輕薄化，如第二圖所示， 係顯示新一代的晶粒玻璃接合（Chip On Glass, COG)製 程所製作之液晶顯不面板。相較於第一圖之液晶顯示面 板，晶粒玻璃接合製程所製作之液晶顯示面板，係利用非 等向性導電膠（Anisotropic Conductive Film，ACF)將 驅動晶片（LSI chips) 42, 52以裸晶（Flip-chip)之方 式電性接合至玻璃基板10表面之接觸墊，因而可以節省可 撓性印刷電路薄膜34之使用。 如第一圖所示，此晶粒玻璃接合製程通常係將電路走 線直接設計於玻璃基板上（Wire-〇n-Array，WOA)。亦即將 第一圖中原本必須製作於印刷電路板3〇之線路，改為直接 製作於玻璃基板10上。又，透過此玻璃基板上之走線，直 接串接（cascade)各個驅動晶片52的技術，更是液晶顯 示面板之閘極端常見的設計。 相較於傳統捲帶式自動接合之方式，此種透過晶粒玻 璃接合製程所製作之液晶顯示面板，不僅可以減少可撓性 印刷電路_ 34之使用崎低製作成本。將電路走線直接 設計於玻璃絲_l(wga)，更可以省掉印刷電路板20 3〇 之設計與製作成本，而印刷電路板2〇, 30之精簡還可以降 低顯示器之尺寸與重量。 明參照第二圖所示’係放大顯示第二圖之液晶顯示面 板的信號端之周邊佈線區域10b，並移除驅動晶片42，以 顯Tit位於驅動晶片42下方之晶片預留區塊11G的線路佈 局。此晶片預留區塊110係排列於液晶顯示面板之周邊佈 線區域1Gb ’其相對兩邊分別具有-接觸墊組120,130。其 中’鄰近於玻璃基板邊緣1〇c之接觸墊組12〇係用以輸入 控制訊號與電源訊號。鄰近於顯示面板之巾央顯示區域 l〇a的接觸墊乡且130’則是用以輸出顯示訊號以控制畫素元 件之顯不。值得注意的是，各個晶#預㈣塊⑽間並未 有線路相互連接。因此，如第_ 如罘一圖所不，控制訊號與電源 訊號係透過可雛印職路_ 44分別輸人各個裝設於 晶片預留區塊110上之驅動晶片42。 雖然晶粒玻璃接合製程具有如此成本上的優勢，但是 文限於顯示面板之邊框（即前述周邊佈線區域）l〇b的大 小’其上所能容許之線路設計空間與接點數量係受到限 制。因此’如第二圖所示，以晶粒玻璃接合製程’搭配玻 璃基板上走線路串接各驅動晶片之方法，通常僅能適用於 接點數較少之閘極驅動晶片52。至於接點數較多之信號驅 動晶片42,其周邊線路主要還是設計於一外接之印刷電路 板40 ’而此電路板再透過可撓性印刷電路薄膜44輸入訊 號至這些信號驅動晶片42。 然而’為了更進一步降低製作成本，在玻璃基板上製 作走線以串接各個信號驅動晶片42已成為必然之趨勢。 又，由於信號驅動晶片42所處理之訊號種類繁多，所需之 接點數也較多。除了會對面板上之線路佈局造成嚴格之限 制外；如何使此串接後的線路佈局相容於既有製程（此既 有製程係配合第三圖之線路佈局），如共用現有之測試方 式、測試治具等，更成為此線路佈局導入量產之一大挑戰。 於是，如何使串接設計之顯示面板的線路佈局相容於 既有製程，已成為當前顯示面板線路佈局設計重要發展目 標之一 ° 【發明内容】 本發明之主要目的係提供一種顯示面板，利用玻璃基 板上走線串接（cascade)各個驅動晶片以降低製作成本。 並且，此顯示面板之線路佈局可相容於既有之測試製程。 本發明所提供之顯示面板線路佈局係形成於一底材 上’而在底材上形成一中央顯示區域與一周邊佈線區域。 此顯示面板線路佈局係在周邊佈'_域内定義有複數個晶 片預留區塊’用以裝置驅動晶片。並且，此顯示面板線路 佈局包括至少-第-組接觸墊、至少—第二組接觸墊與至 少-至少-連接線路。其中，第—組接觸墊係沿著晶片預 留區塊之其中-邊排列。第二組接觸塾係沿著晶片預留區 塊之另一邊排列。連接線路係跨接於第一組接觸墊與第二 組接觸墊間。 搭配此線路佈局，本發明一併提供一顯示面板，包括 一底材、複數個畫素元件、複數個晶片預留區塊、至少一 第一組接觸墊、複數個訊號輸出線路、至少一第二組接觸 塾、複數個訊號傳輸線路、複數個相互串接之驅動晶片與 至少一連接線路。其中，底材係區分為一中央顯示區域與 一周邊佈線區域。複數個晝素元件係陣列排列於中央顯示 區域。複數個晶片預留區塊係沿著中央顯示區域之邊緣， 排列於周邊佈線區域内。第一組接觸墊係沿著晶片預留區 塊鄰近於中央顯示區域之一邊排列。訊號輸出線路係由第 一組接觸墊延伸至中央顯示區域内，用以控制晝素元件之 顯示。第二組接觸墊係沿著晶片預留區塊之另一邊排列。 訊號傳輸線路係位於周邊佈線區域内，並且連接至第二組 接觸墊以傳輸顯示所需之一控制訊號與一電源訊號。驅動 晶片係裝置於晶片預留區塊上；並且，透過這些第一組接 觸塾與第二組接觸墊，電性連接至訊號輸出線路與訊號傳 輸線路。連接線路係位於晶片預留區塊内，並且跨接於第 一組接觸墊與第二組接觸墊間。 關於本發明之優點與精神可以藉由以下的發明詳述及 1322296 所附圖式得到進一步的瞭解。 【實施方式】 請參照第四A與B圖所示，係本發明顯示面板一較佳 實施例之示意圖。如第四A圖所示，此顯示面板包括一底 材200、複數個畫素元件31〇與複數個驅動晶片32〇。其中' 底材200健分為-中蝴域施與—周邊佈線區域 200b。複數個晝素元件31〇係陣列排列於中央顯示區域 2〇〇a。驅動晶片320沿著中央顯示區域2〇〇a之邊緣，排列 於周邊佈線區域200b内。 第四B圖係放大顯示第四A圖之周邊佈線區域2〇〇b， 並且移除驅動晶片320，以顯示本發明之線路佈局。如圖 中所示’周邊佈線區域2〇〇b上係設置有複數個晶片預留區 塊210，以供裝置驅動晶片32〇。各個晶片預留區塊21〇 係沿著中央顯示區域200a之邊緣，排列於周邊佈線區域 200b 内。 第一組接觸墊230係沿著晶片預留區塊2丨〇鄰近於中 央顯不區域200a之一邊210a排列。訊號輸出線路232係 由第一組接觸墊230延伸至中央顯示區域2〇〇a内。藉此， 驅動晶片320可以控制晝素元件31〇之顯示。第二組接觸 墊240係沿著晶片預留區塊21〇之另一邊21牝排列。訊號 傳輪線路242係位於周邊佈線區域2〇〇b内，並且連接至第 ^組接觸墊240，以傳輸驅動晶片32〇運作所需之控制訊 號與電源訊號。第三組接觸墊22〇係沿著晶片預留區塊21〇 鄰近於顯示面板邊緣之一邊21〇c排列。訊號輸入線路222 係連接至第三組接觸墊220，亦可用以輸入控制訊號與電SUMMARY OF THE INVENTION [Technical Field] The present invention relates to a liquid crystal display panel circuit layout, and more particularly to a circuit design for a Chip On Glass (COG) process. [Prior Art] In recent years, Liquid Crystal Display (LCD) has gradually replaced the traditional cathode tube (CRT) display by its advantages of thinness, power saving and no-beam radiation. In electronic products such as computers, personal digital assistants, notebook computers, digital cameras and mobile phones. In the conventional liquid crystal display panel, as shown in the first figure, the driving chips (LSI chips) 22, 32 for driving the pixel display are packaged on a printable printed circuit film 24, 34. The packaged driving wafers 22, 32 are applied to the bonding process by means of Tape Automatic Bonding (TAB), that is, through the flexible printed circuit films 24, 34, which are used for the printing of the traces. The circuit boards 20, 30 are electrically connected to the glass substrate 10. In order to further reduce the thickness of the display panel, as shown in the second figure, a liquid crystal display panel produced by a new generation of chip on glass (Chip On Glass, COG) process is shown. Compared with the liquid crystal display panel of the first figure, the liquid crystal display panel produced by the die glass bonding process uses an anisotropic conductive film (ACF) to drive the LSI chips 42, 52 to be bare. The Flip-chip method is electrically bonded to the contact pads on the surface of the glass substrate 10, so that the use of the flexible printed circuit film 34 can be saved. As shown in the first figure, this die glass bonding process usually uses circuit traces directly on a glass substrate (Wire-〇n-Array, WOA). Also in the first figure, the circuit which has to be fabricated on the printed circuit board 3 , will be directly fabricated on the glass substrate 10. Moreover, the technique of directly cascading the respective driving chips 52 through the wiring on the glass substrate is a common design of the gate terminal of the liquid crystal display panel. Compared with the conventional tape-and-tape automatic bonding method, the liquid crystal display panel produced by the die-grain bonding process can not only reduce the use cost of the flexible printed circuit. By designing the circuit trace directly on the glass filament _l (wga), the design and manufacturing cost of the printed circuit board 20 3 更 can be saved, and the reduction of the printed circuit board 2 〇 30 can also reduce the size and weight of the display. Referring to the second figure, the peripheral wiring area 10b of the signal terminal of the liquid crystal display panel of the second figure is enlarged, and the driving wafer 42 is removed to show that the Tit is located in the wafer reserved block 11G below the driving wafer 42. Line layout. The wafer reserved block 110 is arranged on the peripheral wiring region 1Gb' of the liquid crystal display panel, and has a contact pad group 120, 130 on opposite sides thereof. The contact pad group 12 adjacent to the edge 1c of the glass substrate is used to input a control signal and a power signal. The contact pad and the 130' adjacent to the display area of the display panel of the display panel are used to output display signals to control the display of the pixel elements. It is worth noting that there are no lines connected to each other in the pre-(four) blocks (10). Therefore, as shown in the figure, the control signal and the power signal are respectively input to the driving chips 42 respectively mounted on the chip reserved block 110 through the printable job_44. Although the grain glass bonding process has such a cost advantage, it is limited to the size of the frame of the display panel (i.e., the aforementioned peripheral wiring area) l〇b, and the number of circuit design spaces and contacts that can be tolerated is limited. Therefore, as shown in the second figure, the method of arranging the driving chips in series with the wiring on the glass substrate by the die glass bonding process is generally applicable only to the gate driving wafer 52 having a small number of contacts. As for the signal driving chip 42 having a large number of contacts, the peripheral circuit is mainly designed on an external printed circuit board 40', and the circuit board then inputs signals to the signal driving wafer 42 through the flexible printed circuit film 44. However, in order to further reduce the manufacturing cost, it has become an inevitable trend to make traces on the glass substrate to drive the chips 42 in series. Moreover, since the number of signals processed by the signal driving chip 42 is large, the number of contacts required is also large. In addition to the strict restrictions on the layout of the panels on the panel; how to make the layout of the serial connection compatible with the existing process (this has the process layout with the layout of the third diagram), such as sharing the existing test method , test fixtures, etc., has become a major challenge in the introduction of mass production of this line layout. Therefore, how to make the line layout of the display panel of the serial design compatible with the existing process has become one of the important development goals of the current layout design of the display panel. [Invention] The main object of the present invention is to provide a display panel, which utilizes The drive substrates are cascaded on the glass substrate to reduce the manufacturing cost. Moreover, the layout of the display panel can be compatible with existing test processes. The display panel circuit layout provided by the present invention is formed on a substrate to form a central display region and a peripheral wiring region on the substrate. The display panel layout is defined by a plurality of wafer reserved blocks in the peripheral area '_ domain' for driving the wafer. Also, the display panel wiring layout includes at least a -th set of contact pads, at least - a second set of contact pads and at least - at least - connection lines. Wherein, the first set of contact pads are arranged along the middle side of the wafer pre-reserved block. The second set of contact tethers are arranged along the other side of the wafer reserved block. The connecting circuit is bridged between the first set of contact pads and the second set of contact pads. The present invention provides a display panel, including a substrate, a plurality of pixel components, a plurality of chip reserved blocks, at least one first set of contact pads, a plurality of signal output lines, and at least one Two sets of contact ports, a plurality of signal transmission lines, a plurality of drive chips connected in series, and at least one connection line. Among them, the substrate is divided into a central display area and a peripheral wiring area. A plurality of elementary element arrays are arranged in the central display area. A plurality of wafer reserved blocks are arranged along the edge of the central display area and arranged in the peripheral wiring area. The first set of contact pads are arranged along one side of the wafer reserved area adjacent to the central display area. The signal output circuit extends from the first set of contact pads to the central display area to control the display of the pixel elements. The second set of contact pads are arranged along the other side of the wafer reserved block. The signal transmission line is located in the peripheral wiring area and is connected to the second set of contact pads for transmitting a desired control signal and a power signal. The driving chip system is disposed on the chip reserved block; and is electrically connected to the signal output line and the signal transmission line through the first group of contact pads and the second group of contact pads. The connection circuitry is located within the wafer reserved block and is connected between the first set of contact pads and the second set of contact pads. The advantages and spirit of the present invention will be further understood from the following detailed description of the invention and the appended claims. [Embodiment] Referring to Figures 4A and B, there is shown a schematic view of a preferred embodiment of the display panel of the present invention. As shown in Fig. 4A, the display panel includes a substrate 200, a plurality of pixel elements 31A, and a plurality of driving chips 32A. Among them, the substrate 200 is divided into - the middle field and the peripheral wiring area 200b. A plurality of halogen elements 31 are arrayed in the central display area 2〇〇a. The driving wafer 320 is arranged in the peripheral wiring region 200b along the edge of the central display region 2a. The fourth B is an enlarged view of the peripheral wiring area 2〇〇b of the fourth A diagram, and the driving wafer 320 is removed to show the wiring layout of the present invention. As shown in the figure, the peripheral wiring area 2〇〇b is provided with a plurality of wafer reserved blocks 210 for the device to drive the wafer 32. The respective wafer reserved blocks 21 are arranged along the edge of the central display region 200a and arranged in the peripheral wiring region 200b. The first set of contact pads 230 are arranged along the wafer reserve block 2 丨〇 adjacent one of the sides 210a of the central display area 200a. The signal output line 232 extends from the first set of contact pads 230 into the central display area 2a. Thereby, the driving wafer 320 can control the display of the pixel element 31. The second set of contact pads 240 are arranged along the other side 21 of the wafer reserved block 21〇. The signal transmission line 242 is located in the peripheral wiring area 2〇〇b and is connected to the first group of contact pads 240 for transmitting control signals and power signals required to drive the operation of the chip 32. The third set of contact pads 22 are arranged along the wafer reserve 21 〇 adjacent to one of the edges 21 〇 c of the display panel edge. The signal input line 222 is connected to the third group of contact pads 220, and can also be used for inputting control signals and electricity.
9 源訊號。 連接線路250係位於晶片預留區塊210内，並且跨接 於第一組接觸墊230與第二組接觸墊240間。在第一^接 觸墊230中具有至少一個測試墊A1供電路檢測之用。此測 試墊A1係透過連接線路250電連接至第二組接觸墊之一接 觸墊B1，而此接觸墊B1係連接至一訊號傳輸線路α。因 此’透過測試墊A1即可輸入訊號至訊號傳輸線路^作為 檢測之用。 請一併參照第四A圖，各個裝設於晶片預留區塊21〇 上之驅動晶片320可以透過第二組測試墊240與訊號傳輸 線路242相互串接（cascade)。因此，驅動晶片320運作 所需之控制訊號或電源訊號，可以透過此訊號傳輸線路 242 ’依序傳遞至各個驅動晶片320。相較之下，透過訊號 輸入線路222與第三組測試墊220輸入各個驅動晶片32〇 之控制訊號或電源訊號，則是分別獨立輸入各個驅動晶片 320。 就一較佳實施例而言，驅動晶片320運作所需之電源 訊號最好是經由訊號輸入線路222與第三組測試墊220輸 入，以避免電源訊號之強度在訊號傳遞過程中下降，而影 響驅動晶片320輸出之訊號品質。其次，就受訊號強度影 響不大之控制訊號而言，則可選擇經由訊號傳輸線路242 與第二組測試墊240，依序傳輸至各個驅動晶片320。值得 注意的是，本發明之線路佈局係針對以玻璃基板上走線串 接之驅動晶片，而不限於顯示面板之閘極端或是信號端。 同時，由於本發明可以利用玻璃基板上之走線串接各個驅 1322296 動晶片320。因此’如第四A圖所示，本發明之顯示面板 中’不需要為每-個驅動晶片分別設置-相對應之可 撓性印刷電路_ _。來自印刷電路板圆之訊號，可 以透過相對少數之可撓性印刷電路細棚傳遞至各個驅 動晶片320’而可以節省可撓性印刷電路薄膜棚之使用。9 source signal. Connection line 250 is located within wafer reserved block 210 and is connected between first set of contact pads 230 and second set of contact pads 240. At least one test pad A1 is provided in the first contact pad 230 for circuit detection. The test pad A1 is electrically connected to one of the contact pads B1 of the second set of contact pads via a connection line 250, and the contact pad B1 is connected to a signal transmission line α. Therefore, the signal can be input to the signal transmission line through the test pad A1 for detection. Referring to FIG. 4A, the driving chips 320 respectively mounted on the chip reserved blocks 21A can be cascaded with the signal transmission lines 242 through the second group of test pads 240. Therefore, the control signal or power signal required to drive the chip 320 can be sequentially transmitted to the respective driving chips 320 through the signal transmission line 242'. In contrast, the control signals or power signals input to the respective driving chips 32 through the signal input line 222 and the third group of test pads 220 are independently input to the respective driving chips 320. For a preferred embodiment, the power signal required to drive the chip 320 is preferably input via the signal input line 222 and the third set of test pads 220 to prevent the power signal from falling during the signal transmission process. The signal quality of the output of the driving chip 320. Secondly, in the case of a control signal that is less affected by the signal strength, it can be selectively transmitted to each of the driving chips 320 via the signal transmission line 242 and the second group of test pads 240. It is to be noted that the circuit layout of the present invention is directed to a driver chip that is serially connected in a trace on a glass substrate, and is not limited to the gate terminal or signal terminal of the display panel. At the same time, since the present invention can use the traces on the glass substrate to serially connect the respective flip-flops 3202296. Therefore, as shown in Fig. 4A, the display panel of the present invention does not need to be provided with a corresponding flexible printed circuit __ for each of the drive wafers. The signal from the printed circuit board circle can be transferred to each of the drive wafers 320' through a relatively small number of flexible printed circuit pods, thereby saving the use of the flexible printed circuit film booth.
_如第五圖所示’縣發鴨路佈局第二難實施例之 不意圖。相較料四B圖之實施例，本實施例之晶片預留 區塊210内’並未有第三組接觸塾22〇之配置。因此，驅 動晶片320運作所需之控制訊號與電源訊號係完全藉由第 二組接觸墊240與訊號傳輸線路242傳輸。又，此種配置 方式，主要可應用於閘極端之線路饰局。 …·、、不，、间π不你不發明線路佈局第三較佳實施 列=不意圖。相較於第四Β圖之實施例，本實施例之第一_ As shown in the fifth figure, the second difficult case of the county's hairline layout is not intended. Compared with the embodiment of Figure 4B, there is no configuration of the third set of contacts 22 in the wafer reserved block 210 of the present embodiment. Therefore, the control signals and power signals required to drive the operation of the chip 320 are completely transmitted by the second set of contact pads 240 and the signal transmission line 242. Moreover, this type of configuration can be mainly applied to the line decoration of the gate terminal. ...·,, no, π, you don’t invent the line layout, the third preferred implementation column = not intended. Compared with the embodiment of the fourth figure, the first embodiment
墊23〇中’具有—測試塾Α2透過位於晶片預留區塊 〇内之連接線路252直接連接至訊號傳輸線路c2。並且， 測，墊A2並未連接有訊號輸出線路咖。透過此測試整 ，即可輸入訊號至訊號傳輸線路C2進行檢測。 例之請2第七圖所示，係本發明線路佈局第四較佳實施 。相較於第四B圖之實施例，本實施例之 2 Aft23i) _ ’具#多個（圖中侧示：個）測試塾 A4 ’分別透過連接線路加，2撕連接至不同之訊 佈局路C3，C4。如圖中所示，此等連接線路25私254/之 執’可以採用如第四B圖之方式，亦即跨接於第一 觸墊230之一接觸墊A3與第二組接細接 B3間.丄沉、，p ]蛩^40之一接觸墊 ’也了以採用如第六圖所示之方式，亦即跨接於第—The pad 〇 'with the test 塾Α 2 is directly connected to the signal transmission line c2 through the connection line 252 located in the chip reserved block 〇. Moreover, it is measured that the pad A2 is not connected to the signal output line. Through this test, the signal can be input to the signal transmission line C2 for detection. As shown in the seventh figure of the second embodiment, the fourth preferred embodiment of the circuit layout of the present invention is shown. Compared with the embodiment of FIG. 4B, the 2 Aft23i) _ ' has more than one (the side shows: one) test 塾A4' respectively through the connection line, and the two tear connections are connected to different communication layouts. Road C3, C4. As shown in the figure, the connection line 25 can be used in the manner of the fourth B, that is, the contact pad A3 and the second group B3 are connected across the first contact pad 230. Between the two, p] 蛩 ^ 40 one of the contact pads 'also used in the manner shown in Figure 6, that is, connected to the first -
1322296 組測試墊230之一接觸墊A4與訊號傳輸線路C4間。 請參照第八_示’係本發爾路佈局第五較佳實施 例之示意圖。相較於第四B圖之實施例，本實施例之晶片 預留區塊210内，具有一連接線路258跨接於笛一 墊230中二個不同之接觸塾A5, A6間。其中_個接觸塾a6 係連接至訊號傳輸線路C6，另一個接觸墊A5係連接至訊 號輸出線路D5。又，接觸墊A5可充作一測試墊’以輸1 相對應之訊说至訊號傳輸線路C6作為檢測之用。 • 配合第二圖之傳統線路佈局’傳統之測試製程盘測試 治具係設計以檢測位於晶片預留區塊11()内之接觸^組° 130。相較之下’如第四B圖所示，本發明之線路佈局係增 加了第二組接觸墊240與訊號傳輸線路242。惟，就本發 明之線路佈局而言，並不需要直接檢測第二組測試墊x 240 ’而是透過檢測第-組測試塾23〇 (相對應於第三圖中 之接觸墊組⑽）即可輸人姉應之峨至喊傳輸線路 242作為檢測之用。換言之，本發明之線路佈局可相容於 馨 既有職製程（此喊峨製_搭轉三圖之線路佈 局），並且可以共用測試治具。 以上所述係利用較佳實施例詳細說明本發明，而非限 淋發明之細，*且熟知此類技藝人士皆能明瞭，適當 祕些微的改變及輕，健不失本發明之要義所在亦 不脫離本發明之精神和範圍。 【圖式簡單說明】 第-圓係-傳統_捲帶式自動接合製程之液晶顯示 面板的示意圖。 第二圖係一傳統採用晶粒玻璃接合製程之液晶顯示面 板的示意圖。 第二圖係放大顯示第二圖之液晶顯示面板信號端之線 路佈局。 局One of the 1322296 test pads 230 is in contact with the pad A4 and the signal transmission line C4. Please refer to the eighth embodiment of the present invention for a fifth preferred embodiment of the layout. In the wafer reserved block 210 of the present embodiment, a connection line 258 is connected across two different contact ports A5, A6 in the flute pad 230. One of the contact pads a6 is connected to the signal transmission line C6, and the other contact pad A5 is connected to the signal output line D5. Moreover, the contact pad A5 can be used as a test pad to detect the corresponding signal to the signal transmission line C6 for detection. • In conjunction with the traditional circuit layout of the second figure, the conventional test process disk test fixture is designed to detect the contact 130 located in the wafer reserved block 11(). In contrast, as shown in FIG. 4B, the circuit layout of the present invention adds a second set of contact pads 240 and signal transmission lines 242. However, in the case of the circuit layout of the present invention, it is not necessary to directly detect the second set of test pads x 240 ' but to detect the first set of test 塾 23 〇 (corresponding to the contact pad set (10) in the third figure) It can be used to detect the transmission line 242 as a detection. In other words, the circuit layout of the present invention can be compatible with the existing occupational process (this is called the circuit layout of the three pictures), and the test fixture can be shared. The above description of the present invention will be described in detail by way of preferred embodiments, and not limited to the details of the invention, and it is understood by those skilled in the art that the appropriate and minor changes and lightness are not essential to the invention. Without departing from the spirit and scope of the invention. [Simple diagram of the drawing] Schematic diagram of the liquid crystal display panel of the first-circle-conventional-tape-type automatic bonding process. The second figure is a schematic view of a conventional liquid crystal display panel using a grain glass bonding process. The second figure is an enlarged view showing the line layout of the signal terminal of the liquid crystal display panel of the second figure. Bureau
第四A 圖係本發明顯示面板—較佳實關之示意圖。 第四B圖放大顯示第四A圖之周邊佈線區域的線路佈 第五圖係本發明線路係 ^ 佈局第二較佳實施例之示意圖 第七圖仫士双 佈局第三較佳實施例之示意圖 第七圖係本發明線路 第八圖係本發明線_ 4四較佳實施例之示意圖 【主要元件符號說明】 局第五較佳實施例之示意圖 玻璃基板10 驅動晶片22, 32,42,於 印刷電路板20, 30 可撓性印刷電路薄腺 、34, 44 晶片預留區塊11〇 中央顯不區域1 周邊佈線區域10b 玻璃基板邊緣l〇c 接觸墊組120,13〇 印刷電路板40 13 1322296 底材200 晝素元件310 驅動晶片320 中央顯示區域200a 周邊佈線區域200b 晶片預留區塊210 晶片預留區塊之邊緣210a，210b，210c φ 第一組接觸墊230 訊號輸出線路232 第二組接觸墊240 訊號傳輸線路242 第三組接觸墊220 訊號輸入線路222 連接線路250 ® 測試墊 Al，A2, A3, A4, A5, A6 接觸墊B1，B3 訊號傳輸線路Cl, C2, C3, C4, C6 連接線路 252, 254a，254b，256, 258 訊號輸出線路D5The fourth A is a schematic view of the display panel of the present invention. 4B is an enlarged view showing the wiring of the peripheral wiring area of the fourth A diagram. FIG. 5 is a schematic diagram of the second preferred embodiment of the wiring system of the present invention. 7 is a schematic view of a line of the present invention. FIG. 4 is a schematic view of a preferred embodiment of the present invention. [Following the main components and symbols] The glass substrate 10 of the fifth preferred embodiment drives the wafers 22, 32, 42 Printed circuit board 20, 30 flexible printed circuit thin gland, 34, 44 wafer reserved block 11 〇 central display area 1 peripheral wiring area 10b glass substrate edge l〇c contact pad group 120, 13 〇 printed circuit board 40 13 1322296 Substrate 200 Cellular component 310 Driving wafer 320 Central display area 200a Peripheral wiring area 200b Wafer reserved block 210 Edge of chip reserved block 210a, 210b, 210c φ First set of contact pads 230 Signal output line 232 Two sets of contact pads 240 Signal transmission lines 242 Third set of contact pads 220 Signal input lines 222 Connection lines 250 ® Test pads Al, A2, A3, A4, A5, A6 Contact pads B1, B3 Signal transmission lines Cl, C2, C3, C4, C6 connection Road 252, 254a, 254b, 256, 258 signal output line D5