CN111650793B - Display panel and array substrate thereof - Google Patents
Display panel and array substrate thereof Download PDFInfo
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- CN111650793B CN111650793B CN202010598694.9A CN202010598694A CN111650793B CN 111650793 B CN111650793 B CN 111650793B CN 202010598694 A CN202010598694 A CN 202010598694A CN 111650793 B CN111650793 B CN 111650793B
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
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Abstract
The invention discloses a display panel and an array substrate thereof, wherein the array substrate comprises: the display area is provided with a pixel array and a plurality of data signal lines, and the pixel array comprises pixel units with different colors; the output pads and the input pads are used for binding a driving chip; the output bonding pad is connected with the data signal line through a fanout line, and the data signal line is connected with the pixel unit; the test circuit comprises a plurality of gating thin film transistors which are electrically connected, wherein the grid electrodes of the gating thin film transistors are connected with switch control signal lines, the source electrodes of the gating thin film transistors are connected with reference voltage lines, and the drain electrodes of the gating thin film transistors are connected with the output bonding pads. The technical scheme of the invention can complete the reliability test of the display panel based on the test circuit integrated in the array substrate.
Description
Technical Field
The invention relates to the technical field of display devices, in particular to a display panel and an array substrate thereof.
Background
Along with the continuous development of science and technology, more and more display devices are widely applied to daily life and work of people, bring great convenience to daily life and work of people, and become an indispensable important tool for people.
The main component of the display device for realizing the display function is a display panel. In an array substrate of a display panel, a frame area is provided with an output pad and an input pad, the output pad and the input pad are used for binding a driving chip (IC), and the driving chip is connected with pixel units in the display area of the display panel through fan-out lines connected with the output pad so as to drive the pixel units to display images. The driving chip is also connected with the flexible circuit board through the input bonding pad so as to be connected with a circuit main board of the display device.
Before the driving chip is bound, performance test is required to be performed on the display panel so as to ensure the reliability of the display panel and prevent the bad display panel from being bound with the driving chip after flowing into the subsequent process stage, thereby causing waste of expensive driving chips. Therefore, how to realize the performance test of the display panel is a problem to be solved in the field of display devices.
Disclosure of Invention
In view of this, the present application provides a display panel and an array substrate thereof, and the scheme is as follows:
an array substrate, the array substrate comprising:
a display area and a frame area;
the display area is provided with a pixel array and a plurality of data signal lines, and the pixel array comprises pixel units with different colors;
the output pads and the input pads are used for binding a driving chip; the output bonding pad is connected with the data signal line through a fanout line, and the data signal line is connected with the pixel unit;
the test circuit comprises a plurality of gating thin film transistors which are electrically connected, wherein the grid electrodes of the gating thin film transistors are connected with switch control signal lines, the source electrodes of the gating thin film transistors are connected with reference voltage lines, and the drain electrodes of the gating thin film transistors are connected with the output bonding pads;
the display device comprises an output pad, a display area, a gate thin film transistor, a switch control signal line, a gate thin film transistor and a display control circuit, wherein the switch control signal line is arranged on one side of the output pad, which is far away from the display area, and is connected with the output pad through the gate thin film transistor; and connecting the pixel units with the same color to the output pads connected with the same switch control signal line.
As can be seen from the above description, in the array substrate provided by the technical solution of the present invention, the frame area is provided with the output pad and the input pad for binding the driving chip, and the Test circuit is further provided with the Test circuit, which can perform performance Test on the display panel including the array substrate, for example, perform Visual Test (VT Test) to ensure reliability of the display panel.
The invention also provides a display panel, which comprises the array substrate.
As can be seen from the above description, the display panel provided by the technical solution of the present invention adopts the above-mentioned array substrate, and is provided with an output pad and an input pad for binding a driving chip in a frame area, and a Test circuit, which can perform a performance Test, such as a Visual Test (VT Test) for performing a display Test, on a display panel including the array substrate, so as to ensure reliability of the display panel.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the related art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described below, and it is apparent that the drawings in the following description are only embodiments of the present application, and other drawings may be obtained according to the provided drawings without inventive effort to those skilled in the art.
The structures, proportions, sizes, etc. shown in the drawings are shown only in connection with the present disclosure, and are not intended to limit the scope of the invention, since any modification, variation in proportions, or adjustment of the size, etc. of the structures, proportions, etc. should be considered as falling within the spirit and scope of the invention, without affecting the effect or achievement of the objective.
Fig. 1 is a schematic structural diagram of an array substrate according to an embodiment of the present invention;
FIG. 2 is an enlarged view of a portion of a frame region of the array substrate shown in FIG. 1;
FIG. 3 is a partial enlarged view of a frame area in an array substrate according to an embodiment of the present invention;
FIG. 4 is a partial enlarged view of a frame area of another array substrate according to an embodiment of the present invention;
FIG. 5 is a partial enlarged view of a frame region of an array substrate according to another embodiment of the present invention;
FIG. 6 is a partial enlarged view of a frame region of an array substrate according to another embodiment of the present invention;
FIG. 7 is a partial enlarged view of a frame region of an array substrate according to another embodiment of the present invention;
FIG. 8 is a partial enlarged view of a frame region of an array substrate according to another embodiment of the present invention;
FIG. 9 is a schematic structural diagram of another array substrate according to an embodiment of the present invention;
FIG. 10 is a partial enlarged view of the array substrate shown in FIG. 9;
fig. 11 is a schematic structural diagram of a display panel according to an embodiment of the invention.
Detailed Description
The following description of embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the described embodiments are only some, but not all embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.
In order that the above-recited objects, features and advantages of the present application will become more readily apparent, a more particular description of the invention briefly described above will be rendered by reference to specific embodiments that are illustrated in the appended drawings.
Referring to fig. 1 and fig. 2, fig. 1 is a schematic structural diagram of an array substrate according to an embodiment of the present invention, and fig. 2 is a partial enlarged view of a frame area in the array substrate shown in fig. 1. The array substrate includes: a display area AA and a frame area BB, wherein the display area AA is provided with a pixel array and a plurality of Data signal lines Data, and the pixel array comprises a plurality of pixel units P with different colors; a plurality of rows of output pads 11 and input pads 12 disposed in the frame area BB, wherein the output pads 11 and the input pads 12 are used for binding a driving chip, the output pads 11 are connected with the Data signal lines Data through fan-out lines 13, and the Data signal lines Data are connected with the pixel units P; a test circuit 14, the test circuit 14 includes a plurality of electrically connected gate thin film transistors 141, a gate of the gate thin film transistors 141 is connected to a switch control signal line 15, a source of the gate thin film transistors 141 is connected to a reference voltage line (not shown in fig. 1 and 2), and a drain of the gate thin film transistors 141 is connected to the output pad 11.
Wherein, a plurality of switch control signal lines 15 are arranged on one side of the output pad 11 away from the display area AA, and the switch control signal lines 15 are connected with the output pad 11 through the gating thin film transistor 141; for the output pads 11 connected to the same switch control signal line 15, the pixel units P of the same color are connected.
In the array substrate according to the embodiment of the present invention, the frame area BB is provided with the output pad 11 and the input pad 12 for binding the driving chip, and further provided with the test circuit 14, where the test circuit 14 can perform performance test on the display panel including the array substrate, so as to ensure reliability of the display panel.
The array substrate is used for a display panel, and the electronic equipment with the display panel is provided with a circuit main board. The input pads 12 are used for connecting with a flexible circuit board to connect with a circuit motherboard.
The array substrate has three pixel units P of different colors, and specifically, the pixel array has a first color pixel unit, a second color pixel unit and a third color pixel unit, where the first color pixel unit may be set to be a red pixel unit, the second color pixel unit may be set to be a green pixel unit, and the third color pixel unit may be set to be a blue pixel unit. Correspondingly, three output pads 11 are disposed in the frame area BB, and the three output pads 11 are a first output pad R, a second output pad G, and a third output pad B in this order.
As shown in fig. 2, in the first direction X, the 1 st row output pads 111 to the 3 rd row output pads 113 are sequentially provided; the 1 st row of output pads 111 has a plurality of first output pads R and third output pads B alternately arranged therein; the 2 nd row output pad 112 has a plurality of second output pads G therein; the 3 rd row output pad 113 has a plurality of first and third output pads R and B alternately arranged; the 1 st output pad 11 in the 1 st row output pads 111 is a first output pad R, and the 1 st output pad 11 in the 3 rd row output pads 113 is a third output pad B; the first direction X is a direction in which the input pad 11 points to the display area AA. The first output pad R is used for connecting the first color pixel unit, the second output pad G is used for connecting the second color pixel unit, and the third output pad B is used for connecting the third color pixel unit.
The gate thin film transistor 141 corresponding to the output pad 11 is connected to the corresponding switch control signal line 15 through a via hole 16. By setting the layout and distribution of the output pads 11 in each row, the pitch of two adjacent vias 16 in the same switch control signal line 15 can be adjusted, so as to facilitate adjusting the layout of the test circuit in the bonding area.
In the manner shown in fig. 2, there is at least one row of output pads 11, where the colors of the pixel units P connected to the output pads 11 in the row are not identical, for example, in the 1 st row of output pads 111, there are first output pads R and third output pads B that are alternately arranged, the two output pads 11 are respectively and correspondingly connected to the first color pixel unit and the third color pixel unit, in the 2 nd row of output pads 112, there are second output pads G that are respectively and correspondingly connected to the second color pixel unit, and in the 3 rd row of output pads 113, there are first output pads R and third output pads B that are alternately arranged, and the two output pads 11 are respectively and correspondingly connected to the first color pixel unit and the third color pixel unit.
As shown in fig. 3, fig. 3 is a partial enlarged view of a frame area in an array substrate according to an embodiment of the present invention, and the mode shown in fig. 3 is different from that shown in fig. 2 in that the same row of output pads 11 are the same in type and all connected to pixel units of the same color, for example, the 1 st row of output pads 111 are all first output pads R, the 2 nd row of output pads 112 are all second output pads G, and the 3 rd row of output pads 113 are all third output pads B.
As is clear from comparison between the modes shown in fig. 3 and 2, in the mode shown in fig. 2, the distances between two adjacent vias 16 in the three switch control signal lines 15 are gradually reduced in the first direction X, and in the mode shown in fig. 3, the distances between two adjacent vias 16 in the three switch control signal lines 15 are the same in the first direction X. In the manner shown in fig. 2 and 3, the length of the frame area occupied in the extending direction of the switch control signal line 15 is the same. The layout of the through holes on the two switch control signal lines 15 is different, and the two switch control signal lines can be suitable for binding areas with different shapes to set the through holes 16 connected with the test circuit 14.
As shown in fig. 2, the gate thin film transistor 141 is connected to the corresponding switch control signal line 15 through a via hole 16; in the first direction X, there are 3 switch control signal lines 15, and the 3 switch control signal lines 15 are a 1 st signal line 151 to a 3 rd signal line 153 in order; the thin film transistor 141 corresponding to the first output pad R is connected to the 1 st signal line 151, the gate thin film transistor 141 corresponding to the second output pad G is connected to the 2 nd signal line 142, and the gate thin film transistor 141 corresponding to the third output pad B is connected to the 3 rd signal line 143. In this way, in the first direction X, the distances between two adjacent vias 16 in the three switch control signal lines 15 gradually decrease, and the switch control signal lines 15 and the vias 16 above the same can be suitably arranged in a blank area adapted to the distance variation trend.
In the manner shown in fig. 2 and 3, for the gate thin film transistors 141 that need to be connected to the pixel units P through the output pads 11, the gate thin film transistors 141 and the vias 16 are in one-to-one correspondence, and each gate thin film transistor 141 is connected to the corresponding switch control signal line 15 through a separate via 16.
In other ways, for the gate thin film transistors 141 that need to be connected to the pixel unit P through the output pad 11, the same via hole 16 may be provided for every two gate thin film transistors 141, as shown in fig. 4 to 7.
As shown in fig. 4, fig. 4 is a partial enlarged view of a frame area in another array substrate according to an embodiment of the present invention, in this manner, a plurality of output pads 11 in the same row are sequentially from the 1 st output pad to the 2 nd output pad, and N is a positive integer greater than 1.
In the mode shown in fig. 4, the thin film transistor 141 connected to the 2i-1 th output pad in the 1 st row and the thin film transistor 141 connected to the 2 i-th output pad in the 3 rd row are connected to the 1 st signal line 151 through the same via 16, and the via 16 is the first via 161; i is a positive integer not greater than N; the thin film transistor 141 connected to the 2i-1 th output pad in the 2 nd row and the thin film transistor 141 connected to the 2 i-th output pad are connected to the 2 nd signal line 152 through the same via 16, and the via 16 is the second via 162; the thin film transistor 141 connected to the 2i-1 th output pad in the 3 rd row and the thin film transistor 141 connected to the 2 i-th output pad in the 1 st row are connected to the 3 rd signal line 153 through the same via 16, and the via 16 is the third via 163.
In the manner shown in fig. 4, 2N output pads 11 are in a row, and two adjacent same output pads 11 in different rows can share the same via hole 16 on the same switch control signal line 15, so that the number of via holes 16 can be reduced, and the length of the switch control signal line 15 can be reduced due to the reduced number of via holes 16, so that the occupied area of a binding region is reduced, and the circuit layout is facilitated.
In the embodiment shown in fig. 4, in the first direction X, the first via 161 is connected to the 1 st signal line 151, the second via 162 is connected to the 2 nd signal line 152, and the third via 163 is connected to the 3 rd signal line 153; the first via 161, the second via 162, and the third via 163 are positioned on the same straight line. This way the length of the switch control signal line 15 can be shortened to the greatest extent.
As shown in fig. 5, fig. 5 is a partial enlarged view of a frame area in another array substrate according to an embodiment of the present invention, in the manner shown in fig. 5, in the first direction X, the first via 161 is connected to the 1 st signal line 151, the second via 162 is connected to the 2 nd signal line 152, and the third via 163 is connected to the 3 rd signal line 153; unlike the embodiment shown in fig. 4, in the embodiment shown in fig. 5, the first via 161, the second via 162, and the third via 163 are arranged in a staggered manner, and the three are not aligned. This embodiment can also further shorten the length of the switch control signal line 15, as compared with the embodiment shown in fig. 2.
As shown in fig. 6, fig. 6 is a partial enlarged view of a border area in another array substrate provided in the embodiment of the present invention, the manner shown in fig. 6 is the same as that shown in fig. 5, the first via 161, the second via 162 and the third via 163 are arranged in a staggered manner, and the three are not in the same straight line, unlike the manner shown in fig. 5, in the manner shown in fig. 6, the 2 nd signal line 152 is a broken line, the second via 162 in the 2 nd signal line 152 translates towards the 3 rd signal line 153, a part of the protruding part of the third via 163 in the 3 rd signal line 153 is provided with the second via 162, the bent 2 nd signal line 152 translates along the first direction X, and then the 1 st signal line 151 translates along the first direction X, and the protruding part of the second via 162 in the 2 nd signal line 152 is provided with the first via 161, and the bent second signal line 152 can enable the switch control signal line 15 to be arranged in a staggered manner, thereby compressing the required width dimension of the switch control signal line 15, facilitating the circuit layout, and reducing the space utilization, and the occupied area of the circuit layout.
As shown in fig. 7, fig. 7 is a partial enlarged view of a frame area in another array substrate according to an embodiment of the present invention, based on the manner shown in fig. 6, in the manner shown in fig. 7, the 2 nd signal line 152 has a broken line structure, in the extending direction of the 2 nd signal line 152, the 2 nd signal line 152 has a plurality of first segments 21 and second segments 22 that are alternately arranged, and an extending block facing the 3 rd signal line 153 is arranged at a position corresponding to the second via 162, for arranging the second via 162; wherein, in the extending direction of the 2 nd signal line 152 (the direction perpendicular to the first direction X in fig. 7 and from left to right), the second segment 22 is located between the extending block corresponding to the 2j-1 th second via 162 and the extending block corresponding to the 2 j-th second via 162, and the second segment 22 is close to the 3 rd signal line 153 relative to the first segment 21, so as to form a convex structure facing the 3 rd signal line 153; j is a positive integer.
The 1 st signal line 151 and the 3 rd signal line 153 are both in a straight line structure, and the positions corresponding to the first via hole 161 and the third via hole 163 are provided with extension blocks facing the 2 nd signal line 152, the extension blocks corresponding to the positions of the first via hole 161 in the 1 st signal line 151 are used for arranging the first via hole 161, and the extension blocks corresponding to the positions of the third via hole 163 in the 3 rd signal line 153 are used for arranging the third via hole 163; the extension block corresponding to the 2j-1 th first via hole 161 in the 1 st signal line 151 and the extension block corresponding to the 2 j-th first via hole 161 are located in the j-th bump structure in the 2 nd signal line 152; the second segment 22 between the extension block corresponding to the 2j-1 th second via 162 and the extension block corresponding to the 2 j-th second via 162 in the 2 nd signal line 152 is in a j-th concave structure; the jth bump structure is located between the extension block corresponding to the 2j-1 th third via 163 and the extension block corresponding to the 2j-1 th third via 163 in the 3 rd signal line 153.
In the manner shown in fig. 7, a plurality of protruding structures facing the 3 rd signal line 153 may be formed on the 2 nd signal line 152, where the protruding structures are disposed at positions between the extending blocks of the 3 rd signal line and the 2 nd signal line 152 facing the adjacent two third vias 163, and the protruding structures are disposed at the extending blocks of the 1 st signal line 151 facing the first vias 161 in the 2 nd signal line 152, so that the bent second signal line 152 can enable the switch control signal line 15 to be arranged in a staggered manner, and therefore, a wiring space can be better utilized, a width of a frame area occupied by the switch control signal line 15 in the first direction can be reduced, an occupied area of a binding area is reduced, and circuit layout is facilitated.
As shown in fig. 8, fig. 8 is a partial enlarged view of a frame area in another array substrate according to an embodiment of the present invention, which is different from the manner shown in fig. 7 in that at least three consecutive first output pads R in the 1 st row of output pads 111 are connected to the same via hole 16 in the manner shown in fig. 8. In this embodiment, the same via hole 16 is connected to each pair of two gate thin film transistors 141 in the 2 nd signal line 152 and the 3 rd signal line 153. In the 1 st signal line 161, the same via hole 16 is connected to each eight pairs of gate thin film transistors 141, so that the number of first via holes 161 can be greatly reduced.
In the array substrate of the embodiment of the present invention, the pixel units P having M different colors may be disposed; m is a positive integer greater than 1; for example, m=3, there are three different color pixel units P, which may be a red pixel unit, a green pixel unit, and a red pixel unit, respectively, or m=4, there are four different pixel units P, which may be a red pixel unit, a green pixel unit, a red pixel unit, and a white pixel unit, respectively, or the four pixel units P may be a red pixel unit, a green pixel unit, a red pixel unit, and a yellow pixel unit, respectively, or the like. The value of M and the type of the pixel unit P may be set based on the display driving manner, which is not particularly limited in the embodiment of the present invention.
In the first direction X, there are m+1 switch control signal lines 15, where the m+1 switch control signal lines 15 are sequentially from the 1 st signal line to the m+1 st signal line, there are m+1 rows of output pads 11, and the m+1 rows of output pads are sequentially from the 1 st row of output pads to the m+1 th row of output pads; the first direction X is a direction in which the input pad 11 points to the display area AA; in the first direction X, the m+1th row of output pads includes a plurality of touch pads TP for connecting with touch electrodes, and the 1 st to M signal lines sequentially arranged are used for connecting with the pixel units P through the previous M rows of output pads, and the m+1th signal line is used for connecting with the m+1th row of output pads.
In the array substrate according to the embodiment of the present invention, as shown in fig. 1, the input pad 12 is located at a side of the output pad 11 facing away from the display area AA. Specifically, the frame area BB has a first binding area 001 and a second binding area 002, the output pads 11 are all located in the first binding area 001, the input pads 12 are all located in the second binding area 002, and the test circuit 14 is located in a gap area between the first binding area 001 and the second binding area 002.
In the manner shown in fig. 1, in the first binding region 001, in the same row, a plurality of output pads 11 are arranged in a straight line. The number of the output pads 11 is large, and in order to reduce the length of the first bonding region 001 occupied by the output pads 11, the structure of the array substrate may be provided as shown in fig. 9 and 10.
As shown in fig. 9 and 10, fig. 9 is a schematic structural diagram of another array substrate according to an embodiment of the present invention, and fig. 10 is a partial enlarged view of the array substrate shown in fig. 9. The manner shown in fig. 9 is different from the foregoing embodiments in that the frame area BB has a first binding area 001, the output pads 11 are all located in the first binding area 001, and the manner shown in fig. 9 is different from the foregoing embodiments in that, in the extending direction of the switch control signal line 15, the first binding area 001 has a first area 31, a second area 32, and a third area 33 sequentially arranged, the first area 31 and the third area 33 are both bent away from the display area AA, and the second area 32 is parallel to the extending direction.
In the manner shown in fig. 9 and 10, the first binding region 001 for setting the output pad 11 is divided into three regions, and the first region 31 and the third region 33 disposed at both ends are bent away from the direction of the display region AA, so that the length of the first binding region 001 can be shortened. The included angle θ between the first region 31 and the third region 33 and the line where the output pad 12 is located may be set based on requirements, which is not particularly limited in the embodiment of the present invention.
Because of the test requirement, in the display panel, the test circuit 14 needs to be disposed below the output pad 11, generally between the output pad 11 and the input pad 12, and if the first bonding region 001 is simply bent, the length of the first bonding region 001 is shortened, but the length of a gap region between the first bonding region 001 and the second bonding region 002 is reduced, and there is insufficient space for disposing the test circuit 14. If the test circuit 14 is not provided, the test signals of the data signal lines correspondingly connected to the corresponding output pads 11 and the test signals of the touch signal lines correspondingly connected to the touch electrodes cannot be detected in the VT test stage, and then the connection states of the data signal lines and the touch signal lines cannot be detected, so that whether the data signal lines and the touch signal lines are bad or not is determined, the defective rate of the array substrate is increased, and if components such as a polarizer, a driving control chip and a flexible circuit board are bound on the defective array substrate, the components are lost, and the manufacturing cost is increased. By adopting the technical scheme of the embodiment of the invention, the length of the switch control signal line 15 can be shortened by adjusting the layout of the through holes 16 on the switch control signal line 15 so as to adapt to the problem of shortening the gap between the first binding region 001 and the second binding region 002 caused by bending of the first binding region 001 in the embodiment shown in fig. 9 and 10, and the test circuit 14 can be arranged in a smaller space while shortening the length of the first binding region 001, thereby being convenient for circuit layout.
Based on the above embodiment, another embodiment of the present invention further provides a display panel, where the display panel is shown in fig. 11, and fig. 11 is a schematic structural diagram of the display panel according to the embodiment of the present invention, where the display panel includes the array substrate described in the above embodiment.
The display panel can be an LCD display panel or an OLED display panel and is used for electronic devices such as mobile phones, tablet computers, intelligent wearable devices and the like. The reliability test of the display panel can be completed through a test circuit integrated by the array substrate in the display panel.
In the present specification, each embodiment is described in a progressive manner, or a parallel manner, or a combination of progressive and parallel manners, and each embodiment is mainly described as a difference from other embodiments, and identical and similar parts between the embodiments are all enough to refer to each other. For the display panel disclosed in the embodiment, the description is relatively simple because it corresponds to the array substrate disclosed in the embodiment, and the relevant points refer to the description of the method section.
It should be noted that, in the description of the present invention, it should be understood that the directions or positional relationships indicated by the terms "upper", "lower", "top", "bottom", "inner", "outer", etc. are based on the directions or positional relationships shown in the drawings, are merely for convenience of describing the present invention and simplifying the description, and do not indicate or imply that the devices or elements to be referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present invention. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present.
It is further noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that an article or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such article or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in an article or apparatus that comprises such element.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (13)
1. An array substrate, characterized in that the array substrate comprises:
a display area and a frame area;
the display area is provided with a pixel array and a plurality of data signal lines, and the pixel array comprises pixel units with different colors;
the output pads and the input pads are used for binding a driving chip; the output bonding pad is connected with the data signal line through a fanout line, and the data signal line is connected with the pixel unit;
the test circuit comprises a plurality of gating thin film transistors which are electrically connected, wherein the grid electrodes of the gating thin film transistors are connected with switch control signal lines, the source electrodes of the gating thin film transistors are connected with reference voltage lines, and the drain electrodes of the gating thin film transistors are connected with the output bonding pads;
the display device comprises an output pad, a display area, a gate thin film transistor, a switch control signal line, a gate thin film transistor and a display control circuit, wherein the switch control signal line is arranged on one side of the output pad, which is far away from the display area, and is connected with the output pad through the gate thin film transistor; for the output pads connected with the same switch control signal line, connecting the pixel units with the same color;
the input bonding pad is positioned at one side of the output bonding pad away from the display area; the frame area is provided with a first binding area and a second binding area, the output bonding pads are all positioned in the first binding area, the input bonding pads are all positioned in the second binding area, and the test circuit is positioned in a gap area between the first binding area and the second binding area;
on the extending direction of the switch control signal line, the first binding area is provided with a first area, a second area and a third area which are sequentially arranged, the first area and the third area are bent away from the display area, and the second area is parallel to the extending direction.
2. The array substrate of claim 1, wherein the pixel array has a first color pixel cell, a second color pixel cell, and a third color pixel cell;
in the first direction, the 1 st row output bonding pad to the 3 rd row output bonding pad are sequentially arranged; the 1 st row of output pads are provided with a plurality of first output pads and third output pads which are alternately arranged; the 2 nd row of output pads are provided with a plurality of second output pads; the 3 rd row of output pads are provided with a plurality of first output pads and third output pads which are alternately arranged; the 1 st output pad in the 1 st output pad is a first output pad, and the 1 st output pad in the 3 rd output pad is a third output pad; the first direction is the direction in which the input pad points to the display area;
the first output pad is used for being connected with the first color pixel unit, the second output pad is used for being connected with the second color pixel unit, and the third output pad is used for being connected with the third color pixel unit.
3. The array substrate of claim 2, wherein the gate thin film transistor is connected to the corresponding switch control signal line through a via hole;
in the first direction, 3 switch control signal lines are provided, and the 3 switch control signal lines are sequentially from the 1 st signal line to the 3 rd signal line; the thin film transistor corresponding to the first output bonding pad is connected with the 1 st signal line, the gating thin film transistor corresponding to the second output bonding pad is connected with the 2 nd signal line, and the gating thin film transistor corresponding to the third output bonding pad is connected with the 3 rd signal line.
4. The array substrate of claim 3, wherein each of the gate thin film transistors is connected to the corresponding switch control signal line through a separate via hole.
5. The array substrate of claim 3, wherein the plurality of output pads of the same row are sequentially 1 st output pad to 2 nth output pad, N being a positive integer greater than 1;
the thin film transistor connected with the 2i-1 output pad in the 1 st row and the thin film transistor connected with the 2i output pad in the 3 rd row are connected with the 1 st signal line through the same via hole, and the via hole is a first via hole; i is a positive integer not greater than N;
the thin film transistor connected with the 2i-1 th output pad in the 2 nd row is connected with the 2 nd signal line through the same via hole, and the via hole is a second via hole;
the thin film transistor connected with the 2i-1 output pad in the 3 rd row and the thin film transistor connected with the 2i output pad in the 1 st row are connected with the 3 rd signal line through the same via hole, and the via hole is a third via hole.
6. The array substrate of claim 5, wherein in the first direction, the first via is connected to the 1 st signal line, the second via is connected to the 2 nd signal line, and the third via is connected to the 3 rd signal line; the first via hole, the second via hole and the third via hole are positioned on the same straight line.
7. The array substrate of claim 5, wherein in the first direction, the first via is connected to the 1 st signal line, the second via is connected to the 2 nd signal line, and the third via is connected to the 3 rd signal line; the first via, the second via, and the third via are not collinear.
8. The array substrate of claim 7, wherein the 2 nd signal line has a zigzag structure, and in the extending direction of the 2 nd signal line, the 2 nd signal line has a plurality of first segments and second segments alternately arranged, and an extending block facing the 3 rd signal line is arranged at a position corresponding to the second via hole; in the extending direction of the 2 nd signal line, the second segment is located between the extending block corresponding to the 2j-1 th second via hole and the extending block corresponding to the 2j-1 nd second via hole, and the second segment is close to the 3 rd signal line relative to the first segment so as to form a protruding structure facing the 3 rd signal line; j is a positive integer;
the 1 st signal line and the 3 rd signal line are of straight structures, and the positions corresponding to the first through hole and the third through hole are provided with extension blocks facing the 2 nd signal line; the extension block corresponding to the 2j-1 th first through hole in the 1 st signal line and the extension block corresponding to the 2 j-th first through hole are positioned in the j-th protruding structure in the 2 nd signal line; a second section between the extension block corresponding to the 2j-1 th second through hole and the extension block corresponding to the 2j-1 nd second through hole in the 2 nd signal line is a j-th protruding structure; the jth protruding structure is located between the extension block corresponding to the 2j-1 th third via hole and the extension block corresponding to the 2j-1 th third via hole in the 3 rd signal line.
9. The array substrate of claim 3, wherein at least three consecutive first output pads of row 1 output pads are connected to the same via.
10. The array substrate according to claim 1, wherein there are M kinds of the pixel units having different colors; m is a positive integer greater than 1;
in the first direction, the M+1 switch control signal lines are arranged, the M+1 switch control signal lines are sequentially from the 1 st signal line to the M+1 st signal line, M+1 rows of output pads are arranged, and the M+1 rows of output pads are sequentially from the 1 st row of output pads to the M+1 th row of output pads; the first direction is the direction in which the input pad points to the display area;
in the first direction, the (M+1) -th row output pad comprises a touch pad for connecting with a touch electrode, and the (1) -th signal line to the (M) -th signal line which are sequentially arranged are used for being connected with the pixel unit through the front M-th row output pad, and the (M+1) -th signal line is used for being connected with the (M+1) -th row output pad.
11. The array substrate of claim 1, wherein the input pads are used to connect to a flexible circuit board for connection to a circuit motherboard.
12. The array substrate of claim 1, wherein there is at least one row of the output pads, and the pixel cells connected to the row of the output pads are not identical in color.
13. A display panel comprising an array substrate according to any one of claims 1-12.
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| CN112133241B (en) * | 2020-10-29 | 2022-09-13 | 武汉天马微电子有限公司 | Chip on film, display panel and display device |
| CN115273653A (en) * | 2021-04-29 | 2022-11-01 | 群创光电股份有限公司 | Display device |
| CN113506530A (en) * | 2021-07-06 | 2021-10-15 | 友达光电（昆山）有限公司 | Display panel and display device |
| CN113675221A (en) * | 2021-08-18 | 2021-11-19 | 惠科股份有限公司 | Display panel driving device, driving circuit and display device |
| CN116710992A (en) * | 2021-11-29 | 2023-09-05 | 京东方科技集团股份有限公司 | Display panel and display device |
| CN117542292B (en) * | 2024-01-10 | 2024-04-02 | 长春希龙显示技术有限公司 | Display module with left and right visual angle color consistency and processing method thereof |
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| KR20080049912A (en) * | 2006-12-01 | 2008-06-05 | 엘지디스플레이 주식회사 | Driving ic and display apparatus having the same |
| JP2012118099A (en) * | 2010-11-29 | 2012-06-21 | Optrex Corp | Driver element for driving and display device |
| CN105676497A (en) * | 2016-04-21 | 2016-06-15 | 深圳市华星光电技术有限公司 | Panel test circuit and liquid crystal display panel |
| KR102503732B1 (en) * | 2017-11-30 | 2023-02-27 | 삼성디스플레이 주식회사 | Display apparatus |
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| CN111180464B (en) * | 2020-01-03 | 2021-12-03 | 京东方科技集团股份有限公司 | Array substrate, preparation method thereof, display panel and display device |
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