CN1835195A - 具有层合晶穴的半导体封装构造的制造方法 - Google Patents
具有层合晶穴的半导体封装构造的制造方法 Download PDFInfo
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Abstract
本发明公开了一种具有层合晶穴的半导体封装构造的制造方法,提供有一板材以及一形成有一接着树脂层的金属箔;该金属箔层合于该板材,以使该接着树脂层黏接该板材;接着,形成一贯通口,其贯穿该板材、该接着树脂层与该金属箔;在移除该金属箔之后,该接着树脂层的另一接着面将显露在该板材上,以供贴附于一载板,形成一晶穴。
Description
技术领域
本发明是关于半导体封装的制造,特别是有关于一种具有层合晶穴的半导体封装构造的制造方法。
背景技术
公知在半导体封装与半导体模组领域中,一包含有基板的芯片载体设计有一晶穴(die-cavity),用以容置一芯片,该晶穴包含有一晶穴侧壁及一芯片接合区,为了易于控制晶穴侧壁的高度与芯片接合区的平坦度,该晶穴侧壁与该芯片接合区分别先制作在两不同基板,再以黏胶层将具有该晶穴侧壁的基板与具有该芯片接合区的基板相互黏着组合,以构成一具有晶穴的堆叠基板组合件。如美国专利第6,506,626号与美国专利公开编号第2001/0046725号所揭示,该具有芯片接合区的基板为一球格阵列封装的板材,而该具有晶穴侧壁的基板为一金属加劲环(metal stiffener)或一间隔电路板,两基板能组配成具有晶穴的基板组合件,以供制作晶穴朝上的半导体封装构造或模组。再如美国专利6,639,304号与美国专利第6,501,168号所揭示,该具有芯片接合区的基板为一散热金属片(metal plate或metal core),而该具有晶穴侧壁的基板为一具有开孔或一窗口的板材,以供制作晶穴朝下的半导体封装构造或模组。
常见用于黏着上述两基板的黏胶层为压克力膜(acrylate film)、液胶(liquidadhesive)或预浸材(prepreg),其中例如压克力膜或预浸材(prepreg)的黏性胶片需要预先冲压或铣切出一窗口,再将该具有窗口的黏性胶片黏贴对位至该具有芯片接合区的基板,但由于该黏性胶片具有黏性,因此在制程中会有黏着于治具或黏着粉尘等问题,而造成制程上处理困扰或不易黏着,其中,压克力膜对湿气相当敏感,通常只能到达JEDEC第四级抗湿性,另,预浸材在铣切或冲压的成孔过程中相当容易被损伤且会形成大量树脂薄片(resin flake)或尘埃粒子。
此外,当以液态黏胶层黏着上述两基板,公知该液态黏胶层先以网版印刷(screen printing)形成在该具有晶穴侧壁的基板或是具有芯片接合区的基板,为了不在压合黏着时造成该液态黏胶层流动至该晶穴侧壁,该液态黏胶层必须具有相当高黏度与适当的表面张力。若该液态黏胶层包含有溶剂,通常该液态黏胶层在印刷后需要预烤或干燥,再施压结合两基板并升温加以固化。制程中的条件控制相当严苛,稍有不慎,该液态黏胶层将被挤迫至该晶穴侧壁或该芯片接合区,导致污染基板焊垫并影响芯片在晶穴内的平坦结合。
美国专利第6,195,264号揭示有一种基板的晶穴形成方法,将一光感性物质(photoimageable material)的黏胶层介设在一金属加劲环与一电路板之间,在压合后构成一具有晶穴的基板,该光感性物质被曝光显影已使得在晶穴内不会残留该光感性物质的黏胶层,该黏胶层应被要求同时具备良好易于曝光处理的光感性、热固性、黏着性与导热性,故此一特殊性能的材料取得不容易且成本甚高。
发明内容
本发明的主要目的在于提供一种具有层合晶穴的半导体封装构造的制造方法,首先提供一板材并提供一形成有一接着树脂层的金属箔,将两者加以层合,以使得该接着树脂层黏黏接该板材,再形成一贯通口,该贯通口贯穿该板材、该接着树脂层与该金属箔,该贯通口使该板材具有一晶穴侧壁,再移除该金属箔,以显露该接着树脂层在该板材上,可再黏着至一载板,以形成一晶穴,该接着树脂层不会溢流至该晶穴内并且无碎片(flaking)发生而能减少对该晶穴的污染,亦有具有低温黏着该板材与该载板的功效。
本发明的次一目的在于提供一种具有层合晶穴的半导体封装构造的制造方法,利用一金属箔作为一接着树脂层的承载件,在层合步骤与贯通口形成步骤中可以降低对治具的污染并能转变黏接至一板材,再以该具有黏性的板材贴附至一载板,以得到一深度准确且无黏着剂残留的晶穴,以达到高品质的半导体封装。
依本发明的具有层合晶穴的半导体封装构造的制造方法,分别提供一板材以及一金属箔,该板材的一表面定义有至少一用以形成晶穴侧壁的区域,该金属箔的一表面形成有一接着树脂层,该接着树脂层具有一第一接着面以及一第二接着面,该第一接着面贴附于该金属箔,该第二接着面呈显露。之后,将该板材与该金属箔加以层合,使得该接着树脂层的该第二接着面黏接该板材。之后,在对应于该形成晶穴侧壁的区域形成一贯通口,该贯通口可以铣切(routing)或冲压(punching)等方式形成,该贯通口贯穿该板材、该接着树脂层与该金属箔,使得该板材具有一在该贯通口内的晶穴侧壁。之后,移除该金属箔,以显露该接着树脂层的该第一接着面。之后,将该板材贴附至一载板,使得该接着树脂层的该第一接着面黏接该载板。之后,可将一芯片设置于该载板上且位于该板材的贯通口内。故能低成本地制作晶穴朝上或晶穴朝下的半导体封装构造。
附图说明
图1A至1J是依据本发明的第一具体实施例,一板材在一半导体封装制程中的截面示意图;
图2是依据本发明的第一具体实施例,一板材在层合后形成预切孔的立体示意图;
图3是依据本发明的第一具体实施例,一板材在层合后形成贯通口的立体示意图;及
图4A至4I是依据本发明的第二具体实施例,一板材在另一半导体封装制程中的截面示意图。
附图标记说明:
110板材(board) 111第一表面 112第二表面
113用以形成晶穴侧壁的区域 114导接指 115球垫
116晶穴侧壁 120金属箔 130接着树脂层
131第一接着面 132第二接着面 140贯通口
141预切孔 142金属覆盖层 150载板(carrier plate)
151晶穴的芯片接合区 160芯片 161焊垫
170焊线 180封胶体 190焊球
210板材 211用以形成晶穴侧壁的区域 212晶穴侧壁
220金属箔 230接着树脂层 231第一接着面
232第二接着面 240贯通口 250载板
251晶穴的芯片接合区 260芯片 270焊线
280透光盖 290焊球
具体实施方式
参阅附图,本发明将列举以下的实施例说明。
依据本发明第一具体实施例的具有层合晶穴的半导体封装构造的制造方法,请参阅图1A,首先,提供一板材110以及提供一已形成有一接着树脂层130的金属箔120,该板材110具有一第一表面111及一对应的第二表面112,且该板材110定义有至少一用以形成晶穴侧壁的区域113。在本实施例中,该板材110为一种具有电路图案以适用于晶穴朝下封装的基板,常见地该板材110为包含BT树脂的印刷电路板,该第一表面111用以黏附一载板150(如图1F所示),该第二表面112形成有复数个用以连接焊线的导接指114以及复数个用以连接焊球的球垫115。通常在该板材110的该第一表面111可以不用涂施任何黏着材料。
该金属箔120以易被蚀刻的金属材质为较佳,例如铜箔。并且该接着树脂层130可利用例如印刷或浸涂等方式形成在该金属箔120的其中一表面,经过适当的些许烘烤。该接着树脂层130具有一第一黏着面131以及一第二黏着面132,该第一黏着面131贴附于该金属箔120且该第二黏着面132呈显露。该接着树脂层130应具有多阶固化性质,其材质可选自于环氧基树脂、BT(Bismaleimide Triazine,双顺丁烯二酸酰亚胺)树脂与PI(Polyimide,聚酰亚胺)树脂的其中之一,亦可以是包含有玻璃纤维的预浸材(prepreg),较佳地,该接着树脂层130包含有金属粒子,例如银粒子,以增进该接着树脂层130的导热。其中,该接着树脂层130为一背胶铜箔(Resin Coated Copper foil,RCC),且能以低成本的大量生产。
接着,请参阅图1B,层合(laminating)该板材110与该金属箔120,藉由该接着树脂层130的该第二黏着面132能低温黏接该板材110的该第一表面111,以组成一层合件。较佳地,该接着树脂层130被固化至5-50%之间,其中,又以稍为被固化至5-15%之间尤为佳,在层合步骤中该接着树脂层130被部分固化(partially cured)。在层合(laminating)该板材110与该金属箔120之后,该接着树脂层130经由该金属箔120压迫且具有一致的厚度,其可减少粒子的产生与溢胶污染,故容易加工处理,不会沾附于治具。
之后,请参阅图1C及3,以铣切(routing)或其它方式对该金属箔120、该接着树脂层130与该板材110所组成的层合件形成一贯通口140。请参阅图2,在形成该贯通口140之前,其可预先形成至少一预切孔141(pre-cutting hole),该预切孔141贯通该板材110、该接着树脂层130与该金属箔120,较佳地,该预切孔141位于该区域113的一角隅,以利铣切刀具(图未绘出)的铣切。在铣切形成该贯通口140之后,该贯通口140对应于该形成晶穴侧壁的区域113,并且贯穿该板材110、该接着树脂层130与该金属箔120,使得该板材110具有一位在该贯通口140内的晶穴侧壁116。
请参阅图1D,在该贯通口140形成之后,可以选择性的执行或不执行一遮盖步骤(shielding step),若有需要,可利用电镀或溅镀技术将一例如镍/金的金属覆盖层142形成在该板材110的该晶穴侧壁116,以电性遮蔽一晶穴内芯片160与该板材110的内部电路图案(如图1J所示)。当该金属覆盖层142以电镀形成时,该金属箔120可提供一电镀导通路径。
之后,请参阅图1E,该金属箔120应该被移除,以显露该接着树脂层130的该第一黏着面131。其中移除该金属箔120的方式可以是蚀刻(etching)或剥离(peeling)等。因此,该接着树脂层130以层合方式由该金属箔120转移至该板材110的该第一表面111,再经过上述的贯通口140形成步骤,故该接着树脂层130不会沾附至该板材110的晶穴侧壁116,并且将使得该板材110的第一表面111具有黏性。此外,当该接着树脂层130是以蚀刻(etching)去除时,该金属覆盖层142更可以保护该板材110的内部电路图案不被蚀除。
之后,请参阅图1F,该板材110贴附至一载板150,使得该接着树脂层130的该第一接着面131黏接该载板150。该载板150具有一晶穴的芯片接合区151,其显露于该贯通口140,而与该板材110的晶穴侧壁116组合以形成一晶穴(chipcavity)。请再参阅图1F,上述晶穴的深度与形状能被准确定义,且该芯片接合区151可为高度平坦,以供高品质的半导体封装所用。此外,该接着树脂层130不会溢胶沾附至该晶穴侧壁116与该芯片接合区151,并且不会有公知黏性胶片需要对位的问题。在本实施例中,该具有芯片接合区151的载板150为一散热片。
之后,请参阅图1G,一半导体芯片160贴设于该载板150的芯片接合区151且在该板材110的晶穴侧壁116(即该贯通口140)内。之后,在本具体实施例中,另包含有一打线连接步骤,请参阅图1H,将复数个焊线170连接该半导体芯片160的复数个焊垫161与该板材110的该些导接指114。之后,在本具体实施例中,更包含有一封胶步骤,请参阅图1I,利用压模(molding)或是点胶(dispensing)方式将一封胶体180形成在该晶穴侧壁116与该芯片接合区151所构成的晶穴中,以密封该芯片160与该些焊线170。之后,在本具体实施例中,更包含有一外接端形成步骤,请参阅图1J,可将复数个焊球190设置在该板材110第二表面112的该些球垫115上,以构成一晶穴朝下的半导体封装构造。该接着树脂层130可完全固化在晶穴形成之后或是在该封胶体180形成之后。
因此,在上述的半导体封装构造的制造方法中,该接着树脂层130不会溢出至该晶穴的晶穴侧壁116与芯片接合区151并且无碎片(flaking)的发生。此外,当该板材110的该第一表面111具有不平坦的凸点或凹陷,可以与该金属箔120的层合步骤中,被该接着树脂层130补偿与修正。
此外,本发明的具有层合晶穴的半导体封装构造的制造方法可运用在制作不同封装型态的半导体封装构造,例如晶穴朝上的影像传感器芯片封装构造。如本发明的第二具体实施例所揭示,请参阅图4A,首先,提供一板材210并提供一形成有一接着树脂层230的一金属箔220,其中,该板材210具有一第一表面211及一对应的第二表面212,在本实施例中,该板材210为一基板核心层(substrate core),其为一含浸树脂的玻璃纤维布。该板材210定义有至少一用以形成晶穴侧壁的区域211。该接着树脂层230仅形成于该金属箔220的其中一表面。该接着树脂层230具有一第一接着面231以及一第二接着面232,该第一接着面231贴附于该金属箔220,而该第二接着面232呈显露。
之后,请参阅图4B,令该金属箔220与该板材210相互层合,该接着树脂层230的该第二接着面232黏接该板材210的该第一表面211,以组成一层合件。较佳地,该金属箔220可供形成该接着树脂层230的表面为平坦且光滑。
之后,请参阅图4C,以冲压(punching)方式对上述该板材210、一金属箔220与该接着树脂层230所组成的层合件形成一贯通口240,该贯通口240对应于该区域313而贯穿该板材210、该接着树脂层230与该金属箔220,使得该板材210具有一晶穴侧壁212,该晶穴侧壁212位在该贯通口240内。
之后,请参阅图4D,以剥离(peeling)或蚀刻等方式移除该金属箔220,以显露该接着树脂层230的第一接着面231。接下来,请参阅图4E,该具有贯通口240的板材210贴附至一载板250,使得该接着树脂层230的该第一接着面231黏接该载板250。该载板250具有一晶穴的芯片接合区251,而与该板材210的晶穴侧壁212组合以形成一晶穴(chip cavity)。在本实施例中,该载板250为一具有电路图案的基板。
之后,请参阅图4F,一例如影像传感器芯片的半导体芯片260贴设于该载板250的芯片接合区251且在该板材210的晶穴侧壁212(即该贯通口240)内。之后,在本具体实施例中,请参阅图4G,利用打线形成的复数个焊线270电性连接该半导体芯片260与该载板250。之后,在本具体实施例中,更包含有一密封步骤,请参阅图4H,将一例如玻璃材质的透光盖280设置于该板材210上,以气闭密封该芯片260,或者是以一透明封胶体形成在该晶穴侧壁212与该芯片接合区251所构成的晶穴中(图未绘出)。之后,在本具体实施例中,更包含有一外接端形成步骤,请参阅图4I,可将复数个焊球290设置在该载板250的一下表面,以构成一晶穴朝上的半导体封装构造。
因此,在上述实施例中的半导体封装构造的制造方法中,由该板材210的该晶穴侧壁212与该载板250的芯片接合区251所构成的晶穴有良好的清洁度,并且在黏晶于该晶穴之后,该半导体芯片260的主动面具有良好的水平度与控制准确的高度,以提升封装后影像感测品质。
本发明的保护范围当视申请专利范围所界定者为准,任何熟知此项技艺者,在不脱离本发明的精神和范围内所作的任何变化与修改,均属于本发明的保护范围。
Claims (22)
1、一种具有层合晶穴的半导体封装构造的制造方法,包含:
提供一板材,该板材定义有至少一用以形成晶穴侧壁的区域;
提供一金属箔,该金属箔的一表面形成有一接着树脂层,该接着树脂层具有一第一接着面以及一第二接着面,该第一接着面贴附于该金属箔,该第二接着面呈显露;
层合该板材与该金属箔,使得该接着树脂层的该第二接着面黏接该板材;
在对应于该形成晶穴侧壁的区域形成一贯通口,该贯通口贯穿该板材、该接着树脂层与该金属箔,使得该板材具有一在该贯通口内的晶穴侧壁;
移除该金属箔,以显露该接着树脂层的该第一接着面;
贴附该板材与一载板,使得该接着树脂层的该第一接着面黏接该载板;及
设置一芯片于该载板且位于该板材的该晶穴侧壁内。
2、如权利要求1所述的半导体封装构造的制造方法,其特征是,在移除该金属箔之前,另包含:形成一金属覆盖层于该板材的该晶穴侧壁。
3、如权利要求1所述的半导体封装构造的制造方法,其特征是,该接着树脂层具有多阶固化性质。
4、如权利要求3所述的半导体封装构造的制造方法,其特征是,在黏接该载板之后,该接着树脂层被固化5-50%。
5、如权利要求1所述的半导体封装构造的制造方法,其特征是,该接着树脂层选自于环氧基树脂、BT树脂与PI树脂的其中之一。
6、如权利要求1所述的半导体封装构造的制造方法,其特征是,该接着树脂层包含有金属粒子。
7、如权利要求1所述的半导体封装构造的制造方法,其特征是,该金属箔是以蚀刻方式移除。
8、如权利要求1所述的半导体封装构造的制造方法,其特征是,该金属箔是以剥离方式移除。
9、如权利要求1所述的半导体封装构造的制造方法,其特征是,该贯通口是以冲压方式形成。
10、如权利要求1所述的半导体封装构造的制造方法,其特征是,该贯通口是以铣切方式形成。
11、如权利要求1所述的半导体封装构造的制造方法,其特征是,该板材为一具有电路图案的基板。
12、如权利要求11所述的半导体封装构造的制造方法,其特征是,该载板为一散热片。
13、如权利要求11所述的半导体封装构造的制造方法,其特征是,另包含的步骤有:打线连接该芯片与该板材。
14、如权利要求11所述的半导体封装构造的制造方法,其特征是,另包含的步骤有:形成一封胶体于该板材的贯通口内。
15、如权利要求11所述的半导体封装构造的制造方法,其特征是,另包含的步骤有:设置多个焊球于该板材。
16、如权利要求1所述的半导体封装构造的制造方法,其特征是,该载板为一具有电路图案的基板。
17、如权利要求16所述的半导体封装构造的制造方法,其特征是,该板材为一基板核心层。
18、如权利要求16所述的半导体封装构造的制造方法,其特征是,另包含的步骤有:打线连接该芯片与该载板。
19、如权利要求16所述的半导体封装构造的制造方法,其特征是,另包含:形成一封胶体于该板材的贯通口内。
20、如权利要求16所述的半导体封装构造的制造方法,其特征是,另包含:设置一透光盖于该板材上,以气闭密封该芯片。
21、如权利要求16所述的半导体封装构造的制造方法,其特征是,另包含:设置多个焊球于该载板。
22、如权利要求16所述的半导体封装构造的制造方法,其特征是,该形成有接着树脂层的金属箔为一背胶铜箔。
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102254880A (zh) * | 2010-05-21 | 2011-11-23 | 南茂科技股份有限公司 | 芯片封装装置及其制造方法 |
CN102479763A (zh) * | 2010-11-22 | 2012-05-30 | 钰桥半导体股份有限公司 | 一种散热增益型堆叠式半导体组件 |
Families Citing this family (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7763963B2 (en) | 2005-05-04 | 2010-07-27 | Stats Chippac Ltd. | Stacked package semiconductor module having packages stacked in a cavity in the module substrate |
US7528474B2 (en) * | 2005-05-31 | 2009-05-05 | Stats Chippac Ltd. | Stacked semiconductor package assembly having hollowed substrate |
TW200735340A (en) * | 2006-03-10 | 2007-09-16 | Advanced Semiconductor Eng | Image sensor package and method for manufacturing the same |
JP2008016630A (ja) * | 2006-07-06 | 2008-01-24 | Matsushita Electric Ind Co Ltd | プリント配線板およびその製造方法 |
TWI353661B (en) * | 2007-04-09 | 2011-12-01 | Unimicron Technology Corp | Circuit board structure capable of embedding semic |
US7847387B2 (en) * | 2007-11-16 | 2010-12-07 | Infineon Technologies Ag | Electrical device and method |
US8048708B2 (en) * | 2008-06-25 | 2011-11-01 | Micron Technology, Inc. | Method and apparatus providing an imager module with a permanent carrier |
US7989950B2 (en) * | 2008-08-14 | 2011-08-02 | Stats Chippac Ltd. | Integrated circuit packaging system having a cavity |
US8119454B2 (en) * | 2008-12-08 | 2012-02-21 | Stmicroelectronics Asia Pacific Pte Ltd. | Manufacturing fan-out wafer level packaging |
CN102201348A (zh) * | 2010-03-26 | 2011-09-28 | 力成科技股份有限公司 | 阵列切割式四方扁平无引脚封装方法 |
US20120081872A1 (en) * | 2010-09-30 | 2012-04-05 | Alcatel-Lucent Canada Inc. | Thermal warp compensation ic package |
TWI735525B (zh) * | 2016-01-31 | 2021-08-11 | 美商天工方案公司 | 用於封裝應用之濺鍍系統及方法 |
CN111048534B (zh) * | 2018-10-11 | 2022-03-11 | 胜丽国际股份有限公司 | 感测器封装结构 |
US11139268B2 (en) * | 2019-08-06 | 2021-10-05 | Advanced Semiconductor Engineering, Inc. | Semiconductor package structure and method of manufacturing the same |
US11521947B1 (en) * | 2021-07-14 | 2022-12-06 | Nxp Usa, Inc. | Space efficient flip chip joint design |
Family Cites Families (24)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB8911607D0 (en) * | 1989-05-19 | 1989-07-05 | Emi Plc Thorn | A method of encapsulation for electronic devices and devices so encapsulated |
TW272311B (zh) * | 1994-01-12 | 1996-03-11 | At & T Corp | |
US5661042A (en) * | 1995-08-28 | 1997-08-26 | Motorola, Inc. | Process for electrically connecting electrical devices using a conductive anisotropic material |
US5689091A (en) * | 1996-09-19 | 1997-11-18 | Vlsi Technology, Inc. | Multi-layer substrate structure |
KR100240748B1 (ko) * | 1996-12-30 | 2000-01-15 | 윤종용 | 기판을 갖는 반도체 칩 패키지와 그 제조 방법 및 그를 이용한적층 패키지 |
US6107683A (en) * | 1997-06-20 | 2000-08-22 | Substrate Technologies Incorporated | Sequentially built integrated circuit package |
US6376908B1 (en) * | 1997-12-10 | 2002-04-23 | Mitsubishi Gas Chemical Company, Inc. | Semiconductor plastic package and process for the production thereof |
US6495394B1 (en) * | 1999-02-16 | 2002-12-17 | Sumitomo Metal (Smi) Electronics Devices Inc. | Chip package and method for manufacturing the same |
US6195264B1 (en) * | 1998-11-18 | 2001-02-27 | International Business Machines Corporation | Laminate substrate having joining layer of photoimageable material |
JP3575001B2 (ja) * | 1999-05-07 | 2004-10-06 | アムコー テクノロジー コリア インコーポレーティド | 半導体パッケージ及びその製造方法 |
JP3893423B2 (ja) * | 1999-08-13 | 2007-03-14 | 新日本石油株式会社 | フェノール樹脂、エポキシ樹脂の製造方法 |
US6277672B1 (en) * | 1999-09-03 | 2001-08-21 | Thin Film Module, Inc. | BGA package for high density cavity-up wire bond device connections using a metal panel, thin film and build up multilayer technology |
GB2358957B (en) * | 1999-10-27 | 2004-06-23 | Ibm | Ball grid array module |
TW445558B (en) * | 2000-04-14 | 2001-07-11 | Via Tech Inc | Manufacturing method for cavity-down plastic ball grid array package substrate |
TW454320B (en) * | 2000-05-12 | 2001-09-11 | Siliconware Precision Industries Co Ltd | Semiconductor devices with heat-dissipation stiffener and manufacturing method thereof |
US6931723B1 (en) * | 2000-09-19 | 2005-08-23 | International Business Machines Corporation | Organic dielectric electronic interconnect structures and method for making |
JP2002232135A (ja) * | 2001-01-30 | 2002-08-16 | Matsushita Electric Ind Co Ltd | 積層用両面回路基板とその製造方法及びそれを用いた多層プリント配線板 |
SG108245A1 (en) * | 2001-03-30 | 2005-01-28 | Micron Technology Inc | Ball grid array interposer, packages and methods |
US6475327B2 (en) * | 2001-04-05 | 2002-11-05 | Phoenix Precision Technology Corporation | Attachment of a stiff heat spreader for fabricating a cavity down plastic chip carrier |
KR100432715B1 (ko) * | 2001-07-18 | 2004-05-24 | 엘지전자 주식회사 | 방열부재를 갖는 인쇄회로기판 및 그 제조방법 |
JP2004095972A (ja) * | 2002-09-03 | 2004-03-25 | Sumitomo Metal Electronics Devices Inc | プラスチックパッケージの製造方法 |
CN1484302A (zh) * | 2002-09-17 | 2004-03-24 | 华泰电子股份有限公司 | 半导体芯片的高散热微小封装体 |
KR100742066B1 (ko) * | 2002-12-13 | 2007-07-23 | 가부시키가이샤 가네카 | 열가소성 폴리이미드 수지 필름, 적층체 및 그것을 포함하는 인쇄 배선판의 제조 방법 |
CN1568129A (zh) * | 2003-06-24 | 2005-01-19 | 日月光半导体制造股份有限公司 | 电路基板及其制造方法 |
-
2005
- 2005-03-14 US US11/078,384 patent/US7344915B2/en active Active
- 2005-05-16 CN CNB2005100680843A patent/CN100378933C/zh active Active
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102254880A (zh) * | 2010-05-21 | 2011-11-23 | 南茂科技股份有限公司 | 芯片封装装置及其制造方法 |
CN102254880B (zh) * | 2010-05-21 | 2014-04-30 | 南茂科技股份有限公司 | 芯片封装装置及其制造方法 |
CN102479763A (zh) * | 2010-11-22 | 2012-05-30 | 钰桥半导体股份有限公司 | 一种散热增益型堆叠式半导体组件 |
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