CN1816914B - 半导体器件、制造量子阱结构的方法和包括这种量子阱结构的半导体器件 - Google Patents
半导体器件、制造量子阱结构的方法和包括这种量子阱结构的半导体器件 Download PDFInfo
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Abstract
公开了用于在具有量子阱结构(4)的多层结构(3)的衬底(2)上获得的半导体器件(1)和方法。量子阱结构(4)包括由绝缘层(6,6’)夹在中间的半导体层(5),其中绝缘层(6,6’)的材料优选具有高介电常数。在FET中,量子阱(4,9)用作沟道,允许较高的驱动电流和较低的截止电流。降低了短沟道效应。甚至对于亚35nm栅极长度,多沟道FET也适合于操作。在该方法中,优选通过MBE,通过交替地在相互的顶部上外延生长高介电常数材料和半导体材料来形成量子阱。
Description
技术领域
本发明涉及一种包括具有多层结构的衬底的半导体器件,该多层结构包括量子阱结构,该量子阱结构包括被另外的层夹在中间的半导体层。
本发明还涉及一种在衬底上制造量子阱结构的方法,包括如下步骤:
形成电绝缘材料层,
形成半导体材料层。
本发明还涉及一种制造包括这种量子阱的半导体器件的方法。
背景技术
论文“Multiple SiGe Quantum Wells-Novel Channel Architecture for0.12CMOS”,J.Alieu,T.Skotnicki,J.-L.Regolini和G.Bremond,Proceedings of 29th European Solid-State Device Research Conference,Leuven,Belgium,1999年9月13-15日,第292-295页公开了一种场效应晶体管。该场效应晶体管是具有在硅衬底上的量子阱结构的MOSFET。该量子阱结构包括由硅层包围的SiGe半导体层。该SiGe层的厚度是4nm且包围SiGe层的硅层具有4nm的厚度。
在Si上的外延生长SiGe应变层给出正比于锗部分的价带偏移,导致了空穴限制。
由于该价带偏移和较低的空穴有效质量,空穴迁移率以系数2增长。在具体实施例中,公开了包括三个量子阱结构的多个量子阱。
具有多个SiGe量子阱的公知场效应晶体管的缺点在于该改进受限于PMOS器件。由于应变的SiGe层的释放和自SiGe量子阱向表面的Ce扩散,制造多个SiGe量子阱很困难。
发明内容
本发明的一个目的是提供在开首段中提到的类型的半导体器件,其中对于p型和n型器件都改进了电荷传输。
根据本发明的一方面,提供一种半导体器件,该半导体器件包括具有与沟道区邻接的源和漏区以及位于沟道区上方的栅极的场效应晶体管,并且包括衬底和位于晶体管沟道区内的多层结构,该多层结构包括量子阱结构,该量子阱结构包括夹在电绝缘材料的另外层中间的半导体层,每一个都包括另一个半导体层和另一个电绝缘材料层的一个或多个多层子结构叠置在量子阱结构上,该多层子结构利用量子阱结构上部的另外层形成另一个量子阱结构,从而形成超晶格,所述栅极被定位成与所述半导体层相平行,特征在于所述半导体层和所述另一个半导体层具有距离,从而该半导体层作为另一个半导体层的栅极。
根据本发明的另一方面,提供一种制造上述半导体器件的方法。
在根据本发明的半导体器件中实现该目的在于另外的层的材料是电绝缘材料。
为绝缘体的固体通常具有相对大的带隙(通常大于几eV),导致在熔点下不可观测的传导率。当半导体层具有小于在半导体层的平面内可移动的电荷载流子的de Broglie波长的厚度时,由绝缘层包围的该半导体层为量子阱。在绝缘体材料和半导体材料之间的功函数的不同确定了量子阱的电势差V。
该电势差可出现在导带中或在价带中。该电势差可以是正的或负的。
当电荷载流子由某个电势V限定且该阱的宽度与其de Broglie波长向对应时,粒子的动量hk被量子化。对应于自由运动(m为颗粒质量)的连续能量谱E(k)=h2k2/2m分解为次能量带En(k),n为整数。只要禁闭V(r)不是无限的,则粒子非常可能处于分级的禁带隙区域中。电荷载流于迁移发生在量子阱的于能量带中。相对大的电势差V允许在量子阱中的几个次能带。由于这些次能带起到电荷载流于的沟道的作用,因此显著地改善了电荷载流子的输送。电荷载流子可以是电子或空穴。半导体器件可以是例如场效应晶体管、双极型晶体管、光电二极管或激光器。
当存在其它的量子阱叠置于形成超晶格的至少一个量子阱上时是有利的。由此在量子阱之间的距离很短以使得在量子阱中的电荷载流子的波函数之间交叠。交叠的波函数形成微带(miniband)。在量子阱中的电荷的耦合导致通过微带的增强的载流于输送。
优选绝缘体是高k电介质。术语高k电介质涉及到具有介电常数大于SiO2的介电常数的电介质。SiO2的介电常数的理论值是3.9。高k介电常数提高了在量子阱中的电荷载流子之间的电容耦合,并增强了在量子 阱中的电荷载流子的波函数中的交叠。
在有利实施例中,半导体器件是具有栅极的场效应晶体管,该栅极定位成基本上平行于至少一个量子阱结构。当该器件处于工作状态且将电压施加到栅极时,栅极控制在至少一个量子阱结构中的电荷载流子输送。可自源或漏极区提供电荷载流子。源和漏极区连接到至少一个量子阱。电荷载流子也可自具有某一波长λ的辐射产生。在半导体中产生了电子-空穴对,并且由电场将其分开。
而且,源极和漏极结的耗尽层的延伸并没有显著地伸入到量子阱中。因此降低了短沟道效应。这对于具有亚100nm栅极长度的CMOS晶体管来讲是非常重要的优点,在这样的CMOS晶体管中短沟道效应控制了晶体管的性能。
当存在由栅极下方的多个量子阱形成的超晶格时,其非常有利。在工作状态,将电压施加到栅极,以使得电流从源至漏极流动,或反之亦然。具有超晶格(由薄的半导体介电层形成的)的效果导致出现形成单个导带的栅极电势(对于所有的半导体层都是共同的,由垂直波函数的非零交叠引起),当具有零偏置的栅极时,只有顶部层具有全部电荷载流子。由于该超晶格,在FET中,开态载流子浓度增加,而截止态漏电流降低。该电流大致正比于量子阱的数目。
而且,源极和漏极结的耗尽层的延伸并没有显著地伸入到量子阱中。因此降低了短沟道效应。这对于具有亚100nm栅极长度的CMOS晶体管来讲是非常重要的优点,在这样的CMOS晶体管中短沟道效应控制了晶体管的性能。
为了获得从栅极向量子阱的良好的电容耦合,在一个量子阱和另一个量子阱之间的距离是使得一个量子阱起另一个量子阱的栅极的作用。
因此,优选地,包括高k材料的绝缘层具有小于1nm的相同的氧化硅厚度。
在先进的实施例中,半导体层包括硅。当高k材料的晶格常数是硅的晶格常数的整数倍,硅可外延生长在几种高k材料上,反之亦然。
一般当硅层的厚度小于10nm时,发生电荷载流子在硅中的禁闭。当硅厚度小于5nm时,在恰位于栅极下方的反型沟道中的电荷载流子密度剧烈地降低了。然后在反型沟道中的电荷载流子密度变得极度依赖于半导体层的掺杂浓度。掺杂浓度越大,反型沟道中的电荷载流于密度就越小。
因此,优选硅半导体层的厚度约为5nm。尤其是当使得FET的开态电流尽可能大的时候,几个单层硅足够起量子阱的作用。高k材料的绝缘层也优选为几个单层,以使得栅极的电压尽可能多的耦合至在最大可能数量的量子阱中的电荷载流子。
其它的硅化合物如SiGe或SiGeC可外延生长在高k材料上,尽管在层中存在应变。只要应变层相对薄,就不发生释放。高k材料可通过分子束外延(MBE)、化学气相淀积(CVD)、原子层化学气相淀积(ALCVD)或分子有机化学气相淀积(MOCVD)来外延生长。
本发明的另一个目的是提供一种制造在开首段中提到的类型的量子阱结构的方法,其中可调整电势的深度。
在根据本发明的量子阱结构中实现该方法的目的在于绝缘材料层和半导体材料层在相互的顶部外延生长。
绝缘层是结晶的且具有半导体材料的晶格常数的整数倍的晶格常数,反之亦然。晶格常数的某一偏差会导致应变,其可以是压缩的或是伸长的。只要该层薄,则某一晶格失配仍会导致外延生长。在结晶体衬底上通常存在由半导体材料制成的缓冲层。
该缓冲层使得现行的量子阱结构对表面污染具有较小敏感性。该绝缘材料可以是例如半导体氧化物、硅酸盐或金属氧化物,只要绝缘材料是结晶体即可。量子阱的深度可以是正的或负的。可外延生长在相互顶部上的多种绝缘材料和半导体材料提供了在设计势阱过程中的大的自由度。从该能带图,可以以不同的晶向计算材料的导带和价带。当形成化合物如SiGe和SiC时,很多半导体材料的晶格常数可变化某一数量。
半导体材料可以是Si、Ge、GaAs、InP或任何的结晶体材料。优选衬底具有高电阻率和在GHz范围内的频率处的低损耗。
当重复几次绝缘材料层和半导体材料层的外延生长时,可形成多个量子阱。
绝缘层的材料可以是具有大于3.9的介电常数的高k电介质。高k材料的介电常数越大,就越容易以可靠的方式控制高k材料层的厚度。具有接近于Si的晶格常数的晶格常数的高k材料如硅酸盐是在顶部生长Si的合适材料。绝缘材料层的等效氧化物厚度通常小于1nm。
优选通过分子束外延形成绝缘层。气体入口是纯净的,且超高真空非常适合于生长非常薄的外延层,而没有污染。
为了防止发生界面氧化物生长,原位退火绝缘层。在外延生长量子阱结构之后,在超高真空系统中退火该层。温度范围在200和700摄氏度C之间。在退火步骤中,尤其改善了绝缘体和半导体之间的界面。位错可移动至表面并消失。该原位退火防止形成中间非晶层如氧化硅或金属硅化物。
包括钇的高k材料非常适合于在硅上外延生长。在Si(001)衬底上,可以外延生长结晶的Y2O3。在理想的情况下,YO层由一个区域结构(domain structure)构成,但是在YO中的超结构也是非常适合的。
获得了非常明显的氧化硅界面,具有2-3埃的非常薄的界面区域。
由于Si技术的半导体工业的大量经验和与现有的CMOS、BiCMOS和其它的嵌入式CMOS处理相比较,半导体层优选包括硅或硅-锗组合物。
本发明的另一目的是提供一种制造在开首段中提到的类型的半导体器件结构的方法,在该器件中源极和漏极区的深度相对于其它亚100nm栅极长度CMOS晶体管来讲不必是超浅的。
实现该目的在于该方法进一步包括如下步骤:
在量子阱结构上形成栅极电介质,
形成栅极,
通过将掺杂原子引入到与栅极自对准的量子阱结构中到达至少量子阱结构的总厚度的深度来形成源区和漏区。
可通过穿过栅极的注入或通过自邻于栅极外延生长的升高的源和漏区的扩散来自对准栅极地形成源和漏区。栅极和外延生长区域通过间隔物来相互电绝缘。该间隔物可以是L状的且可用作注入源和漏区的延伸的补偿间隔物。通常将这些源极和漏极延伸定位成在栅极下方的小的扩展,以获得在MOS晶体管开态中的沟道上方的良好的栅极控制。由于源极和漏极结的耗尽层没有明显地穿进到量子阱中,因此降低了短沟道效应。这对于具有亚100nm栅极长度的CMOS晶体管是非常重要的优点,在这样的CMOS晶体管中短沟道效应控制了晶体管性能。
由于源极和漏极结具有寄生电容,因此其对于尽可能多的降低源极和漏板结也很重要。为了很好地将电荷载流子注入到量子阱中,结的深度应该至少是量子阱(超晶格)的总厚度。
自下面的详细描述,结合附图,本发明的这些和其它的特征和优点将变得显而易见,借助例子附图说明了本发明的原理。给出这种描述只是例子,并不限制本发明的范围。下面引用的参考图涉及到所附的图。
附图说明
图1是具有两个根据本发明的量子阱结构的半导体器件的示意图。
图2是包括两个根据本发明的量子阱结构的超晶格的示意性截面图。
图3是具有五个根据本发明的量子阱结构的场效应晶体管的示意性截面图。
图4示出了相对于常规晶体管(开口方形),如图3(填充的圆形) 中示出的场效应晶体管的阈值电压与栅极长度的关系曲线。
图5示出了相对于常规晶体管(开口方形),图3的场效应晶体管(填充的圆形)的截止态电流。
图6示出了相对于常规晶体管(虚线),图3中的场效应晶体管在两个不同的漏-源电压Vds=1.0V和Vds=0.1V下的输出特性(实线)。
具体实施方式
在图1中的半导体器件1的实施例中,衬底2是具有1017at/cm3掺杂浓度的p型硅(100)衬底,其上生长了多层结构3。在生长多层结构之前,移除了衬底的原生氧化层。在衬底上,外延生长了包括20nm的未掺杂的硅缓冲层的多层结构。随后通过MBE外延生长了量子阱结构4。量子阱结构4包括3nm的Y2O3(图1中的数字6)、5nm的Si(图1中的数字5)和3nm的Y2O3(图1中的数字6’)。随后生长了间隔层21且在间隔层顶部上外延生长了第二量子阱9。在该具体实施例中,该第二量子阱与第一量子阱相同。第二量子阱9可包括与第一量子阱4不同的高k材料8和不同的半导体层7。
高k材料Y2O3的介电常数约为20。在安装有适合于MBE生长Si和Si基化合物的电子枪的UHV室中进行生长。Y2O3(10.6 )的晶格常数约为Si(5.43 )的晶格常数的两倍。用于在Si(001)上良好外延质量的结晶体Y2O3的温度在450℃附近。Y2O3(110)//Si(100)是在相对高的温度(T>350℃)下的主要取向,而Y2O3(111)//Si(100)是在较低温度下优选的。域的形成是特定的异质外延取向Y2O3(110)//Si(001)的直接结果。在610℃左右的较高温度下,硅界面处的反应导致形成降低了外延层的整体质量的YSi2相。
衬底材料并不限于硅。其它适合的材料可以是Ge、GaAs、GaN或InP。只要衬底具有确定的晶格常数且高k材料具有约为衬底材料的晶格常数的整数倍的晶格常数,就可以获得外延异质结构。由于多层结构包括非常薄的高k材料层和非常薄的半导体层,所以该层会受到应变。
在图1b中,示出了图1a中的多层结构的能带图。在量子阱中,示出了可在平行于量子阱的方向(在半导体层的平面中)上移动的电荷载流子的离散能级E1。高k材料相对于半导体材料的功函数确定了在量子阱之间的能量势垒的高度。当电荷载流子如电子具有能量E1时,其能移动穿过离散能带E1,该离散能带E1称为沟道且位于半导体材料的标准禁带隙中。该离散能级通过在多层结构中的层的材料和晶体取向来确定。相对大的电势差V允许在量子阱中的几个子带。由于这些子能带起电荷载流子的沟道的作用,因此显著地改善了电荷载流子的输送。电荷载流子可以是电子或空穴,其经常从与量子阱相连的源区注入。辐射如可见光也可以在半导体中产生电子-空穴对。电子-空穴对可通过电场而相互分离。
在图2中,示出了作为超晶格的多层结构3。两个量子阱结构4、9的半导体层5、7每一个都通过电势V下的能量势垒而分离。能量势垒的高度是eV。
能量势垒的宽度通过高k层的厚度确定。在该具体的实施例中,每个Y2O3层也具有3nm的厚度,在3nm的Y2O3顶部上的Si层的厚度是5nm。在量子阱中的电子的波函数中的交叠产生了微带E微带。当高k材料的厚度进一步降低时,微带会被加宽且电荷载流子输送通过微带被进一步增强。
在高k材料和半导体材料的功函数之间差越高,可能的微带就越多。半导体或高k材料的功函数取决于材料的参数,如晶体取向、材料内部或在半导体材料和高k材料之间中的应变。多层结构可包括一个或多个不同介电常数氧化物的层,该氧化物选自氧化铪(HfO2)、氧化锆(ZrO2)、钛酸锶(SrTiO3)、氧化镧(La2O3)、氧化钇(Y2O3)、氧化钛(TiO2)、钛酸钡(BaTiO3)、铝酸镧(LaAlO3)、氧化钪镧(LaScO3)和氧化铝(Al2O3)的组。
半导体层的厚度确定了电荷密度分布。离散能级的填充发展(由于在Si-膜中电荷载流子禁闭)由其各自在Si导带(关于费米能级)中的位置被控制。对于厚度在3nm左右的层,电荷密度具有最大值。
在图3的有利实施例中,半导体器件是具有栅极和多个沟道的场效应晶体管。在该实施例中,FET是NMOS晶体管。以4×1013原子/cm2的注入剂量、4keV的能量用硼进行P阱注入。代替了常规FET的情况中具有形成晶体管沟道的体Si(bulk Si),首先在半导体衬底上生长超晶格。
淀积了覆盖层化结构(也在源区12和漏区12’中延展):具有0.6nm的等效氧化物厚度EOT的Y2O3层与具有1015原子/cm3的As掺杂级3nm Si交替生长,并重复5次(见图3)。以这种方式,获得了具有5个量子阱的NMOSFET,5个量子阱中的每一个都起沟道的作用。
然后,淀积栅极电介质。优选栅极电介质是类似于Hf基的高k电介质(如Hf-O-Si-N化合物)的高k材料。可选地,重金属氧化物及其与 铝酸盐和Si氧化物的混合物(硅酸盐)是非常合适的,且允许按比例缩小至0.5nm EOT,在栅极泄漏中提供了2-5个数量级的降低。
基本垂直于5个量子阱结构定位栅极。在栅极和量子阱之间的电容耦合应尽可能地强。栅极材料可以是如TaN或TiN的具有Si的功函数中间能隙(workfunction midgap)的金属,或者是高掺杂的多晶硅。在该具体的实施例中,通过栅极以70keV、4×1013at/cm2的As进行阈值电压注入。
为了减少注入损伤,在生长超晶格之前,进行注入到半导体本体中的p阱中的阈值电压(VT)是有利的。
该实施例中示出的器件具有25nm的非常短的栅极长度。对于这样的短栅极长度来讲,不需要阈值电压注入。该半导体层可以是本征硅。
在形成栅极之后,将掺杂剂原子引入到超晶格中以形成源极和漏极结。可通过离子注入来引入掺杂剂原子,或从超晶格顶部上的缓冲层向外扩散该掺杂剂原子。对于n型晶体管来讲,在源极、漏极和栅极中的该掺杂剂原子是As、Sb、P。在该实施例中,用As以1keV的能量、15nm的偏移量同时注入源极12和漏极12’。为了该目的,使用L形的补偿间隔物。
对于p型晶体管,可以使用B或In作为掺杂原子。
源极和漏极结的深度优选几乎与在FET的垂直方向中的超晶格的总的层厚度相同。在该实施例中,该深度是35nm。不需要超浅结是大的优点。
如果将1V电压施加到栅极,则电荷载流子注入到量子阱中。在该例子中,电荷载流子是电子。但是如果极性是相反的(PMOS器件),则相同的情况可应用于空穴。
栅极电势控制在全部量子阱中的电荷载流子输送。在栅极下方的沟道中的电荷载流子用作相邻量子阱的栅极。通过这种方式,沟道用作一个导电沟道。
源极和漏极结的耗尽层没有明显地延伸到量子阱中。因此,降低了短沟道效应。在图4中可以看出短沟道效应的降低。对于具有5个量子阱(填充的圆形)的NMOS晶体管来讲,相对于常规(和在处理中的等价物)体NMOS晶体管(bulk NMOS transistor)(开口方形),阈值电压(VT)下降显著地减小。如果栅极关断,则在最接近栅极的沟道中只存 在电荷载流子。这些电荷载流子确定截止电流。
在图5中示出了对比于常规体NMOS器件(开口方形),具有5个量子阱(填充的圆形)的NMOS晶体管降低了约3个数量级的截止电流。
在图6中,具有5个量子阱(多沟道MOS)的NMOS晶体管的电学性能与常规(和在处理中的等价物)体晶体管相对比。注意到,对于体晶体管的总的等效氧化物厚度为1.5nm,而对于多沟道MOS来讲是3nm。在整体情况下的25nm的器件完全不起作用(虚线),而多沟道MOS相对于栅极-源极电压(Ids-Vgs)曲线(实线)显示出卓越的漏极-源极电流。示出了在两种不同的漏极-源极电压Vds=1.0V和Vds=0.1V下的漏源极电流Ids。
该Ids常被称为是开态电流,Ion是520μA/um和截止电流是Ioff=7nA/μm。亚阈值电压斜率是83mV/dec。可以从多沟道MOS晶体管具有非常良好的电学特性的结果作出结论,尤其是对于亚35nm CMOS一代。目前为止,广泛地认为通过单个栅极Si MOSFET能够实现这样的性能。相信唯一可行的方法是具有超薄Si沟道(1.5-5nm)的双栅极器件。
多个量子阱不仅可用在NMOS或PMOS晶体管中,也可用在任一般导体器件如双极型晶体管、HBT、二极管、存储器件、光电器件或量子器件。当通过电势V的电荷载流子禁闭起重要作用且量子效应在器件的电荷载流子输送中为重要时,本发明尤其有用。
Claims (14)
1.一种半导体器件(1),该半导体器件(1)包括具有与沟道区邻接的源和漏区以及位于沟道区上方的栅极(11)的场效应晶体管,并且包括衬底(2)和位于晶体管沟道区内的多层结构(3),该多层结构包括量子阱结构(4),该量子阱结构包括夹在电绝缘材料的另外层(6,6’)中间的半导体层(5),一个或多个多层子结构叠置在量子阱结构(4)上,该多层子结构各自包括另一个半导体层(7)和另一个电绝缘材料层(8),并利用量子阱结构(4)上部的另外层(6’)形成另一个量子阱结构(9),从而形成超晶格,所述栅极(11)被定位成与所述半导体层相平行,特征在于所述半导体层(5)和所述另一个半导体层(7)具有距离,从而所述半导体层(5)作为所述另一个半导体层(7)的栅极,以及电绝缘材料为具有大于SiO2的介电常数的高k材料。
2.如权利要求1的半导体器件,其特征在于高k材料是结晶体。
3.如权利要求2的半导体器件,其特征在于在包括高k材料的另外层(6)和位于该另外层(6)顶部上的半导体层(5)的半导体材料之间存在外延。
4.如权利要求1至3中任一项的半导体器件,其特征在于所述另外层(6,6’)的电绝缘材料具有小于1nm的等效硅氧化物厚度。
5.如权利要求1至3中任一项的半导体器件,其特征在于半导体层(5)包括硅。
6.如在权利要求5的半导体器件,其特征在于半导体层(5)的厚度小于10nm。
7.如权利要求1至3中任一项的半导体器件,其特征在于所述另外层(6,6’)包括具有不同的介电常数的高k电绝缘材料。
8.如权利要求6的半导体器件,其特征在于穿过量子阱结构(4,9)延伸的掺杂区域(12)形成至量子阱结构(4,9)的电接触。
9.一种制造半导体器件(1)的方法,该半导体器件(1)包括具有与沟道区邻接的源和漏区以及位于沟道区上方的栅极(11)的场效应晶体管,并且包括衬底(2)和位于晶体管沟道区内的多层结构(3),该多层结构包括量子阱结构(4),该量子阱结构包括夹在电绝缘材料的另外层(6,6’)中间的半导体层(5),每一个都包括另一个半导体层(7)和另一个电绝缘材料层(8)的一个或多个多层子结构叠置在量子阱结构(4)上,该多层子结构利用量子阱结构(4)上部的另外层(6’)形成另一个量子阱结构(9),从而形成超晶格,所述栅极(11)被定位成与所述半导体层相平行,特征在于所述半导体层(5)和所述另一个半导体层(7)具有距离,从而所述半导体层(5)作为所述另一个半导体层(7)的栅极,以及电绝缘材料为具有大于SiO2的介电常数的高k材料,
其中,采用以下步骤在衬底(2)上形成量子阱结构(4):
在衬底(2)顶部上形成电绝缘材料的另外层(6),
在电绝缘材料的另外层(6)顶部上形成半导体层(5),其中半导体层(5)在电绝缘材料的另外层(6)的顶部上外延生长,所述步骤至少执行两次。
10.如权利要求9的方法,其特征在于采用分子束外延形成电绝缘材料的另外层(6,6’)。
11.如权利要求9的方法,其特征在于原位退火电绝缘材料的另外层(6,6’)。
12.如权利要求9的方法,其特征在于选择包括钇的材料作为电绝缘材料。
13.如权利要求9的方法,其特征在于选择硅或硅锗组合物作为半导体层(5)的材料。
14.如权利要求9的方法,其特征在于:
在所述另一个量子阱结构(9)上形成栅极电介质(14),
形成栅极(11),
通过将掺杂原子引入到与栅极(11)自对准的所述另一个量子阱结构(9)中到达至少是量子阱结构(4,9)的总厚度的深度,来形成源极区(12)和漏极区(12’)。
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