TWI597844B - Field effect transistor - Google Patents

Field effect transistor Download PDF

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Publication number
TWI597844B
TWI597844B TW103128861A TW103128861A TWI597844B TW I597844 B TWI597844 B TW I597844B TW 103128861 A TW103128861 A TW 103128861A TW 103128861 A TW103128861 A TW 103128861A TW I597844 B TWI597844 B TW I597844B
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Taiwan
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field effect
effect transistor
dielectric constant
type
relative dielectric
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TW103128861A
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TW201517273A (zh
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Shinji Migita
Hiroyuki Ota
Koichi Fukuda
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Aist
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Description

場效電晶體
本發明係關於一種使次臨限區域中之電流變化率急峻變化，而減小使電流值發生一位數變化所必要之閘極電壓之場效電晶體。
以半導體積體電路之低消耗電力化為目的，追求使作為構成要素之各個電晶體之消耗電力減少。
於該種技術中，已進行如下研究開發：藉由使上述電晶體之接通/斷開之開關動作之閾值電壓以下之區域(次臨限區域)之電流變化率急峻變化，而減少開關動作所必要之電力。該次臨限區域中之電流變化率係作為使電流值發生一位數變化所必要之閘極電壓(S因素)設為指標，該值為越低值，可將開關動作設為越急峻者。
但，於通常之電晶體之構成中，上述次臨限區域之室溫下之電流變化率理論上設為60mV/decade以上，存在無法獲得低於其之急峻之特性之問題(例如，參照非專利文獻1)。
因此，目前之狀況係藉由與先前之電晶體不同之構成，摸索開發具有上述電流變化率小於60mV/decade之急峻之特性之新電晶體。
作為該種新電晶體，例如，有人提出利用穿隧現象之穿隧場效型電晶體(非專利文獻2)。
但，於上述提案之穿隧場效型電晶體中，藉由向穿隧接合施加強電場而調變頻帶，感應載體之穿隧輸送，故動作時需要較大之閘極電壓，而存在無法實現低消耗電力化之問題。
因此，現狀係自各種觀點摸索研究開發用於以低消耗電力，使上述次臨限區域之電流變化率於室溫下急峻化為不滿60mV/decade之新電晶體。
[先前技術文獻]
[專利文獻]
[非專利文獻1]Yuan Taur and Tak H. Ning著、Fundamentals of MODERN VLSI DEVICES, Cambridge University Press 1998, p. 128.
[非專利文獻2]W. Y. Choi, et.al., Electron Device Letters 28 (2007) 743.
本發明之課題在於解決先前之上述諸問題，達成以下之目的。即，本發明之目的係提供一種可以低消耗電力，使次臨限區域之電流變化率於室溫下急峻化為不滿60mV/decade之場效電晶體。
為解決上述課題，本發明者進行專心研究，獲得以下之見解。
即，於累積動作型之場效電晶體中，藉由以具有相對介電常數根據施加於閘極電極之閘極電壓之大小發生減少變化之上述相對介電常數之變化梯度之介電質構成閘極絕緣膜，可以低消耗電力，使上述次臨限區域之電流變化率於室溫下急峻化為不滿60mV/decade。
關於該見解，利用圖1進行說明。圖1係顯示以上述相對介電常數不變化之材料及上述相對介電常數變化之介電質形成有上述閘極絕緣膜之情形之電晶體特性之圖。如圖1所示，於表示上述相對介電常數為5且固定之情形之電流變化率(汲極電流-閘極電壓特性)之曲線a、表示上述相對介電常數為10且固定之情形之上述電流變化率之曲線b及表示上述相對介電常數為25且固定之情形之上述電流變化率之曲線c中，無法使上述次臨限區域之上述電流變化率於室溫下急峻化為不 滿60mV/decade，於表示上述相對介電常數根據上述閘極電極之電場強度發生變化之情形之上述電流變化率之曲線d中，上述相對介電常數以橫穿5、10、25之情形之特性之方式，特性發生變化，可使上述次臨限區域之上述電流變化率於室溫下急峻化為不滿60mV/decade。
本發明係基於上述見解者，作為解決上述課題之步驟，係如下所述，即：
<1>一種場效電晶體，其特徵係累積層動作型者，該場效電晶體包含：半導體層，其形成有共通設為N型及P型之任一導電型之源極區域、通道區域及汲極區域；及閘極電極，其介隔閘極絕緣膜而與上述通道區域鄰接配置；且上述閘極絕緣膜係以具有相對介電常數根據施加於上述閘極電極之閘極電壓之大小發生減少變化之上述相對介電常數之變化梯度之介電質形成。
<2>如上述技術方案<1>之場效電晶體，其中將施加於介電質之電場強度為0時作為原點，自上述原點脫離之上述電場強度之範圍中，上述介電質具有相對介電常數之極大值。
<3>如上述技術方案<1>至<2>中任一項之場效電晶體，其中介電質具有於將閘極電壓調變0.5V時，較調變前之相對介電常數成為上述相對介電常數之0.5倍以下之上述相對介電常數之變化梯度。
<4>如上述技術方案<1>至<3>之場效電晶體，其中介電質係以將具有鈣鈦礦型結晶構造之金屬氧化物、具有螢石型結晶構造之金屬氧化物、具有種類不同之上述鈣鈦礦型結晶構造之金屬氧化物之層積層所形成之超晶格構造，將具有種類不同之上述螢石型結晶構造之金屬氧化物之層積層所形成之超晶格構造，及將具有上述鈣鈦礦型結晶構造之金屬氧化物之層與具有上述螢石型結晶構造之金屬氧化物之層積層所形成之超晶格構造中之任一者形成。
<5>如上述技術方案<1>至<4>中任一項之場效電晶體，其中半導體層之厚度為6nm~10nm。
<6>如上述技術方案<1>至<5>中任一項之場效電晶體，其中通道區域之雜質濃度為4×1018/cm3~7×1018/cm3。
<7>如上述技術方案<1>至<6>中任一項之場效電晶體，其中於通道區域與閘極絕緣膜之間配置界面層。
<8>如上述技術方案<1>至<7>中任一項之場效電晶體，其中半導體層之形成材料為矽、鍺、錫、矽與鍺之混晶、鍺與錫之混晶、及III-V族化合物中之任一者。
<9>如上述技術方案<1>至<8>中任一項之場效電晶體，其中電晶體構造為塊體型、SOI型、鰭片型、及納米線型中之任一者。
根據本發明，可解決先前技術之上述諸問題，可提供一種可以低消耗電力，使次臨限區域之電流變化率於室溫下急峻化不滿60mV/decade之場效電晶體。
1‧‧‧支持基板
2‧‧‧絕緣層
3‧‧‧源極區域
4‧‧‧汲極區域
5‧‧‧通道區域
6‧‧‧界面層
7‧‧‧閘極絕緣膜
8‧‧‧閘極電極
9‧‧‧半導體層
10‧‧‧場效電晶體
20‧‧‧場效電晶體
21‧‧‧支持基板
22‧‧‧絕緣層
23‧‧‧源極區域
24‧‧‧汲極區域
25‧‧‧通道區域
27‧‧‧閘極絕緣膜
28‧‧‧閘極電極
29‧‧‧半導體層
31‧‧‧場效電晶體之閘極電壓-汲極電流特性
32‧‧‧場效電晶體之閘極電壓-汲極電流特性
33‧‧‧場效電晶體之閘極電壓-相對介電常數特性
a‧‧‧曲線
b‧‧‧曲線
c‧‧‧曲線
d‧‧‧曲線
圖1係顯示以相對介電常數不變化之材料及相對介電常數變化之介電質形成有閘極絕緣膜之情形之電晶體特性之圖。
圖2係顯示本發明之一實施形態之場效電晶體之剖面構造之說明圖。
圖3係顯示介電質之電場強度-介電常數特性之圖。
圖4係顯示非線性應答介電質之電場強度-介電常數特性之圖。
圖5(a)係顯示具有鈣鈦礦型結晶構造之SrTiO3之相對介電常數之電場依存性之一例之圖。
圖5(b)係顯示具有超晶格構造之介電質之相對介電常數(靜電電容)之電場(電壓)依存性之一例之圖。
圖6係顯示設為模擬試驗之對象之場效電晶體之剖面構造之說明圖。
圖7係顯示場效電晶體之閘極電壓-汲極電流特性之圖。
圖8係顯示閘極絕緣膜相對於閘極電壓之EOT變化之圖。
圖9係顯示將閘極電壓調變0.5V時之EOT變化率特性之圖。
圖10係顯示算出使通道區域之厚度發生變化之情形之電流變化率(Subthreshold swing)之結果之圖。
圖11係顯示算出使通道領域之雜質濃度發生變化之情形之電流變化率(Subthreshold swing)之結果之圖。
圖12係顯示SrHfO3膜之結晶構造之測定結果之圖。
圖13(a)係顯示形成有具有鈣鈦礦型結晶構造之SrHfO3之單體膜之Si基板之Sr原子之深度分佈之測定結果之圖。
圖13(b)係顯示形成有界面層之情形之Sr原子之深度分佈之測定結果之圖。
主要參照圖2說明本發明之場效電晶體。圖2係顯示本發明之一實施形態之場效電晶體之剖面構造之說明圖。如該圖2所示，場效電晶體10係以支持基板1、絕緣層2、源極區域3、汲極區域4、通道區域5、界面層6、閘極絕緣膜7及閘極電極8構成。
作為支持基板1，無特別限制，可根據目的適當選擇，例如，可應用周知之SOI(Silicon on Insulator：絕緣層上覆矽)基板中之支持基板。
絕緣層2配置於支持基板1上。作為該絕緣層2，無特別限制，可根據目的適當選擇，例如，可應用上述SOI基板中之埋入氧化膜。
形成源極區域3、汲極區域4及通道區域5之半導體層9配置於絕緣層2上。作為該半導體層9，無特別限制，可根據目的適當選擇， 例如，可應用上述SOI基板中之半導體層。即，作為支持基板1、絕緣層2及半導體層9，可使用上述SOI基板構成。
另，雖例示上述SOI基板，但作為構成半導體層9之半導體材料，無特別限制，亦可適當選擇矽以外之半導體材料，例如，可使用鍺、錫、矽與鍺之混晶、鍺與錫之混晶、InxGa1-xAs(其中，x為0.53以上)、GaSb等之III-V族化合物等。
作為半導體層9之厚度，雖無特別限制，但自使上述次臨限區域之上述電流變化率於室溫下急峻化為不滿60mV/decade之觀點而言，較佳為6nm~10nm。
源極區域3及汲極區域4係於半導體層9離子注入雜質物質所形成。作為上述雜質物質，若為產生載體之材料，則無特別限制，設為N型之導電型之情形時，例舉P、As等。又，設為P型之導電型之情形時，例舉B等。作為離子注入之方法，無特別限制，可藉由周知之離子注入方法實施，例如，可藉由周知之離子注入裝置，對半導體層9進行將二氟化硼(BF2)氣體、膦(PH3)氣體、砷化氫(AsH3)氣體等之原料氣體、及固體P、固體As等之原料固體作為離子源之離子注入而實施。
該等源極區域3及汲極區域4係以同一導電型形成。又，作為源極區域3及汲極區域4之上述雜質物質之濃度，無特別限制，為減少寄生電阻，較佳為1×1019/cm3~1×1021/cm3。
通道區域5配置於源極區域3-汲極區域4之間，作為累積動作型之電晶體，以與源極區域3及汲極區域4相同之導電型形成。
作為該通道區域5，無特別限制，可藉由與源極區域3及汲極區域4相同之形成方法形成，作為通道區域5之上述雜質濃度，自使上述次臨限區域之上述電流變化率於室溫下急峻化為不滿60mV/decade之觀點而言，較佳為4×1018/cm3~7×1018/cm3。
如以上般，半導體層9係形成有共通設為N型及P型之任一導電型之源極區域3、通道區域5及汲極區域4，而可進行累積層型之電晶體動作。即，於閘極電極8設定特定之閘極電壓時，藉由因閘極電極8與通道區域5之電性電位差而產生之場效，通道區域5空乏化而切斷源極區域3-汲極區域4間之汲極電流(斷開狀態)，於閘極電極8施加不同之閘極電壓時，通道區域5之空乏化減退而促進於通道區域5中形成與源極區域3及汲極區域4相同之載體之累積層，經由上述累積層而於源極區域3-汲極區域4間流通汲極電流(接通狀態)。
但，於上述累積動作型之電晶體中，一般為未施加閘極電壓之情形時亦流通電流之以常開動作之類型，作為應用於低消耗電力之積體電路時之電晶體，較佳為以常關動作之類型。因此，於場效電晶體10中，設為以常關動作之類型之累積動作型之電晶體。
另，於場效電晶體10中，根據周知之例，藉由調整閘極電極8之金屬材料(功函數)及通道區域5(半導體層9)之厚度，將規定開/關動作之閾值電壓設定為特定值，而可以常關動作。即，藉由上述閾值電壓之設定，於場效電晶體10中，即使於未施加閘極電壓之狀態下，通道區域5亦以消除因閘極電極8與通道區域5之電性電位之差而產生之電場之方式空乏化而設為斷開狀態，另一方面，於正方向施加閘極電壓時，上述電場變弱，空乏化減退而設為接通狀態。
閘極絕緣膜7配置於通道區域5上，以具有相對介電常數根據施加於閘極電極8之閘極電壓之大小發生減少變化之上述相對介電常數之變化梯度之介電質形成。利用圖3說明該介電質之特性。另，圖3係顯示介電質之電場強度-介電常數特性之圖。
一般，於介電質中，存在具有該圖3中之符號A所例示之特性之、相對介電常數根據電場強度之變化發生變化之介電質(此處，將該介電質稱為非線性應答介電質)，及具有符號B所例示之特性之、相 對介電常數相對於電場強度之變化不發生變化之介電質(此處，將該介電質稱為線性應答介電質)。作為上述線性應答介電質之代表例，舉例SiO2，作為上述累積動作型之場效電晶體或反轉動作型之場效電晶體之閘極絕緣膜，被廣泛使用。對此，於場效電晶體10中，使用上述非線性應答介電質作為閘極絕緣膜7之形成材料，利用上述相對介電常數根據施加於閘極電極8之上述閘極電壓之大小發生減少變化之上述相對介電常數之變化梯度，使上述次臨限區域之上述電流變化率於室溫下急峻化為不滿60mV/decade。
此處，於場效電晶體10中，於上述相對介電常數根據上述閘極電壓之大小發生變化之上述非線性應答介電質中，以利用該相對介電常數發生減少變化之上述相對介電常數之變化梯度之全部或者一部分之方式，設定上述閘極電壓之範圍而動作。
又，關於圖3，於具有符號A所例示之特性之上述非線性應答介電質中，上述相對介電常數根據上述電場強度發生變化，於場效電晶體10中，利用於上述閘極電壓之動作範圍中，上述閘極電壓增加時上述非線性應答介電質之上述電場強度變化，上述相對介電常數發生減少變化之作用。
作為上述非線性應答介電質，較佳為將所施加之電場強度為0時作為原點，而於自上述原點脫離之上述電場強度之範圍中具有上述相對介電常數之極大值。利用圖4說明該上述非線性應答介電質之特性。另，圖4係顯示上述非線性應答介電質之電場強度-介電常數特性之圖。
如該圖4所示，作為上述非線性應答介電質之較佳之特性，例舉於自上述原點脫離之上述電場強度之範圍中具有上述相對介電常數之極大值之、向上凸之曲線表示之特性。
於累積動作型之場效電晶體10中，即使為於閘極電極8未施加閘 極電壓之斷開狀態，藉由因上述電性電位差而產生之場效，存在於上述非線性應答介電質施加強電場強度之情形。因此，適合使用於自上述原點脫離之上述電場強度之範圍中具有上述相對介電常數之極大值之上述非線性應答介電質。
又，於利用上述相對介電常數之變化梯度之場效電晶體10中，自使上述次臨限區域之上述電流變化率於室溫下急峻化為不滿60mV/decade之觀點而言，較佳為上述相對介電常數之變化梯度急峻，具體而言，上述非線性應答介電質較佳為具有以絕對值大0.5V調變閘極電壓時，與調變前之上述相對介電常數相比成為上述相對介電常數之0.5倍以下之上述相對介電常數之變化梯度。
作為上述非線性應答介電質，無特別限制，作為具有上述特性者，例如，較佳為以將具有鈣鈦礦型結晶構造之金屬氧化物、具有螢石型結晶構造之金屬氧化物、具有種類不同之上述鈣鈦礦型結晶構造之金屬氧化物之層積層所形成之超晶格構造，將具有種類不同之上述螢石型結晶構造之金屬氧化物之層積層所形成之超晶格構造，及將具有上述鈣鈦礦型結晶構造之金屬氧化物之層與具有上述螢石型結晶構造之金屬氧化物之層積層所形成之超晶格構造中之任一者形成。
作為具有上述鈣鈦礦型結晶構造之金屬氧化物，例如，例舉CaTiO3、SrTiO3、BaTiO3、CaZrO3、SrZrO3、BaZrO3、CaHfO3、SrHfO3、BaHfO3、PbTiO3、(Ba,Sr)TiO3、Pb(Zr,Ti)O3、SrBi2Ta2O9、SrBi2Nb2O9、Sr2Bi4Ti5O18等。
又，作為具有上述螢石型結晶構造之金屬氧化物，例如，例舉ZrO2、添加有9摩爾%~13摩爾%之Y之ZrO2、HfO2、添加有9摩爾%~13摩爾%之Y之HfO2、添加有9-13摩爾%之La之HfO2、及(Zr,Hf)O2等。
又，作為上述超晶格構造，例如，例舉SrTiO3與BaTiO3之積層構 造物、SrZrO3與BaZrO3之積層構造物、SrHfO3與BaHfO3之積層構造物、ZrO2與HrO2之積層構造物、SrHfO3與HfO2之積層構造物、SrZrO3與ZrO2之積層構造物等。
作為如此之上述非線性應答介電質，有各種報告例，可根據該等周知例形成。作為該等周知例之具體例，於圖5(a)、圖5(b)中顯示具有上述鈣鈦礦型結晶構造之SrTiO3之報告例(參考文獻1)、上述超晶格構造之報告例(參考文獻2)。該等圖均係顯示上述非線性應答介電質之上述相對介電常數之電場依存性者。
又，作為以上述非線性應答介電質形成之閘極絕緣膜7之厚度，雖無特別限制，但自使上述次臨限區域之上述電流變化率於室溫下急峻化為不滿60mV/decade之觀點而言，較佳的是，將閘極電壓調變0.5V時之實效氧化膜厚(EOT；Equivalent Oxide Thickness)之變化率(EOTmax/EOTmin)為2以上。另，EOTmax表示閘極電壓調變後之EOT，EOTmin表示閘極電壓調變前之EOT。
參考文獻1：S. Komatsu et al., Jpn. J. Appl. Phys. vol. 37 (1998) p. 5651.
參考文獻2：J. Kim et al., Appl. Phys. Lett. vol. 80 (2002) p. 3581
閘極電極8配置於閘極絕緣膜7上。作為閘極電極8之形成材料，無特別限制，例如，例舉Al、Au、Pt、w、TaN、TiN、矽化物等。又，作為閘極電極8之形成方法，無特別限制，例舉濺鍍法、CVD(Chemical Vapor Deposition：化學氣相沉積)法等。又，作為閘極電極8之厚度，無特別限制，只要設為10nm~50nm左右即可。
界面層6配置於通道區域5與閘極絕緣膜7之間。該界面層6具有抑制閘極絕緣膜7-通道區域5間之各構成原子之相互擴散之作用，根據閘極絕緣膜7及通道區域5之構成基於必要而配置。
作為界面層6之形成材料，無特別限制，舉例HfO2、ZrO2、 Al2O3、SiN、InP等。作為界面層6之形成方法，亦無特別限制，舉例濺鍍法、CVD法等。
另，配置界面層6之情形時，作為界面層6之厚度，越薄越佳，例如，較佳為5nm以下。又，配置界面層6之情形時，作為上述閘極絕緣膜7之EOT，係附加界面層6之EOT而設定。
對如此般構成之累積動作型之場效電晶體10之動作進行說明。
首先，將閘極電極8之閘極電壓設定為0至較小值。此時，於閘極絕緣膜7因閘極電極8與通道區域5之電性電位差而施加強電場強度，根據圖4所示之上述非線性應答介電質之特性，成為相對介電常數較大之狀態。於該狀態中，於通道區域5亦施加與閘極絕緣膜7之電場平衡之強電場而空乏化，強力切斷源極區域3-汲極區域4間之汲極電流(斷開狀態)。
其次，於閘極電極8施加大於上述斷開狀態之閘極電壓。此時，於閘極絕緣膜7中，隨著閘極電壓變大，閘極絕緣膜7之電場強度變弱，根據上述非線性應答介電質之特性，相對介電常數以減少之方式發生變化。根據該減少變化，於通道區域5中，於空乏化之區域漸漸累積載體，形成累積層，經由通道區域5之上述累積層，於源極區域3-汲極區域4間流通汲極電流(接通狀態)。
此時，可使自斷開狀態過渡至接通狀態時之上述次臨限區域之上述電流變化率於室溫下急峻化為不滿60mV/decade。
又，可以低電壓規定開/關切換時之閘極電壓之動作範圍。
另，作為記憶體動作用途，已知有以介電常數根據電場強度發生變化之強介電質形成閘極絕緣膜，而構成作為反轉動作型之場效電晶體者。但，應用該上述反轉動作型之場效電晶體之構成，而構成開關動作用途之場效電晶體之情形時，無使上述電流變化率於室溫下急峻化為不滿60mV/decade之報告。作為其理由，雖並非明確，但根據 本發明者們計算研究之結果，可推測為：因為於上述反轉層動作之情形時，上述非線性應答介電質之上述閘極絕緣膜之效果不發揮作用，汲極電流為一定值之鞍點存在於上述次臨限區域內，而阻礙電流變化率之急峻化。
舉圖1、圖4所示之特性為例說明該情況。閘極電壓較小時(-0.1V，參照圖1中之曲線d)，閘極絕緣膜7之電場強度為較強狀態(1.5MV/cm，參照圖4)，閘極絕緣膜7之相對介電常數採取極大值。(相對介電常數：25，參照圖4)。
隨著閘極電壓自該狀態變大(1.0V，參照圖1中之曲線d)，閘極絕緣膜7之電場強度變弱(1.0MV/cm，參照圖4)，閘極絕緣膜7之相對介電常數下降(相對介電常數：5，參照圖4)，可實現汲極電流之急峻上升(參照圖1中之曲線d)。
另，於該例中，雖已對使閘極電壓朝正方向變化之、所謂之N型電晶體之情形進行說明，但於本發明之場效電晶體中，亦可應用於使閘極電壓朝負方向變化動作之、所謂之P型電晶體。即，由於該情形時閘極絕緣膜7之相對介電常數及電場強度之變化亦為與朝正方向變化之情形相同之變化，故可設為利用該特性之場效電晶體。
又，作為本發明之一實施形態，雖已舉例說明以SOI型之場效電晶體為代表之、於半導體層9之通道區域5上依序配置有閘極絕緣膜7與閘極電極8之場效電晶體10，但作為利用形成閘極絕緣膜7之上述非線性應答介電質之特性之電晶體構成，不限於該SOI型，作為本發明之場效電晶體，可由利用結晶基板之平坦表面作為通道之塊體型、對通道區域以將一面與另一面形成為字狀之閘極絕緣膜及閘極電極覆蓋之鰭片型、將圓筒狀地形成之通道區域之外周以閘極絕緣膜及閘極電極覆蓋之納米線型等之周知之電晶體構成所構成。
為了以上所說明之場效電晶體之動作確認，進行模擬試驗。該 模擬試驗係設想圖6所示之場效電晶體20而進行。圖6係顯示設為上述模擬試驗之對象之場效電晶體20之剖面構造之說明圖。
於該場效電晶體20中，係由於支持基板21上依序積層絕緣層22、形成有源極區域23、汲極區域24及通道區域25之半導體層29之SOI基板，配置於通道區域25上之閘極絕緣膜27，及配置於閘極絕緣膜27上之閘極電極28所構成。
此處，作為各部之詳情，將半導體層29之厚度設為8nm，將離子注入於源極區域23及汲極區域24之雜質設為As，將該雜質濃度設為1×1020/cm3，將離子注入於通道區域25之雜質設為As，將該雜質濃度設為5×1018/cm3，將由上述非線性應答介電質形成之閘極絕緣膜27之相對介電常數設為可於25至5之範圍內變化，將閘極電極28之功函數設為5.0eV。
於上述模擬試驗中，保持源極電極為0V，且汲極電極為0.1V之狀態，而計算於場效電晶體20之閘極電極28施加閘極電壓時之汲極電流。另，計算時使用之模擬器為Selete公司所開發之HyENEXX ver.5.5。
於圖7顯示模擬結果。圖7係顯示場效電晶體20之閘極電壓-汲極電流特性之圖。又，圖7中，符號31係表示場效電晶體之閘極電壓-汲極電流特性，符號32表示設為既存之場效電晶體之理論性界限之、上述次臨限區域之室溫下之電流變化率為60mV/decade之汲極電流之上升特性。又，符號33表示場效電晶體之閘極電壓-相對介電常數特性，具有隨著閘極電壓變大而閘極絕緣膜27之相對介電常數發生減少變化之變化梯度。
如該圖7所示，場效電晶體20之閘極電壓-汲極電流特性顯示較場效電晶體更急峻之汲極電流之上升，上述次臨限區域之室溫下之電流變化率設為48mV/decade。
另，對上述模擬試驗之計算時使用之、閘極絕緣膜27相對於閘極電壓之相對介電常數變化進行說明。如下述式(1)所示，於由上述非線性應答介電質形成之閘極絕緣膜27中，具有相對介電常數最大時EOT最薄，相對介電常數最小時EOT最厚之關係。於圖8顯示閘極絕緣膜27相對於閘極電壓EOT變化。於上述模擬試驗中，利用該EOT變化特性進行計算。
其中，上述式(1)中，T表示閘極絕緣膜27之物理膜厚，ε表示閘極絕緣膜之介電常數，εSiO2表示SiO2之介電常數。
如以上所示，於上述模擬試驗中，可獲得較既存之場效電晶體之理論性界限之、上述次臨限區域之室溫下之電流變化率為60mV/decade更急峻之汲極電流之上升特性。
以下，進而說明針對用以獲得急峻之汲極電流之上升特性之條件進行研究之結果。
首先，說明變更上述之EOT變化之特性之情形。自獲得急峻之汲極電流之上升之觀點而言，將閘極電壓調變0.5V時，必須使相對介電常數變化發生較大變化。
此處，關於此前之圖8所示之EOT變化，基於將閘極電壓調變0.5V時之EOT變化率(EOTmax/EOTmin)，研究對獲得急峻之汲極電流之上升有效之相對介電常數變化條件。
圖9中顯示將閘極電壓調變0.5V時之EOT變化率特性。圖8中，○係表示上述電流變化率不滿60mV/decade之情形，×係表示上述電流變化率為60mV/decade以上之情形。另，EOTmax係表示閘極電壓調變後之EOT，EOTmin係表示閘極電壓調變前之EOT。
如該圖9所示，將閘極電壓調變0.5V時之EOT變化率(EOTmax/EOTmin)為2以上之情形時，可獲得上述電流變化率不滿60mV/decade之急峻之電流上升特性。此點係指將閘極電壓調變0.5V時，閘極絕緣膜27具有較閘極電壓調變前之相對介電常數成為上述相對介電常數之0.5倍以下之上述相對介電常數之變化梯度。
其次，說明半導體層29之通道區域25之厚度與上述電流變化率之關係。
圖10中顯示於上述模擬試驗中，算出使通道區域25之厚度變化之情形之上述電流變化率(Subthreshold swing)之結果。
如該圖10所示，可確認於通道區域25之厚度為6nm~10nm之情形時可獲得上述電流變化率不滿60mV/decade之急峻之電流上升特性。
其次，說明半導體層29之通道區域25之雜質濃度與上述電流變化率之關係。
圖11中顯示於上述模擬試驗中，算出使通道區域25之雜質濃度發生變化之情形之上述電流變化率(Subthreshold swing)之結果。
如該圖11所示，可確認於通道區域25之雜質濃度為4×1018/cm3~7×1018/cm3之情形時可獲得上述電流變化率不滿60mV/decade之急峻之電流上升特性。
[實施例]
進行將與上述模擬試驗之計算中使用之閘極絕緣膜27具有相同特性之上述非線性應答介電質之膜實際成膜之成膜實驗。此處，作為上述非線性應答介電質之膜，進行具有鈣鈦礦型結晶構造之SrHfO3膜之成膜。
首先，對配置於RF濺鍍裝置(股份有限公司ULVAC公司製造，MPS-6000-MLT)之真空室中之Si基板，控制目標之電漿出力及快門開 關時間，並進行於Ar氣體氛圍中將SrO2及HfO2作為目標之濺鍍，而形成已調整化學組合之SrHfO3膜。其次，對形成有SrHfO3膜之Si基板，於氮氣氛圍中以1,000℃進行10秒鐘之加熱處理，而形成具有鈣鈦礦型結晶構造之SrHfO3膜。
圖12中，顯示藉由SrHfO3膜之平面X射線解析裝置(Rigaku公司製造，高解析度X射線薄膜評估裝置，SuperLab)之結晶構造之測定結果。如該圖12所示，於本成膜實驗中，可於Si基板上形成具有鈣鈦礦型結晶構造之SrHfO3之單體膜。
此處，對形成有具有鈣鈦礦型結晶構造之SrHfO3之單體膜之Si基板，使用拉瑟福後方散射分析裝置(神戶製鋼所製造，HRBS500)，進行Sr原子之深度分佈之測定。於圖13(a)顯示測定結果。圖13(a)中，實線表示上述加熱處理後之Sr原子之深度分佈，虛線表示上述加熱處理前之Sr原子之深度分佈。
如該圖13(a)所示，於上述加熱處理之前後，可見表現信號強度之能量位置與寬度之變化。該點表示Sr原子之一部分與Si基板發生反應且擴散，而產生深度分佈之擴大。
此後，一旦於Si基板形成厚度為3nm之HfO2膜作為界面層後，用與上述相同之方法於HfO2膜上進行具有鈣鈦礦型結晶構造之SrHfO3膜之形成。此處，HfO2膜係使用RF濺鍍裝置(股份有限公司ULVAC公司製造，MPS-6000-MLT)成膜。
圖13(b)中顯示藉由形成有該界面層之情形之拉瑟福後方散射分析裝置進行Sr原子之深度分佈之測定之結果。圖13(b)中，實線表示上述加熱處理後之Sr原子之深度分佈，虛線表示上述加熱處理前之Sr原子之深度分佈。
如該圖13(b)所示，形成有界面層之情形時，於上述加熱處理之前後，表現信號強度之能量位置與寬度大致一致。
因此，形成有界面層之情形時，可抑制Sr原子擴散於Si基板中。
31‧‧‧場效電晶體之閘極電壓-汲極電流特性
32‧‧‧場效電晶體之閘極電壓-汲極電流特性
33‧‧‧場效電晶體之閘極電壓-相對介電常數特性

Claims (8)

  1. 一種場效電晶體，其特徵在於：其係累積層動作型(accumulation-layer-operation type)者，該場效電晶體包含：半導體層，其形成有共通設為N型及P型之任一導電型之源極區域、通道區域及汲極區域；及閘極電極，其介隔閘極絕緣膜而與上述通道區域相鄰配置；且上述閘極絕緣膜係以具有相對介電常數根據施加於上述閘極電極之閘極電壓之大小而變少之上述相對介電常數之變化梯度之介電質形成；上述介電質具有：將閘極電壓調變了0.5V時，相較於調變前之相對介電常數而成為0.5倍以下之上述相對介電常數的上述相對介電常數之變化梯度。
  2. 如請求項1之場效電晶體，其中將施加於介電質之電場強度為0時作為原點，自上述原點脫離之上述電場強度之範圍中，上述介電質具有相對介電常數之極大值。
  3. 如請求項1或2之場效電晶體，其中介電質係以將具有鈣鈦礦型結晶構造(perovskite-type crystalline structure)之金屬氧化物、具有螢石型結晶構造(fluorite-type crystalline structure)之金屬氧化物、具有種類不同之上述鈣鈦礦型結晶構造之金屬氧化物之層積層所形成之超晶格構造，將具有種類不同之上述螢石型結晶構造之金屬氧化物之層積層所形成之超晶格構造，及將具有上述鈣鈦礦型結晶構造之金屬氧化物之層與具有上述螢石型結晶構造之金屬氧化物之層積層所形成之超晶格構造中之任一者形成。
  4. 如請求項1或2之場效電晶體，其中半導體層之厚度為6nm~10 nm。
  5. 如請求項1或2之場效電晶體，其中通道區域之雜質濃度為4×1018/cm3~7×1018/cm3。
  6. 如請求項1或2之場效電晶體，其中於通道區域與閘極絕緣膜之間配置界面層。
  7. 如請求項1或2之場效電晶體，其中半導體層之形成材料為矽、鍺、錫、矽與鍺之混晶、鍺與錫之混晶、及III-V族化合物中之任一者。
  8. 如請求項1或2之場效電晶體，其中電晶體構造為塊體型、SOI型、鰭片型、及納米線型中之任一者。
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US11444171B2 (en) * 2019-03-06 2022-09-13 Intel Corporation Self-aligned gate endcap (SAGE) architecture having gate or contact plugs
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