CN1728400A - 多栅晶体管及其制造方法 - Google Patents

多栅晶体管及其制造方法 Download PDF

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CN1728400A
CN1728400A CNA2005100845687A CN200510084568A CN1728400A CN 1728400 A CN1728400 A CN 1728400A CN A2005100845687 A CNA2005100845687 A CN A2005100845687A CN 200510084568 A CN200510084568 A CN 200510084568A CN 1728400 A CN1728400 A CN 1728400A
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channel region
transistor
floating boom
insulator
gate
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CN100459161C (zh
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布伦特·A·安德森
艾德华·J·诺瓦克
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GlobalFoundries Inc
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Abstract

本申请公开了一种包括沟道区和沟道区端部的源和漏区的多栅晶体管。在逻辑栅和沟道区之间设置栅氧化物，在浮栅和沟道区之间形成第一绝缘体。该第一绝缘体比栅氧化物厚。浮栅与其它结构电绝缘。并且，在编程栅和浮栅之间设置第二绝缘体。逻辑栅中的电压导致晶体管的导通和断开，而浮栅中的存贮电荷调节晶体管的阈值电压。晶体管可以包括翅型场效应晶体管(FinFET)，其中沟道区包括翅结构的中间部分，源和漏区包括翅结构的端部。

Description

多栅晶体管及其制造方法
技术领域
本发明一般地涉及晶体管，更具体地涉及在沟道区的一侧上具有逻辑栅并且在沟道区的另一侧上具有浮栅和编程栅的多栅晶体管。
背景技术
晶体管的尺寸已经持续地减小，以提高速度并减小使用晶体管的器件的尺寸。比例缩小是描述晶体管尺寸的这种持续减小的术语。互补金属氧化物半导体(CMOS)器件的比例缩小已经将集成电路推至可以提供给器件的功率的极限。这种功率危机的一个重要方面是由于场效应晶体管(FET)中的亚阈值漏电。在一个管芯内，多个FET的阈值电压(Vt)的变化严重限制了可以制造的速度。本发明提供了一种途径在制造工艺后调节一个管芯内各个FET的Vt以及结构。
发明内容
本发明提供了一种多栅晶体管，包括沟道区和在沟道区端部的源和漏区。栅氧化物位于逻辑栅和沟道区之间，第一绝缘体被形成在浮栅和沟道区之间。第一绝缘体比栅氧化物厚。浮栅与其它结构电绝缘。并且，第二绝缘体位于编程栅和浮栅之间。逻辑栅中的电压使晶体管导通或断开，而编程栅中的电压调节晶体管的阈值电压。晶体管可以包括翅型场效应晶体管(FinFET)，其中沟道区包括翅结构的中间部分，而源和漏区包括翅结构的端部。
本发明的这些和其它方面将在结合下文的描述和附图时考虑时更容易理解。然而，应当理解的是下文的描述尽管指出了本发明的优选实施方式及其大量特定的细节，但只是以示例而非限制的方式给出。可以在本发明的范围内进行许多改变和变更，而不背离其精神，本发明包括所有这样的变更。
附图说明
从下文参照附图的详细描述可以更好地理解本发明。
图1是部分完成的晶体管的截面示意图；
图2是部分完成的晶体管的截面示意图；
图3是部分完成的晶体管的截面示意图；
图4是部分完成的晶体管的截面示意图；
图5是部分完成的晶体管的截面示意图；
图6是部分完成的晶体管的截面示意图；
图7是部分完成的晶体管的截面示意图；
图8是部分完成的晶体管的截面示意图；
图9是部分完成的晶体管的截面示意图；
图10是部分完成的晶体管的截面示意图；
图11是部分完成的晶体管的截面示意图；
图12是部分完成的晶体管的截面示意图；
图13是部分完成的晶体管的截面示意图；
图14是部分完成的晶体管的截面示意图；
图15是部分完成的晶体管的截面顶视图。
具体实施方式
参照在附图中示出并在下文的描述中详细给出的非限制性实施方式，更完整地解释本发明及各种特征及有益的细节。应当注意，附图中示出的特征没有必要按比例绘制。对公知的部件和处理技术的描述被省略，以免不必要地混淆本发明。希望这里采用的例子只是便于理解应用本发明的方式并进而使本领域的技术人员可以应用本发明。因此，这些例子不应理解成对本发明的范围的限制。
为了提供对阈值电压的控制的提高，从而帮助解决集成电路中出现的功率危机，本发明给出了一种双栅晶体管，其中第一栅是通常的用于逻辑或其它电路、具有薄氧化物的栅，而第二栅包括叠置的浮栅。在诊断测试中，确定哪些器件具有过高(慢)的Vt，或过低的Vt(漏电的)。然后按照为芯片提供较高性能和较低功率的需要对浮栅编程。更具体地，通过向编程栅提供高电压，或者通过电子从漏向浮栅的隧穿，或者，如果也提供了高的漏电压，通过在漏区边缘沟道热电子的注入，从而可以改变浮栅中的电荷。也即，载流子通过分隔漏和浮栅的绝缘体而流至浮栅。浮栅中的电荷产生穿过沟道区的电场线，改变晶体管自身的阈值电压。因此，通过改变浮栅的电荷，可以提高或减小晶体管的阈值电压。作为衬底中的注入线或BOX中的埋置互连，布线网络可以被用作浮栅的编程网格(programming grid)。
尽管本领域的一般技术人员将理解本发明可以在多种不同类型的晶体管中实现，包括翅型场效应晶体管(FinFET)、平面晶体管、垂直晶体管等，但图1-14示出了本发明在FinFET晶体管中实施的一个例子。更具体地，图1示出了衬底晶片10、埋置的氧化物(box)绝缘体结构12、硅层14、绝缘体(如SiO2或Si3N4/SiO2叠层等)、以及模芯(mandrel)18。正如本领域的一般技术人员可以理解的那样，可以采用许多不同的工艺来形成图1所示的结构，为了简洁不对相同的情形进行详细讨论。
在图2中，本发明的蚀刻穿过绝缘体16和硅14，停止在氧化层12上，以产生开口22。这可包括单一的蚀刻步骤(process)或多个蚀刻步骤。在产生这些开口之后，例如采用如热氧化的任何传统氧化物形成工艺在露出的硅14的侧面上生长氧化物20。随后，在图3中例如按任何通用的间隔层形成技术，沉积导体30(如多晶硅或一些其它的通用导体)，然后进行选择性地去除。例如，当形成侧壁间隔层时，通常沉积材料，然后按取向的蚀刻去除(例如各向异性蚀刻)，该取向的蚀刻从水平表面去除材料的速率高于从垂直表面去除材料的速率，这只在各种结构的侧壁上留下材料。如图3所示，这在绝缘体20上形成导电的间隔层30。然后附加的蚀刻步骤去除埋置的氧化层12的一部分，停止在晶片材料10上，如图4所示。
在图5中本发明再次在晶片和导体30的露出区域上形成绝缘体50。该绝缘体50再次可以是任何通用的绝缘体(如SiO2或Si3N4/SiO2叠层等)，并采用本领域的一般技术人员公知的许多技术来生长。在图6中，沉积另一个导体60(多晶硅或任何公知的导体)。然后，按选择性的蚀刻工艺去除中央部分66，该中央部分穿过绝缘体50向下延伸到晶片10。
如图7所示，在前面的导体材料60上方和开口66中沉积附加的导电材料70。在图8中，再次采用公知的工艺形成绝缘体80。然后，在图9中采用如蚀刻的选择性去除处理去除模芯材料18。在图10中，采用如上面讨论的任何侧壁间隔层形成技术在导体70和绝缘体80的露出部分上形成遮蔽间隔层100。
在图11中，采用蚀刻工艺去除硅14和绝缘体16的一部分。这种处理使硅14形成翅结构，这可以从图14中示出的顶视图中更清楚地看出。随后，在图12中，在硅14的露出部分上生长绝缘体120。在图13中，在整个结构的上方沉积栅材料130，并随后进行图案化。注意浮栅30和编程栅70也与逻辑栅130同时被图案化。图14示出了沿图13的线I-I所示的结构的顶视图，栅导体130在硅翅14的中央部分上方被图案化。硅翅142的中央部分包括沟道区，而硅翅14的端部140被掺杂成包括源和漏区。
图13和14表示包括沟道区142和沟道区142端部的源和漏区140的多栅晶体管的最终结构。栅氧化物120位于逻辑栅130和沟道区142之间，第一绝缘体20形成在浮栅30和沟道区142之间。第一绝缘体20比栅氧化物120厚。浮栅30与其它结构电绝缘。同样，第二绝缘体50位于编程栅70和浮栅30之间。逻辑栅130中的电压导致晶体管导通或断开，而浮栅30中的电荷调节晶体管的阈值电压。
如图14所示，晶体管可以包括翅型场效应晶体管(FinFET)，其中沟道区142包括翅结构14的中间部分，而源和漏区142包括翅结构14的端部。或者，本发明可以包括图15中示意性示出的任何晶体管。该结构包括上文中讨论的逻辑栅130、源和漏140、沟道区142、氧化物120、绝缘体20和50、浮栅30和编程栅70。该类型的晶体管可包括平面场效应晶体管、垂直场效应晶体管、或任何其它的类似类型的晶体管。
如上所述，通过改变编程栅70的电压，浮栅30中的电压被相应的改变，使得电荷可以传输至浮栅，或从浮栅向外传输。也即，载流子通过将漏14的一部分与浮栅30分隔的绝缘体20从漏14向浮栅30迁移。在浮栅30上存贮的电荷产生穿过沟道区142的电场线，这改变了晶体管自身的阈值电压。因此，通过改变浮栅30的电荷，可以提高或减小晶体管的阈值电压。这使得浮栅可以按照为芯片提供较高的性能和较低的功耗的需要而被编程。
作为本发明的结果，可以制造具有较小的延迟或较低的漏电的电路。具体地，晶体管或晶体管组的漏电可以在制造半导体器件之后按需要来调节，例如在一些电路的速度过快时，通过提高选定的快速器件的阈值电压而减少漏电。类似地，如果确定一些晶体管速度不够，可以减小那些晶体管的阈值电压，以提高那些晶体管的驱动强度。一些电路的功能关键地取决于特定的关系，例如，6T SRAM单元内FET的驱动强度的比率；通过按需要调节FET组以恢复电路中的阈值电压或驱动强度的所需关系，这些电路可以进一步地衍生提高处理产率的好处，否则，这些电路将会由于刚制造时的不合格而失效。
尽管已经按照优选的实施方式描述了本发明，本领域的技术人员将认识到本发明可以在所附权利要求的精神和范围内应用。

Claims (28)

1.一种多栅晶体管，包括：
沟道区；
与所述沟道区的第一侧相邻的逻辑栅；
与所述沟道区的第二侧相邻的浮栅，其中所述第一侧与所述第二侧相反；以及
与所述浮栅相邻的编程栅，其中所述浮栅在所述编程栅和所述沟道区之间。
2.根据权利要求1的晶体管，还包括所述沟道区和所述逻辑栅之间的栅氧化物，以及所述沟道区和所述浮栅之间的第一绝缘体，其中所述第一绝缘体比所述栅氧化物厚。
3.根据权利要求1的晶体管，其中所述逻辑栅中的电压导致所述晶体管导通或断开。
4.根据权利要求1的晶体管，其中所述浮栅中的电荷调节所述晶体管的阈值电压。
5.根据权利要求1的晶体管，其中所述晶体管包括翅型场效应晶体管即FinFET。
6.根据权利要求1的晶体管，还包括所述沟道区端部的源和漏区，其中所述沟道区包括翅结构的中间部分，所述源和漏区包括所述翅结构的端部。
7.根据权利要求1的晶体管，其中所述浮栅与其它结构电绝缘。
8.一种多栅晶体管，包括：
沟道区；
所述沟道区端部的源和漏区；
所述沟道区的第一侧上的栅氧化物；
与所述第一栅氧化物相邻的逻辑栅，其中所述栅氧化物在所述逻辑栅和所述沟道区之间；
所述沟道区的第二侧上的第一绝缘体，其中所述沟道区的所述第二侧与所述第一侧相反；
与所述第一绝缘体相邻的浮栅，其中所述第一绝缘体在所述浮栅和所述沟道区之间；
与所述浮栅相邻的第二绝缘体；以及
与所述第二绝缘体相邻的编程栅，其中所述第二绝缘体在所述编程栅和所述浮栅之间。
9.根据权利要求8的晶体管，其中所述第一绝缘体比所述栅氧化物厚。
10.根据权利要求8的晶体管，其中所述逻辑栅中的电压导致所述晶体管导通和断开。
11.根据权利要求8的晶体管，其中所述浮栅中的电荷调节所述晶体管的阈值电压。
12.根据权利要求8的晶体管，其中所述晶体管包括翅型场效应晶体管即FinFET。
13.根据权利要求8的晶体管，其中所述沟道区包括翅结构的中间部分，所述源和漏区包括所述翅结构的端部。
14.根据权利要求8的晶体管，其中所述浮栅与其它结构电绝缘。
15.一种制造多栅晶体管的方法，所述方法包括：
形成沟道区；
形成与所述沟道区的第一侧相邻的逻辑栅；
形成与所述沟道区的第二侧相邻的浮栅，其中所述第一侧与所述第二侧相反；以及
形成与所述浮栅相邻的编程栅，其中所述浮栅在所述编程栅和所述沟道区之间。
16.根据权利要求15的方法，还包括在所述沟道区和所述逻辑栅之间形成栅氧化物，在所述沟道区和所述浮栅之间形成第一绝缘体，其中所述第一绝缘体比所述栅氧化物厚。
17.根据权利要求15的方法，其中所述逻辑栅中的电压导致所述晶体管导通或断开。
18.根据权利要求15的方法，其中所述浮栅中的电荷调节所述晶体管的阈值电压。
19.根据权利要求15的方法，其中所述晶体管包括翅型场效应晶体管即FinFET。
20根据权利要求15的方法，还包括所述沟道区的端部处的源和漏区，其中所述沟道区包括翅结构的中间部分，所述源和漏区包括所述翅结构的端部。
21.根据权利要求15的方法，其中所述浮栅与其它结构电绝缘。
22.一种制造多栅晶体管的方法，所述方法包括：
形成沟道区；
在所述沟道区的端部形成源和漏区；
在所述沟道区的第一侧上形成栅氧化物；
形成与所述第一栅氧化物相邻的逻辑栅，其中所述栅氧化物在所述逻辑栅和所述沟道区之间；
在所述沟道区的第二侧上形成第一绝缘体，其中所述沟道区的所述第二侧与所述第一侧相反；
形成与所述第一绝缘体相邻的浮栅，其中所述第一绝缘体在所述浮栅和所述沟道区之间；
形成与所述浮栅相邻的第二绝缘体；以及
形成与所述第二绝缘体相邻的编程栅，其中所述第二绝缘体在所述编程栅和所述浮栅之间。
23.根据权利要求22的方法，其中所述第一绝缘体比所述栅氧化物厚。
24.根据权利要求22的方法，其中所述逻辑栅中的电压导致所述晶体管导通或断开。
25.根据权利要求22的方法，其中所述浮栅中的电荷调节所述晶体管的阈值电压。
26.根据权利要求22的方法，其中所述晶体管包括翅型场效应晶体管即FinFFT。
27.根据权利要求22的方法，其中所述沟道区包括翅结构的中间部分，所述源和漏区包括所述翅结构的端部。
28.根据权利要求22的方法，其中所述浮栅与其它结构电绝缘。
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