CN1726582A - 制造半导体器件的方法和用该方法获得的半导体器件 - Google Patents

制造半导体器件的方法和用该方法获得的半导体器件 Download PDF

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CN1726582A
CN1726582A CNA2003801064123A CN200380106412A CN1726582A CN 1726582 A CN1726582 A CN 1726582A CN A2003801064123 A CNA2003801064123 A CN A2003801064123A CN 200380106412 A CN200380106412 A CN 200380106412A CN 1726582 A CN1726582 A CN 1726582A
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V·C·维内兹亚
C·J·J·达奇斯
J·C·霍克
M·J·H·范达尔
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Interuniversitair Microelektronica Centrum vzw IMEC
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Abstract

本发明涉及一种具有场效应晶体管的半导体器件(10)的制造方法，在该方法中，提供半导体材料的半导体主体(1)，在其表面具有源区(2)和漏区(3)以及源区(2)和漏区(3)之间的栅区(4)，其中栅区栅电介质(5)与半导体主体(1)表面分离的另一半导体材料的半导体区(4A)，并且具有用于形成源和漏区(2，3)的邻近栅区(4)的隔离物(6)，在该方法中，给源区(2)和漏区(3)提供了用于形成金属和半导体材料化合物(8)的金属层(7)，并且给栅区(4)提供了用于形成金属和另一半导体材料化合物(8)的金属层(7)。不同的金属层被用于硅化源和漏区和栅区(2，3，4)的已知方法有若干缺点。依据本发明方法的特征在于，在形成隔离物(6)之前，关于半导体区(4A)可选择性蚀刻的材料的牺牲区(4B)在半导体区(4A)的顶部上被沉积，并且在形成隔离物(6)之后，通过蚀刻去除牺牲层(4B)，而在牺牲层(4B)去除之后，沉积单一金属层(7)与源、漏以及栅区(2，3，4)接触。该方法一方面非常简单，这是由于它仅需单个金属层和少量的直接向前的步骤并且和现有的(硅)技术相兼容，而在另一方面它产生在完全硅化的栅(4)中没有耗尽层效应的(MOS)FET。

Description

制造半导体器件的方法和用该方法获得的半导体器件
本发明涉及制造具有场效应晶体管的半导体器件的方法，在该方法中，在半导体材料的半导体主体的表面，提供了源区和漏区以及源区和漏区之间的栅区，其中栅区包括通过栅电介质来与半导体主体表面分离的另一半导体材料的半导体区，并且具有用于形成源和漏区的邻近栅区的隔离物，在该方法中，源区和漏区具有用金属和半导体材料化合物形成的金属层，并且漏区用金属和另一半导体材料化合物形成的另一金属层。通过这种方法获得的具有多晶硅栅的MOSFET(＝金属氧化物半导体场效应晶体管)会遭受问题即：耗尽层效应可导致MOSFET的有效栅电容和晶体管驱动电流的不希望的减小。该影响已成为CMOS(＝互补MOS)尺寸减小的显著限制。在栅—栅电介质界面增加掺杂可减小所说的耗尽层，但是栅掺杂受多晶硅中掺杂剂的溶度的限制。因此必须找到多晶硅或非晶硅或单晶栅的替换物。
在开始段落中提到的方法在2001年3月20日公开的美国专利6,204,103中公知。在那里的第6栏第51行到第7栏第10行中描述了该方法，其中硅MOSFET的源和漏与一金属层硅化以及栅与另一金属层硅化，后者的金属层不同于NMOS和PMOS晶体管的多晶硅栅。该过程提供了避免上述耗尽效应的可能，从而可避免有效栅电容的减小。
该方法的一个缺点是当它包括一方面硅化源和漏以及另一方面硅化多晶硅栅的不同步骤时该方法是相当复杂的。而且，它还包含如CMP(＝化学机械抛光)步骤的多个其它步骤，这些增加了该方法的复杂性。
因此，本发明的目的是避免上述缺点和提供简单的方法并且避免上述耗尽层效应的可能，特别是在具有多晶硅栅的MOSFET中。
为了实现该目的，根据本发明，在开始段落中描述的该类方法的特征在于，在形成隔离物之前，关于半导体区可选择性蚀刻的材料的牺牲区在半导体区的顶部被沉积，而在形成隔离物之后，通过蚀刻去除牺牲层，以及在牺牲层去除之后，沉积单一金属层与源、漏以及栅区接触。此外，本发明还基于这一认识即：通过多晶硅栅的全部硅化可避免上述的耗尽层效应是可能的。而且，可在源和漏的硅化的同时进行，假设和当前工艺的标准栅厚度相比，多晶硅栅的厚度受限于相对小的厚度。本发明进一步基于这一认识即：当栅堆叠的高度要减少时上述厚度的减少是不希望的，其对所用的技术，如离子注入能量和隔离物厚度，有很大影响。通过在栅堆叠的半导体区上提供牺牲区，在减少半导体区的层厚度的同时可保持栅堆叠的高度不变。选择牺牲区的厚度使与半导体区的期望的减少互补。因此避免了对技术的上述影响并且同时由于为了硅化源和漏区以及栅区仅需单个金属层，依照本发明的方法是相对简单的。为栅堆叠选择的总高度依赖于正被讨论的技术，即，关于实际晶体管的尺寸。例如，对于标准的CMOS工艺，标准的半导体区可以是例如100nm厚度。在那种情况下，半导体区可减小到例如50nm而同样选择牺牲区为50nm。
由于相对于例如多晶硅可选择性地蚀刻牺牲区的事实，在金属层沉积之前可容易地去除牺牲区。在该方法中，隔离物的高度和宽度保持不受影响，这是由于它们是由全部的栅堆叠的总高度来决定的。牺牲区的蚀刻可是湿法蚀刻或干法蚀刻。
总之，依据本发明的方法的优点是仅需对标准的CMOS工艺进行轻微的改变，即，无需增加如光刻和CMP的困难步骤，其产生全部硅化的栅并且因此在器件操作期间无耗尽影响。此外，去除隔离物之后器件获得的剩余物相对较平坦，其使得后来的前金属电介质层的沉积、图案化和蚀刻变得更容易。
在优选实施例中，通过在其上存在包括半导体区和牺牲区的栅区的半导体主体的顶部上沉积一层电介质材料以及通过用蚀刻随后去除栅区的顶部和两侧上的沉积层来形成隔离物。该过程是简单的并且隔离物的宽度和高度都依赖于栅堆叠的高度和沉积的电介质层的厚度。
从上述来看，很清楚，如果半导体区例如多晶硅在金属和另一半导体材料化合物的形成期间完全被消耗，则获得关于耗尽层效应减少的最好结果。
在优选的实施例中，在金属与半导体材料和金属与另一半导体材料之间化合物的形成在两个独立的加热步骤中进行，第一加热步骤导致具有较低含量的半导体材料或另一半导体材料的中间化合物，而在第二加热步骤中，中间化合物被转变成具有更高含量的半导体材料或另一半导体材料的化合物。因此，在硅MOST和钴金属层的情况下，中间化合物将为例如CoSi而化合物将为CoSi2。后者材料的薄层电阻比前者的薄层电阻小得多，这显然是重要的优点。优选地，通过在第一和第二加热步骤之间进行蚀刻来去除对于形成中间化合物未起反应的金属层的一部分。
在另一个优选的修改中，一层另一半导体材料，即在硅MOST情况下的多晶硅层在两个加热步骤之间在半导体主体的表面上被沉积。在第二热处理期间，该层例如5到10nm厚为从CoSi形成的例如CoSi2而作为硅的源。因此，该层的沉积减轻了多晶硅可供消耗的栅，即栅的半导体硅区的厚度的限制。在第二加热步骤之后，去除例如多晶硅层的未反应部分。即可通过选择性的干法或湿法蚀刻或者也可通过氧化并随后通过基于HF的蚀刻剂去除得到的氧化物来进行去除。
优选地，在金属和半导体材料以及金属和另一半导体材料的化合物形成之后去除隔离物。在该方法中，得到的结构保持相对平坦化。一般地，对于半导体材料和另一半导体材料，硅是优选的材料，而中间化合物和化合物是由硅化物形成的。目前硅是在半导体工业中使用最广泛最成功的材料。包括用依据本发明的方法获得的场效应晶体管的半导体器件提供了在本描述的前面部分所述的重要优点。
参照其后描述的实施例以及结合相关的附图，这些和本发明的其它方面将变得显而易见，其中
图1到6是在依靠依据本发明的方法的器件制造中各个阶段的半导体器件的截面图，
图7和8是在依靠依据本发明方法的改进的器件制造中各个阶段的半导体器件的截面图，和
图9显示了薄层电阻作为通过依据本发明的方法来制造的器件的栅的半导体区的厚度的函数。
这些图是示意性的，并不是按比例画的，为了更清楚，厚度方向的尺寸被特别地放大了。在各种图中的相应部分一般给出相同的参考数字和相同的阴影。
图1到6是在依靠依据本发明的方法的器件制造中各个阶段的半导体器件的截面图。器件10(参见图1)包括半导体主体1，在这种情况下，其由硅构成，但也可选择由其它合适的半导体材料构成。用于主体1的基底是p型硅衬底11，其中形成n型阱12。在主体1中形成隔离区13—所谓的二氧化硅的沟槽。随后在硅主体1表面上通过热氧化形成栅氧化物5。然后通过CVD(＝化学汽相沉积)形成半导体层4A，这里是多晶硅层，在其顶部也是通过CVD沉积牺牲层4B，在该实例中的牺牲层是氮化硅，一种可选择性地从下面的多晶硅材料4A中去除的材料。掩膜111然后在形成栅4的位置上的堆叠的顶部上形成。
随后(参见图2)在掩膜111的外部的氮化硅层4B和多晶硅层4A被去除，通过该步骤形成了包括栅氧化物5、多晶区4A和牺牲区4B的栅堆叠4。区4A的厚度被选择为40nm并且牺牲区4B的厚度被选择为60nm。栅堆叠4的厚度因此大约等于100nm，其在标准CMOS工艺中相应于亚100nm的器件的高度。
接着(参见图3)使浅的n型注入2B、3B形成待形成的MOSFET的源和漏区2，3的LDD(＝轻掺杂的漏)的扩展。接着进行高能量的p型所谓的HALO倾斜注入(在附图中没有单独示出)，并且执行其以提高在LDD的边缘处的沟道渗杂。然后接着形成隔离物6。通过CVD方法在器件10上沉积二氧化硅的电介质层6。因此覆盖栅堆叠4。本实例中电介质层6的厚度总计为90-100nm。然后，通过干法蚀刻方法，再次去除沉积层以使得既清理了牺牲区4B的上表面又清理了在栅堆叠4的两侧的主体1的表面。由于蚀刻的各向同性的特性，二氧化硅的隔离物6保持附着于栅堆叠4的侧面。现在进行更深的n+型注入2A、3A以完成源和漏2、3的形成。然后半导体主体在1000到1100摄氏度的温度下退火，以激活源和漏的注入2A、2B、3A、3B。图3在单一图中显示了所有的这些步骤。
随后(参见图4)通过选择性的蚀刻去除栅堆叠4的牺牲区4B。依靠湿法蚀刻，使用热磷酸作为用于区4B的氮化硅的蚀刻剂，在本实例中进行蚀刻。在该方法中，蚀刻不仅关于多晶区4A是选择性的而且关于隔离物6的二氧化硅和薄热氧化物也是选择性的，其中薄热氧化物可以存在于在栅堆叠4的两侧上的半导体主体1的表面上。接着，金属层7沉积在结构10上。在该实例中，金属层7包括10nm厚的钴层和在其顶部上的8nm厚的钛层。钛层的功能可阻止硅化后的捷径(shortcuts)并且用作用于氧气的阻挡和/或氧气的吸气剂。
接着(参见图5)热处理器件10以形成硅化物区8，即，来自源和漏2、3的一部分的区8A，以及来自多晶区4A的区8B。在本实例中，硅化物区8A、8B形成的发生是通过使用两个加热步骤：第一步骤在400和600℃之间，这里大约是540摄氏度，其中钴层7变成了CoSi。接着通过蚀刻去除未反应的钛和未反应的钴。在600和900℃之间进行第二加热步骤，这里大约是850摄氏度。在该步骤中，在区8中形成的CoSi转变成了CoSi2。另一方面，现在区8A有了合适的厚度并且在另一方面，多晶区4A成为了全部硅化的区8B。因此，避免了栅4中的耗尽层效应。
最后(参见图6)通过干法蚀刻去除隔离物6。得到的结构10现在是(又)相对平坦的，尽管制造的中间阶段中的栅堆叠4的高度相当多地大于得到的栅4的高度。通过前金属电介质例如二氧化硅的沉积，接着对其图案化，沉积接触金属层例如铝，接着又对其图案化，进一步完成MOSFET的制造。后者的步骤并未在图中显示。
图7和8是在依靠依据本发明的方法的改进的器件制造中各个阶段的半导体器件的截面图。该方法的绝大部分步骤对应于前面实例中的那些步骤，这里做的描述参考相应于描述的上述部分。图7和8中显示的阶段相应于前面实例中图5的阶段。在第一加热步骤(参见图7)即金属层7已与硅反应之后，从而形成包括CoSi的硅化物区8A、8B，并且在去除未参加反应的残余的钛和钴之后，通过CVD方法在结构10的顶部上沉积薄的多晶硅层44。层44的厚度可以在5到10nm的范围之内。接着(参见图8)进行第二加热步骤，在该步骤中CoSi变成了CoSi2。在该步骤至少部分消耗硅层44并且通过蚀刻步骤去除其中的残余物。在该方法中，减轻了精确确定多晶区4A的要求。参考图9可说明在没有第二实例的步骤的方法中精确确定多晶区4A的厚度的重要性。
图9显示了薄层电阻依据本发明的方法来制造的器件作为栅的半导体区的厚度的函数。连接测量点91的曲线90显示了在这些实验中发现的区8的薄层电阻(ρsh)作为栅4的多晶区4A的厚度(d)的函数。曲线92相应于整体CoSi2的薄层电阻，其等于大约8ohm/方块，CoSi的薄层电阻则更高。因此，很清楚，在该实例中，相应于上述第一实施例中的条件，仅为区4A的厚度大约4nm，实现了想要的完全转化成CoSi2。
很明显本发明并不局限于此处描述的实例，且在本发明范围之内的许多变化和修改对于本技术领域的专业技术人员是可能的。
例如，替代用于牺牲区的氮化硅，也可使用其它合适的材料或材料的组合，比如氮氧化硅或硅和锗的合金。隔离物可(然后)由除了二氧化硅以外的材料构成，例如氮化硅。此外，替代热氧化，可使用沉积的氧化物来形成栅电介质。在良好的改进中，栅电介质包括氮化硅，最好是由CVD沉积的，因为该材料关于硅化处理更稳定。需进一步注意，为形成硅化物，可以用其它金属替代钴，如钛或钼。在单个步骤中进行硅化。半导体主体可由其它半导体材料构成，例如GaAs或锗。在这些情况下，使用多晶或非晶硅栅。

Claims (10)

1.一种具有场效应晶体管的半导体器件(10)的制造方法，在该方法中，提供半导体材料的半导体主体(1)，在其表面具有源区(2)和漏区(3)以及源区(2)和漏区(3)之间的栅区(4)，其中栅区包括通过栅电介质(5)与半导体主体(1)的表面分离的另一半导体材料的半导体区(4A)，并且具有用于形成源和漏区(2，3)的邻近栅区(4)的隔离物(6)，在该方法中，源区(2)和漏区(3)具有用于形成金属和半导体材料化合物(8)的金属层(7)，并且栅区(4)具有用于形成金属和另一半导体材料化合物(8)的金属层(7)，其特征在于，在形成隔离物(6)之前，关于半导体区(4A)可选择性蚀刻的材料的牺牲区(4B)沉积在半导体区(4A)的顶部上，以及在形成隔离物(6)之后，通过蚀刻去除牺牲层(4B)，并且在去除牺牲层(4B)之后，沉积单一金属层(7)与源、漏以及栅区(2，3，4)接触。
2.如权利要求1的方法，其特征在于通过在其上存在包括半导体区(4A)和牺牲区(4B)的栅区(4)的半导体主体(1)的顶部上沉积一层电介质材料，并且接着通过蚀刻去除栅区(4)的顶部和两侧上的沉积层来形成隔离物(6)。
3.如权利要求1或2的方法，其特征在于半导体区(4A)在金属和另一半导体材料化合物(8)的形成期间完全被消耗。
4.如权利要求1、2或3的方法，其特征在于金属与半导体材料和金属与另一半导体材料之间的化合物(8)的形成是在两个分离的加热步骤中进行，第一加热步骤生成具有较低含量的半导体材料或另一半导体材料的中间化合物，而在第二加热步骤中，中间化合物被转变成具有更高含量的半导体材料或另一半导体材料的化合物。
5.如权利要求4的方法，其特征在于在两个加热步骤之间通过蚀刻去除未起反应形成中间化合物的金属层(7)的一部分。
6.如权利要求4或5的方法，其特征在于在两个加热步骤之间，另一半导体材料的层(44)沉积在半导体主体(1)的表面上。
7.如权利要求6的方法，其特征在于在第二加热步骤之后，通过蚀刻去除未起反应形成化合物的另一半导体材料的层(44)的一部分。
8.如前面任一权利要求的方法，其特征在于在形成金属与半导体材料和金属与另一半导体材料的化合物之后，去除隔离物(6)。
9.如前面任一权利要求的方法，其特征在于对于半导体材料和另一半导体材料被选择是硅，对于金属和半导体材料以及另一半导体材料的中间化合物和化合物被选择是金属硅化物。
10.一种半导体器件(10)，包括通过如前面任一权利要求的方法所形成的场效应晶体管。
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WO2004057659A1 (en) 2004-07-08
EP1579488B1 (en) 2011-12-07
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EP1579488A1 (en) 2005-09-28
CN100390939C (zh) 2008-05-28

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