CN1723544A - 在集成电路系统和方法中电气故障的快速定位 - Google Patents

在集成电路系统和方法中电气故障的快速定位 Download PDF

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Publication number
CN1723544A
CN1723544A CNA2003801056803A CN200380105680A CN1723544A CN 1723544 A CN1723544 A CN 1723544A CN A2003801056803 A CNA2003801056803 A CN A2003801056803A CN 200380105680 A CN200380105680 A CN 200380105680A CN 1723544 A CN1723544 A CN 1723544A
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China
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test
pin
parallel
chip
pedestal
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CNA2003801056803A
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English (en)
Chinese (zh)
Inventor
丹尼斯·齐普里卡斯
克里斯托弗·赫斯
谢丽·李
拉格·H·韦兰
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PDF Solutions Inc
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PDF Solutions Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2884—Testing of integrated circuits [IC] using dedicated test connectors, test elements or test circuits on the IC under test
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2894—Aspects of quality control [QC]
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/302—Contactless testing
    • G01R31/305—Contactless testing using electron beams
    • G01R31/307—Contactless testing using electron beams of integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Automation & Control Theory (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Tests Of Electronic Circuits (AREA)
CNA2003801056803A 2002-12-11 2003-12-11 在集成电路系统和方法中电气故障的快速定位 Pending CN1723544A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US43278602P 2002-12-11 2002-12-11
US60/432,786 2002-12-11

Publications (1)

Publication Number Publication Date
CN1723544A true CN1723544A (zh) 2006-01-18

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Country Link
US (1) US7527987B2 (enExample)
EP (1) EP1570510A2 (enExample)
JP (1) JP2006515464A (enExample)
CN (1) CN1723544A (enExample)
AU (1) AU2003297025A1 (enExample)
WO (1) WO2004053944A2 (enExample)

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CN102375092A (zh) * 2010-08-05 2012-03-14 富士通株式会社 多层布线板和评估多层布线板的方法
CN101576565B (zh) * 2008-05-09 2013-07-10 上海华碧检测技术有限公司 集成电路缺陷定位测试系统
CN105264640A (zh) * 2013-04-07 2016-01-20 科磊股份有限公司 用于线内合格率监测的关键参数电测试参数的自动确定的系统及方法
CN107861045A (zh) * 2017-10-13 2018-03-30 天津市英贝特航天科技有限公司 一种基于直流ct技术的短路芯片查找装置及方法
CN110398617A (zh) * 2018-04-25 2019-11-01 晶豪科技股份有限公司 测试装置及折叠探针卡测试系统

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CN102148132B (zh) * 2010-11-19 2013-02-27 上海微曦自动控制技术有限公司 光学检测装置
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TW201418738A (zh) 2012-11-02 2014-05-16 Kinsus Interconnect Tech Corp 終端檢驗系統
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US10199283B1 (en) 2015-02-03 2019-02-05 Pdf Solutions, Inc. Method for processing a semiconductor wager using non-contact electrical measurements indicative of a resistance through a stitch, where such measurements are obtained by scanning a pad comprised of at least three parallel conductive stripes using a moving stage with beam deflection to account for motion of the stage
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US9929063B1 (en) 2016-04-04 2018-03-27 Pdf Solutions, Inc. Process for making an integrated circuit that includes NCEM-Enabled, tip-to-side gap-configured fill cells, with NCEM pads formed from at least three conductive stripes positioned between adjacent gates
US9627370B1 (en) 2016-04-04 2017-04-18 Pdf Solutions, Inc. Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least via-open-configured, GATE-short-configured, GATECNT-short-configured, and TS-short-configured, NCEM-enabled fill cells
TWI598610B (zh) * 2017-02-16 2017-09-11 致茂電子股份有限公司 通用控制系統
US9748153B1 (en) 2017-03-29 2017-08-29 Pdf Solutions, Inc. Process for making and using a semiconductor wafer containing first and second does of standard cell compatible, NCEM-enabled fill cells, with the first DOE including side-to-side short configured fill cells, and the second DOE including tip-to-side short configure
US9773774B1 (en) 2017-03-30 2017-09-26 Pdf Solutions, Inc. Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including chamfer short configured fill cells, and the second DOE including corner short configured fill cells
US9768083B1 (en) 2017-06-27 2017-09-19 Pdf Solutions, Inc. Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including merged-via open configured fill cells, and the second DOE including snake open configured fill cells
US9786649B1 (en) 2017-06-27 2017-10-10 Pdf Solutions, Inc. Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including via open configured fill cells, and the second DOE including stitch open configured fill cells
US10096530B1 (en) 2017-06-28 2018-10-09 Pdf Solutions, Inc. Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including merged-via open configured fill cells, and the second DOE including stitch open configured fill cells
US9865583B1 (en) 2017-06-28 2018-01-09 Pdf Solutions, Inc. Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including snake open configured fill cells, and the second DOE including stitch open configured fill cells
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Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101576565B (zh) * 2008-05-09 2013-07-10 上海华碧检测技术有限公司 集成电路缺陷定位测试系统
CN101820285A (zh) * 2009-01-07 2010-09-01 英特赛尔美国股份有限公司 改进的n位管脚adc阅读器
CN101820285B (zh) * 2009-01-07 2014-08-20 英特赛尔美国股份有限公司 改进的n位管脚adc阅读器
CN102375092A (zh) * 2010-08-05 2012-03-14 富士通株式会社 多层布线板和评估多层布线板的方法
CN105264640A (zh) * 2013-04-07 2016-01-20 科磊股份有限公司 用于线内合格率监测的关键参数电测试参数的自动确定的系统及方法
CN105264640B (zh) * 2013-04-07 2018-02-27 科磊股份有限公司 用于线内合格率监测的关键参数电测试参数的自动确定的系统及方法
CN107861045A (zh) * 2017-10-13 2018-03-30 天津市英贝特航天科技有限公司 一种基于直流ct技术的短路芯片查找装置及方法
CN110398617A (zh) * 2018-04-25 2019-11-01 晶豪科技股份有限公司 测试装置及折叠探针卡测试系统
CN110398617B (zh) * 2018-04-25 2022-03-25 晶豪科技股份有限公司 测试装置及折叠探针卡测试系统

Also Published As

Publication number Publication date
WO2004053944A3 (en) 2004-11-04
US20060105475A1 (en) 2006-05-18
US7527987B2 (en) 2009-05-05
EP1570510A2 (en) 2005-09-07
WO2004053944A2 (en) 2004-06-24
AU2003297025A8 (en) 2004-06-30
JP2006515464A (ja) 2006-05-25
AU2003297025A1 (en) 2004-06-30

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