CN1717617A - 薄膜晶体管衬底及其制造方法、具有其的液晶显示装置以及制造该液晶显示装置的方法 - Google Patents

薄膜晶体管衬底及其制造方法、具有其的液晶显示装置以及制造该液晶显示装置的方法 Download PDF

Info

Publication number
CN1717617A
CN1717617A CNA2003801045955A CN200380104595A CN1717617A CN 1717617 A CN1717617 A CN 1717617A CN A2003801045955 A CNA2003801045955 A CN A2003801045955A CN 200380104595 A CN200380104595 A CN 200380104595A CN 1717617 A CN1717617 A CN 1717617A
Authority
CN
China
Prior art keywords
electrode pad
salient point
conductive
thin film
film transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CNA2003801045955A
Other languages
English (en)
Inventor
黄星龙
吴元植
尹胄永
姜圣哲
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of CN1717617A publication Critical patent/CN1717617A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333Constructional arrangements; Manufacturing methods
    • G02F1/1345Conductors connecting electrodes to cell terminals
    • G02F1/13454Drivers integrated on the active matrix substrate
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333Constructional arrangements; Manufacturing methods
    • G02F1/1345Conductors connecting electrodes to cell terminals
    • G02F1/13452Conductors connecting driver circuitry and terminals of panels
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333Constructional arrangements; Manufacturing methods
    • G02F1/1345Conductors connecting electrodes to cell terminals
    • G02F1/13458Terminal pads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2202/00Materials and properties
    • G02F2202/02Materials and properties organic material
    • G02F2202/022Materials and properties organic material polymeric
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0556Disposition
    • H01L2224/05568Disposition the whole external layer protruding from the surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05573Single external layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/1301Shape
    • H01L2224/13012Shape in top view
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/1301Shape
    • H01L2224/13016Shape in side view
    • H01L2224/13018Shape in side view comprising protrusions or indentations
    • H01L2224/13019Shape in side view comprising protrusions or indentations at the bonding interface of the bump connector, i.e. on the surface of the bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354Coating
    • H01L2224/13575Plural coating layers
    • H01L2224/1358Plural coating layers being stacked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354Coating
    • H01L2224/13599Material
    • H01L2224/136Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119Arrangement of the bump connectors prior to mounting
    • H01L2224/81193Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818Bonding techniques
    • H01L2224/81801Soldering or alloying
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01005Boron [B]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01006Carbon [C]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01013Aluminum [Al]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01022Titanium [Ti]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01024Chromium [Cr]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/0103Zinc [Zn]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01033Arsenic [As]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01042Molybdenum [Mo]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01049Indium [In]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/0105Tin [Sn]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01057Lanthanum [La]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01058Cerium [Ce]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01073Tantalum [Ta]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01074Tungsten [W]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01082Lead [Pb]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701Low temperature co-fired ceramic [LTCC]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits

Abstract

导电凸点包括多个凸出元件(251)和形成在该凸出元件上的导电层(252),并设置在TFT衬底(200)上。每个凸出元件设置在TFT衬底的焊盘区域(292,293)中的电极焊盘(270a、b,280a、b)上,并且导电层电连接到电极焊盘。非导电树脂(600)设置在导电凸点上,驱动IC(500)热压在导电凸点上。所以,驱动IC和电极焊盘之间的电接触特性得到了提高。

Description

薄膜晶体管衬底及其制造方法、具有其的液晶显示装置 以及制造该液晶显示装置的方法
技术领域
本申请涉及薄膜晶体管(以下简称TFT)衬底及制造其的方法、具有该TFT衬底的液晶显示(以下简称LCD)装置及制造该LCD装置的方法。更具体地,本发明涉及能够提高驱动集成电路(IC)和电极焊盘之间的电接触的TFT衬底、制造其的方法、具有该TFT衬底的LCD装置以及制造该LCD装置的方法。
背景技术
图1是图示了LCD装置中在LCD面板和驱动IC之间传统的玻璃基芯片(chip-on-glass,COG)结合结构的横截面视图。
参考图1,在LCD面板10的焊盘区域中的电极焊盘12由各向异性的导电层30电连接到驱动IC 20的电极。
多个电极焊盘12排布在绝缘衬底11上所确定的焊盘区域中,并且各个电极焊盘12以预定的距离彼此间隔开。电极焊盘12电连接到驱动IC,以接收驱动LCD面板10的驱动信号。
作为示范性实施方案,各向异性导电膜(ACF)30包括含有多个导电球31的热固性树脂。导电球31布置在电极焊盘12和驱动IC 20的电极21之间,从而电极焊盘12和驱动IC 20可以相互进行电接触。此外,ACF 30使驱动IC 20粘附于电极焊盘12,使得电极焊盘12和驱动IC 20之间的电接触可以得到确保或维持。
下面,将示意性地介绍使用ACF 30以电连接电极焊盘12和驱动IC 20的传统COG结合工艺。
首先,将ACF 30置于每个电极焊盘12之上,然后放置驱动IC 20使得它的电极21与每个电极焊盘12一一对应。之后,将驱动IC 20向下热压到电极焊盘12上。因此,导电球31被压缩在电极焊盘12和驱动IC 20的电极21之间,从而电极焊盘12与驱动IC 20进行电接触。ACF 30通过热压工艺软化,并从热压工艺完成时逐渐硬化。由于ACF 30的硬化,驱动IC 20牢固地粘附于电极焊盘12,使得驱动IC 20通过中间的导电球31与电极焊盘12具有好的接触。
发明内容
因为ACF 30昂贵,所以COG结合结构并不低廉,因此增加了LCD装置的制造成本。
而且,COG结合结构还在驱动IC 20和电极焊盘12之间造成错位以及短路。该错位导致从驱动IC 20到电极焊盘12的驱动信号传输失败。
通常,在电极焊盘之间或在驱动IC 20的电极之间的空间并不完全均匀或一致,所以ACF 30的导电球31在驱动IC 20的热压期间未必就位于驱动IC 20的电极和电极焊盘12之间。因此,驱动IC 20可能由于没有导电球31而没有电连接到对应的电极焊盘12上,使得用于驱动LCD面板的驱动信号没有从驱动IC 20传输到电极焊盘12。
同时,导电球31可能过度地聚集在驱动IC 20和电极焊盘12之间,使得过多的电流可能被施加在驱动IC 20和电极焊盘12之间。即,由于在电极焊盘12和驱动IC 20之间导电球过度的积聚而可能导致短路。
本发明提供了一种TFT衬底,它能够提高驱动IC与在其焊盘区域中的电极焊盘之间的电接触。
本发明还提供了一种制造该TFT衬底的方法。
本发明还提供了一种具有该TFT衬底的LCD装置。
本发明还提供了一种制造该LCD装置的方法。
根据本发明一个示范性实施方案的TFT衬底包括多个电极焊盘和导电凸点。该电极焊盘形成在布置于衬底上的栅线路和数据线路的端部上。该导电凸点包括凸出元件和导电涂层。导电凸点通过使用非导电树脂电连接到为电极焊盘施加预定信号的驱动IC上。具有预定厚度的凸出元件设置在电极焊盘上。电连接到电极焊盘的导电涂层设置在凸出元件上。
凸出元件包括弹性有机材料。该凸出元件可以包括由预定距离间隔开的多个凸起,并设置在电极焊盘上使得电极焊盘的一部分通过凸起之间的空间暴露或使得电极焊盘的外围部分被暴露。凸起元件包括在其上表面上的凹凸图案。
根据本发明一个方面的制造TFT衬底的方法包括形成栅线路、数据线路、以及多个电极焊盘,和形成导电凸点。多个电极焊盘形成在衬底上的栅线路和数据线路端部上。导电凸点形成在电极焊盘上,并通过使用非导电树脂电连接到用于向电极焊盘施加预定信号的驱动IC上。该导电凸点包括凸出元件和导电涂层。非导电树脂设置在导电凸点和驱动IC之间。凸出元件具有预定厚度,形成在电极焊盘上。导电涂层电连接到电极焊盘,形成在凸出元件上。
根据本发明另一个方面的制造TFT衬底的方法包括形成光致抗蚀剂有机层、对该光致抗蚀剂有机层构图、形成导电层以及对该导电层构图。作为示范性实施方案,将光致抗蚀剂有机层涂覆在像素区域和焊盘区域,然后对其构图,从而在像素区域上形成绝缘薄膜和在焊盘区域上形成凸出元件。绝缘薄膜保护多个TFT和导电线路,并且凸出元件形成在电极焊盘上。将导电层沉积并构图于绝缘层和凸出元件上,使得在绝缘层上形成像素电极,在凸出元件上形成导电涂层。
根据本发明的一个方面的LCD装置包括具有多个TFT和电连接到该TFT的导电线路的像素区域、和具有多个电极焊盘的焊盘区域,该LCD装置包括LCD面板、驱动ICD和粘附元件。该LCD面板包括TFT衬底、面向TFT衬底的滤色器衬底以及介于该TFT衬底和滤色器衬底之间的液晶层。TFT衬底包括凸出元件和导电凸点。凸出元件设置在电极焊盘上,导电凸点设置在凸出元件上。导电凸点包括电连接到电极焊盘的导电涂层。
驱动IC电连接到导电凸点并将预定信号施加到电极焊盘。
粘附元件设置在导电凸点和驱动IC之间,并将驱动IC粘附到导电凸点以确保导电凸点和驱动IC之间的电连接。
凸出元件包括弹性有机材料。凸出元件可以包括由预定距离隔开的多个凸起,并设置在电极焊盘上使得电极焊盘的一部分通过凸起之间的空间暴露或使得电极焊盘的外围部分被暴露。凸起元件包括在其上表面上的凹凸图案。
粘附元件是一非导电树脂,该非导电树脂在对驱动集成电路的热压工艺期间软化,并从热压工艺完成时逐渐硬化。所以,通过使用驱动IC在其硬化期间的收缩将驱动IC粘附到导电凸点。
根据本发明一个示范性实施例的制造LCD装置的方法,其中该LCD装置包括具有多个薄膜晶体管和连接到所述薄膜晶体管的导电线路的像素区域,以及具有多个电极焊盘的焊盘区域,该方法是通过执行如下步骤进行的:形成包括凸出元件和导电元件的TFT衬底,形成滤色器衬底,形成液晶层,以及将驱动IC连接到导电凸点。凸出元件形成在电极焊盘上。导电凸点形成在凸出元件上,并具有电连接到电极焊盘的导电涂层。滤色器衬底与TFT衬底相对组合。液晶层介于TFT衬底和滤色器衬底之间。驱动IC用于向电极焊盘施加预定信号,并通过使用粘附元件电连接到导电凸点。
导电层包括铟锡氧化物(ITO)、铟锌氧化物(IZO)、或金属。导电层可以包括具有第一层和第二层的叠层。第一层包括ITO或IZO,第二层包括金属。
绝缘层包括有机绝缘层或无机绝缘层。优选地,绝缘层可以包括有机绝缘层。
通过上述示范性实施方案,在驱动IC安装在TFT衬底的焊盘区域上时,弹性导电凸点设置在每个电极焊盘上,非导电树脂介于驱动IC和导电凸点之间用于将驱动IC电连接到导电凸点上。所以,驱动IC和电极焊盘之间的电接触特性得到了提高。
附图说明
当结合附图考虑时,参考下面详细的描述,本发明的上述及其他优点将变得更加清楚,在附图中:
图1是图示了LCD装置中在LCD面板和驱动IC之间传统的玻璃基芯片(COG)结合结构的横截面视图;
图2是图示了根据本发明一个示范实施方案的LCD装置的平面图;
图3是沿图2的线I-I’所截取的横截面视图;
图4是图示图2的TFT衬底的平面图;
图5是沿图4的线II-II’截取的横截面视图;
图6是图示图5的导电凸点一部分的部分放大图;
图7是图示根据本发明一个示范实施方案的导电凸点和驱动IC之间的结合结构的横截面视图;
图8A和8B是图示根据本发明一个示范实施方案的栅焊盘区域和数据焊盘区域的横截面视图;
图9A和9B是图示根据本发明一个示范实施方案的栅焊盘区域和数据焊盘区域的横截面视图;
图10A到10D是图示根据本发明一个示范实施方案的制造TFT衬底的方法的横截面视图;
图11A和图11B是图示根据本发明一个示范实施方案的制造TFT衬底的方法的横截面视图;
图12A和图12B是图示根据本发明一个示范实施方案的制造TFT衬底的方法的横截面视图。
具体实施方式
现在,下面将通过参考附图对本发明进行更加全面的说明,在附图中示出了本发明示范性实施方案。但是,本发明可以以许多不同的形式实现,并不应当解释为限于本文所描述的实施方案。
图2是图示了根据本发明第一实施方案的LCD装置的平面图;图3是沿图2的线I-I’所截取的横截面视图。
参考图2和图3,根据本发明第一实施方案的LCD装置100包括具有TFT衬底200、滤色器衬底300和液晶层400的LCD面板,该液晶层400布置在TFT衬底200和滤色器衬底300之间。
LCD面板包括在其中滤色器衬底与TFT衬底相重叠的像素区域291,以及在其中滤色器衬底与TFT衬底不相重叠的焊盘区域292和293。
焊盘区域包括向像素区域291施加栅信号的栅焊盘区域292,以及向像素区域291施加数据信号的数据焊盘区域293。
所以,如图3所示,像素区域包括TFT衬底200、对应于该TFT衬底200的滤色器衬底300,以及介于TFT衬底200和滤色器衬底300之间的液晶层400,使得图像能够显示在像素区域291中。
TFT衬底200包括第一绝缘衬底210、置于第一衬底210之上的多个TFT220、有机或无机绝缘层230、以及像素电极240。绝缘层230以预定的厚度设置在每个TFT 220之上。像素电极240以均匀的厚度设置在绝缘层230之上。
TFT 220包括从在第一绝缘衬底210上沿第一方向延伸的栅线路(未示出)分出的栅电极221,置于栅电极221之上的栅绝缘层222,依次堆叠在栅绝缘层222之上对应于栅电极221的半导体和欧姆接触层223和224,以及从在第一绝缘衬底210上沿与第一方向垂直的第二方向延伸的数据线(未示出)分出的源电极225和漏电极226。
像素区域240是透明的或反射的导电层,其具有比如ITO和IZO的材料、金属层、或它们的组合。该导电层也是叠层,在其中透明的导电层和金属层交替叠加。
接触孔235形成在绝缘层230之上以暴露漏电极226的部分,从而像素电极240通过接触孔235电连接到漏电极226。
滤色器衬底300包括第二绝缘衬底310、置于第二绝缘衬底310之上的滤色器层320,以及置于滤色器层320之上的公共电极330。滤色器层320包括红、绿和蓝滤色器。公共电极330以均匀的厚度设置在滤色器层320之上。
栅焊盘区域292包括置于第一绝缘衬底210之上的栅电极焊盘270a和270b,置于栅电极焊盘270a和270b之上的多个第一导电凸点250,电连接到第一导电凸点250的驱动IC 500,以及用于将驱动IC粘附于第一导电凸点250从而确保驱动IC和第一导电凸点250之间的电连接的非导电树脂600。每个第一导电凸点250包括第一凸出元件251和第一导电涂层252。
数据焊盘区域293包括在第一绝缘衬底210之上的数据电极焊盘280a和280b,置于数据电极焊盘280a和280b之上的多个第一导电凸点250,电连接到第一导电凸点250的驱动IC 500,以及用于将驱动IC粘附于第一导电凸点250从而确保驱动IC和第一导电凸点250之间的电连接的非导电树脂600。每个第一导电凸点250包括第一凸出元件251和第一导电涂层252。
驱动IC 500包括电连接到第一导电凸点250的多个电极510。每个电极510与第一导电凸点250一一对应,并且电连接到第一导电凸点250。
驱动IC 500通过热压工艺或其他适当的方法安装在栅焊盘区域292和数据焊盘区域293之上。非导电树脂600在热压工艺期间在驱动IC上软化,然后从热压工艺完成时逐渐硬化。所以,驱动IC 500通过非导电树脂600由于其硬化所导致的收缩而在经过预定时间之后粘附于第一导电凸点250。也就是说,驱动IC 500的电极牢固地粘附于第一导电凸点250,使得第一导电凸点和驱动IC 500之间的电连接可得以确保。
图4是图示图2的TFT衬底的平面图,图5是沿图4的线II-II’截取的横截面视图。现在参考图4和图5中的具体细节,其中同样的参考标记用于指代图2和图3中同样的元件,并且因此,除LCD装置100的像素区域291、栅焊盘区域292和数据焊盘区域293以外,省略了关于同样元件的任何更进一步的详细说明。
参考图4和图5,TFT衬底200包括多个栅线路270和数据线路280,以及多个TFT 220。栅线路270沿第一方向延伸,数据线路280沿第二方向延伸,使得栅线路270和数据线路280彼此相交从而以矩阵形状布置。每个TFT 220设置于栅线路270和数据线路280的交叉区域。每个TFT 220包括从栅线路270分出的栅电极221,以及从数据线路280分出的源电极225和漏电极226。栅电极焊盘270a形成在每条栅线路270的端部,数据电极焊盘280a形成在每条数据线路280的端部。所以,TFT衬底200被划分为显示图像的像素区域291,在其上设置有栅电极焊盘270a的栅焊盘区域292,以及在其上设置有数据电极焊盘280a的数据焊盘区域293。栅焊盘区域和数据焊盘区域形成在像素区域291的外围部分中。
栅电极焊盘270a和多个第一导电凸点250形成在栅焊盘区域292之上。每个第一导电凸点250包括以预定深度设置在栅电极焊盘270a之上的第一凸出元件251,和置于第一凸出元件251之上的第一导电涂层252。第一导电涂层252电连接到栅电极焊盘270a。
栅绝缘层222、数据电极焊盘280a和多个第一导电凸点250形成在数据焊盘区域293之上。每个第一导电凸点250包括以预定厚度放置在数据电极焊盘280a之上的第一凸出元件251,和置于第一凸出元件251之上的第一导电涂层252。第一导电涂层252电连接到数据电极焊盘280a。
栅电极焊盘270a和数据电极焊盘280a分别设置在栅线路270和数据线路280的端部。此外,栅电极焊盘270a和数据电极焊盘280a要分别宽于栅线路270和数据线路280。
在栅电极焊盘270a或数据电极焊盘280a之上的第一凸出元件251包括与沉积在TFT 220上像素区域291中的绝缘层230基本上相同的材料。置于第一凸出元件251之上的第一导电涂层252包括与沉积在对应于像素区域291的绝缘层230上的像素电极层基本相同的材料。
所以,当使用具有ITO或IZO的透明导电层形成像素电极240时,第一导电涂层252是透明导电层;当使用金属层形成像素电极240时,第一导电涂层252是金属层。此外,当使用透明导电层和金属层的叠层形成像素电极240时,第一导电涂层252可以是透明导电层、金属层或透明导电层和金属层的叠层。
将包括导电凸点250的TFT衬底安装到液晶显示装置。图4和图5所示的包括导电凸点250的TFT衬底可以安装到另外的平面显示装置,例如有机电致发光显示装置,如本领域普通技术人员将所知的那样。
图6是图示图5的导电凸点一部分的部分放大图。
参考图5和图6,在栅焊盘区域292中的第一导电凸点250包括第一凸出元件251以及置于第一凸出元件251之上的第一导电涂层252。
第一凸出元件251以预定厚度置于形成在栅线路270端部的栅电极焊盘270a之上。第一凸出元件251的宽度要小于栅电极焊盘270a的宽度,并且第一凸出元件251的底表面积也要小于栅电极焊盘270a的表面积,使得栅电极焊盘270a的外围部分被暴露。导电涂层252形成在第一凸出元件251之上,并且电连接到栅电极焊盘270a暴露的外围部分。
以与栅焊盘区域292上的第一导电凸点同样的方式,数据焊盘区域293上的第一导电凸点250也包括第一凸出元件251以及置于第一凸出元件251之上的第一导电涂层252。第一凸出元件置于数据电极焊盘280a之上,表面积小于数据电极焊盘280a的表面积,使得数据电极焊盘280a的外围部分被暴露。第一导电涂层252形成在第一凸出元件251之上,并且电连接到数据电极焊盘280a的外围部分。
图7是图示根据本发明第一实施方案的导电凸点和驱动IC之间的结合结构的横截面视图。
参考图7,驱动IC 500通过介于第一导电凸点250和驱动IC 500之间的中间非导电树脂600电连接到第一导电凸点250。
第一导电凸点250以第一厚度(T1)形成在栅电极焊盘270a之上,然后与驱动IC 500一同热压,使得导电凸点250电连接到驱动IC 500。由于第一导电凸点250的第一凸出元件251包括弹性有机绝缘材料,在热压工艺期间,第一凸出元件251被压缩至第二厚度(T2)。
作为将驱动IC 500粘附到第一导电凸点250的粘附元件的示范性实施方案,非导电树脂600介于第一导电凸点250和驱动IC 500的电极510之间,使得驱动IC 500粘附到第一导电凸点250,从而充分确保驱动IC 500和第一导电凸点250之间的电连接。
在进行热压工艺时,非导电树脂600软化,介于电极510和第一导电凸点250之间的一部分非导电树脂被向外挤出到邻近导电凸点250和电极510的空间。非导电树脂600从热压工艺完成时逐渐硬化,使得非导电树脂600收缩并最终硬化为预定的形状。因此,第一导电凸点250仍保持被压缩至第二厚度T2,并因此与驱动IC 500的电极510电连接。
当非导电树脂600硬化时,非导电树脂600沿第一方向D1和第二方向D2收缩,使得驱动IC 500和第一导电凸点250之间的粘附力通过非导电树脂600的收缩而得到增强。
根据传统的结合结构,在第一导电凸点和驱动IC之间产生的电阻生热增加了非导电树脂的温度,该非导电树脂并因此而热膨胀。所以,由于非导电树脂的热膨胀,栅电极焊盘和驱动IC之间的距离从而变宽,使得栅电极焊盘和驱动IC之间的电连接断开。本发明的上述结合结构即使非导电树脂600热膨胀也可以确保栅电极焊盘和驱动IC之间的电连接。第一导电凸点250包括弹性材料,并且驱动IC 500以压缩厚度T2压焊到导电凸点250。所以,第一导电凸点250的回复可以补偿栅电极焊盘270a和驱动IC 500之间由于非导电树脂600的热膨胀而导致的距离增加,使得栅电极焊盘270a和驱动IC 500之间的电连接可以充分地得到确保。
除非导电树脂600的热膨胀以外,许多其他的因素,例如,对第一导电凸点250和驱动IC之间边界表面的撞击,以及非导电树脂对第一导电凸点250和驱动IC 500粘附力的减弱,也可以增加栅电极焊盘270a和驱动IC 500之间的距离。第一导电凸点250也可以对应于由于上述其他因素所导致的距离增加而回复,使得栅电极焊盘270a和驱动IC 500之间的电连接也可以充分地得到确保。
图8A和8B是图示根据本发明另一个实施方案的栅焊盘区域和数据焊盘区域的横截面视图。现在参考图8A和8B中具体的细节,其中,同样的参考标记指代图2和图3中同样的元件,因此省略了关于这些同样元件的任何更进一步的详细说明。
参考图8A,根据本发明另一个实施方案的栅焊盘区域292包括第一衬底210,置于第一衬底210之上的栅电极焊盘270a,以及多个第二导电凸点250a。每个第二导电凸点250a包括置于栅电极焊盘270a之上的第二凸出元件251a以及置于第二凸出元件251a之上的第二导电涂层252a。
如图4所示,栅电极焊盘270a置于第一衬底210上栅线路270的端部上,并具有预定的表面积。
多个第二凸出元件251a通过预定的距离分隔开而设置在栅电极焊盘270a之上。所以,当在包括第二凸出元件251a的栅电极焊盘270a的平面图中查看其时,第二凸出元件251a被表示为设置在栅电极焊盘270a上的多个点。
栅电极焊盘270a的部分通过第二凸出元件251a之间的空间暴露,并且栅电极焊盘270a被暴露的部分电连接到第二导电涂层252a。
参考图8B,根据本发明另一个实施方案的数据焊盘区域293包括形成在第一衬底210上的栅绝缘层222,置于栅绝缘层222之上的数据电极焊盘280a,以及多个第二导电凸点250a。每个第二导电凸点250a包括置于数据电极焊盘280a之上的第二凸出元件251a以及置于第二凸出元件251a之上的第二导电涂层252a。
数据电极焊盘280a以与上述栅电极焊盘270a同样的方法置于绝缘层222上数据线路280的端部上,并具有预定的表面积。
由于在数据电极焊盘280a上的第二导电凸点250a与在栅电极焊盘270a上的第二导电凸点250a基本上相同,所以下面就省略了关于在数据电极焊盘280a上的第二导电凸点250a任何更进一步的详细说明。
第二导电涂层252a如图5所示的第一导电涂层252可以是透明导电层、金属层或透明导电层和金属层的叠层,并电连接到栅电极焊盘270a和数据电极焊盘280a。
每个第二导电凸点250a包括从栅电极焊盘270a和数据电极焊盘280a凸出的凸起,并含有弹性材料。每个凸起可以单独地被压缩从而彼此具有不同的高度。即使驱动IC的电极彼此不均匀,第二导电凸点250a的每个凸起也根据驱动IC每个电极的厚度而被压缩来具有不同高度,使得第二导电凸点250a分别被压缩为不同的厚度。所以,不管驱动IC电极的非均匀性,驱动IC和第二导电凸点之间的电连接都可以稳定地得到确保。
图9A和9B是图示根据本发明另一个实施方案的栅焊盘区域和数据焊盘区域的横截面视图。
现在参考图9A和9B中具体的细节,其中,同样的参考标记指代图8A和8B中同样的元件,因此省略了关于这些同样元件的任何更详细的说明。即使在图9A中示范性地示出了栅电极焊盘和其上的导电凸点,但是多个栅电极焊盘和导电凸点可以设置在衬底上。同样,即使在图9B中示范性地示出了数据电极焊盘和其上的导电凸点,但是多个数据电极焊盘和导电凸点也可以设置在衬底上。
参考图9A,栅焊盘区域292包括第一衬底210,置于第一衬底210之上的栅电极焊盘270a,以及第三导电凸点250b。第三导电凸点250b包括置于栅电极焊盘270a之上的第三凸出元件251b以及置于第三凸出元件251b之上的第三导电涂层252b。
在第三凸出元件251b的上表面上形成具有多个凹入部分和多个凸出部分的凹凸图案。第三导电涂层252b根据该凹凸图案的形状以均匀的厚度形成在第三凸出元件251b上,以及形成在栅电极焊盘270a之上,使得第三导电涂层252b连接到邻近第三凸出元件251b的侧表面的栅电极焊盘270a暴露的部分。
参考图9B,数据焊盘区域293包括形成在第一衬底210之上的栅绝缘层222,置于栅绝缘层222之上的数据电极焊盘280a,以及第三导电凸点250b。第三导电凸点250b包括置于数据电极焊盘280a之上的第三凸出元件251b以及置于第三凸出元件251b之上的第三导电涂层252b。
由于在数据电极焊盘280a上的第三导电凸点250b与在栅电极焊盘270a上的第三导电凸点250b基本上相同,所以下面就省略了关于在数据电极焊盘280a上的第三导电凸点250b任何更加详细的说明。
第三导电涂层252b如图5所示的第一导电涂层252可以是透明导电层、金属层或透明导电层和金属层的叠层,并电连接到栅电极焊盘270a和数据电极焊盘280a。
当驱动IC安装到上述第三导电凸点时,凹凸图案的凸出部分与驱动IC的电极接触。所以,即使驱动IC的电极厚度不均匀,驱动IC和第二导电凸点之间的电连接也可以稳定地得到确保。
图10A到10D是图示根据本发明实施方案的制造TFT衬底的方法的横截面视图。
参考图4和图10A,第一金属层包括一种金属,例如,铝(Al)、钼(Mo)、铬(Cr)、钽(Ta)、钛(Ti)、铜(Cu)、钨(W)等,其沉积在第一衬底210上,第一衬底210包括比如玻璃、陶瓷等的绝缘材料。
第一衬底210包括用于显示图像的像素区域291、用于接收栅信号的栅焊盘区域292、和用于接收数据信号的数据焊盘区域293。栅焊盘区域和数据焊盘区域设置在第一衬底210的外围部分。
对第一金属层构图,从而多条栅线路270在第一衬底210上沿第一方向延伸,并彼此由预定距离分开。栅电极221从每条栅线路270分出,栅电极焊盘270a形成在每条栅线路270的端部。所以,栅电极焊盘270a形成在被称为栅焊盘区域292的像素区域291的外围部分。作为示范性实施方案,栅电极焊盘270a的表面积被形成得大于栅电极221和栅线路270的表面积。
随后,通过等离子体化学气相沉积(CVD)工艺在第一衬底210的整个表面上沉积氮化硅(SiNx),从而在栅线路270、栅电极221和栅电极焊盘270a上形成栅绝缘层222。
如图10B所示,通过等离子体CVD工艺以此在栅绝缘层222上依次沉积非晶硅和原位掺杂的N+非晶硅,从而形成非晶硅和N+非晶硅的叠层。然后,对该叠层构图,并且将半导体层223和欧姆接触层224形成在对应于栅电极221的栅绝缘层222的部分上。
第二金属层沉积在第一衬底210的整个表面上,其上形成有半导体层223和欧姆接触层224。第二金属层包括铝(Al)、钼(Mo)、铬(Cr)、钽(Ta)、钛(Ti)、铜(Cu)或钨(W)。对第二金属层构图,从而多条数据线路280在栅绝缘层222上沿垂直于第一方向的第二方向延伸,并彼此由预定距离分开。然后,如图4所示,形成从每条数据线路280分出的源电极225、在第二方向上面向该源电极的漏电极226。而且,数据电极焊盘280a形成在每条数据线路280的端部。所以,数据电极焊盘280a形成在被称为数据焊盘区域293的像素区域291的外围部分。作为示范性实施方案,数据电极焊盘280a的表面积被形成得大于数据线路280的表面积。
因此,在第一衬底210的像素区域291上形成了多个TFT,并且每个TFT包括栅电极221、半导体层223、欧姆接触层224、源电极225和漏电极226。栅电极焊盘270a和数据电极焊盘280a分别形成在栅焊盘区域292和数据焊盘区域293上。
之后,如图10C和图10D所示,以预定厚度在第一衬底210的整个表面上沉积光致抗蚀材料,使得在像素区域291、栅焊盘区域292和数据焊盘区域293上形成光致抗蚀剂层231。
在光致抗蚀剂层231上设置具有第一透明区域710和第一遮蔽区域720的第一掩模700,并且通过使用第一掩模700的光刻工艺以选择性地去除光致抗蚀剂层231。所以,在像素区域291中形成有机或无机绝缘层230,在栅焊盘区域292和数据焊盘区域293中形成第一凸出元件251。绝缘层230包括用于暴露部分漏电极226的接触孔235,并且第一凸出元件251暴露栅焊盘区域292中栅电极焊盘270a的外围部分和暴露数据焊盘区域293中数据电极焊盘280a的外围部分。
在有机或无机绝缘层230和第一凸出元件251上沉积比如ITO、IZO等的透明导电材料、比如铝-钕(AlNd)、钼-钨(MoW)的金属、或反射材料,等等,从而形成透明导电层或金属层。对该透明导电层或金属层构图以形成像素电极(未示出)和第一导电涂层(未示出)。否则,通过对包括透明导电层和金属层的叠层构图,可以将该像素电极和第一导电涂层形成为叠层结构。所以,形成了如图5所示的TFT衬底200。
然后,TFT衬底200相对地与滤色器衬底300组合,并由预定距离隔开以在它们之间注入液晶。即,TFT衬底200、面向该TFT衬底200的滤色器衬底300、和介于该TFT衬底和滤色器衬底之间的液晶层构成了如图3所示的液晶显示装置100。
图11A和图llB是图示根据本发明另一个实施方案的制造TFT衬底的方法的横截面视图。
参考图11A和图11B,光致抗蚀剂层231以对图10C中示出的光致抗蚀剂层所述同样的方法涂覆在第一衬底210上。在光致抗蚀剂层231上放置具有第二透明区域810和第二遮蔽区域820的第二掩模800,并且通过使用第二掩模800的光刻工艺以选择性地去除光致抗蚀剂层231。所以,在像素区域291中形成绝缘层230,在栅焊盘区域292和数据焊盘区域293中以均匀的高度形成多个第二凸出元件251a。有机或无机绝缘层230包括用于暴露部分漏电极226的接触孔235,并且第二凸出元件251a暴露栅焊盘区域282中栅电极焊盘270a的外围部分和暴露数据焊盘区域283中数据电极焊盘280a的外围部分。
多个第二遮蔽区域820以预定表面积设置在栅电极焊盘270a或数据电极焊盘280a之上。第二透明区域810将各个第二遮蔽区域820彼此隔开。所以,第二凸出元件251a对应于第二遮蔽区域820形成为由预定距离隔开的凸起。
由于第二透明区域810下面的光致抗蚀剂层231在光刻工艺期间被去除,所以使在第二凸出元件251a之间的栅电极焊盘270a和数据电极焊盘280a部分暴露出来。
在有机或无机绝缘层230和第二凸出元件251a上沉积比如ITO、IZO等的透明导电材料、比如铝-钕(AlNd)、钼-钨(MoW)的金属、或反射材料,等等,从而形成透明导电层或金属层。对该透明导电层或金属层构图以形成像素电极(未示出)和第一导电涂层(未示出)。可以对包括透明导电层或金属层的叠层构图,以形成具有该像素电极和第一导电涂层的叠层结构。
图12A和图12B是图示根据本发明另一个实施方案的制造TFT衬底的方法的横截面视图。
参考图12A和图12B,有机或无机绝缘层230和第一凸出元件251形成在第一衬底210上,如图10D所示。即,绝缘层230在像素区域291中包括接触孔235,第一凸出元件251设置在第一衬底210的栅焊盘区域292和数据焊盘区域293。然后,在第一衬底210上设置具有第三透明区域910和第三遮蔽区域920的第三掩模900,并且通过使用第三掩模900对绝缘层230和第一凸出元件251构图,使得在绝缘层230和第一凸出元件251的上表面上形成凹凸图案。即,在第一衬底210上的栅焊盘区域292和数据焊盘区域293中形成多个第三凸出元件251b。如本领域普通技术人员所知的那样,该凹凸图案可以仅设置在除绝缘层230的上表面以外的第一凸出元件251的上表面上。
透明导电层或金属层沉积在绝缘层230和第三凸出元件251b上。透明导电层包括ITO或IZO,金属层包括铝-钕(AlNd)或钼-钨(MoW)。然后,对透明导电层或金属层构图以在像素区域291中形成像素电极(未示出)和在第三凸出元件251b上形成第三导电涂层(未示出)。通过对包括透明导电层和金属层的叠层构图,形成包括该像素电极和第三导电涂层的叠层结构。
尽管本发明公开的是接触孔和第三凸出元件在先形成,之后形成凹凸图案,但是凹凸图案可以在先形成在光致抗蚀剂层上,之后形成接触孔和第三凸出元件,就如本领域普通技术人员所知的那样。
工业实用性
如上所述,在LCD装置或其他比如电致发光显示、PDP等的显示应用中的TFT衬底的栅焊盘区域和数据焊盘区域中形成了弹性导电凸点,并且驱动IC通过介于该导电凸点和驱动IC之间的中间非导电树脂安装在弹性导电凸点之上。
非导电树脂将驱动IC粘附到导电凸点上以确保驱动IC和导电凸点之间的电连接。
非导电树脂由于其在热压工艺之后硬化的收缩力可以提高驱动IC和导电凸点之间的粘附力。
此外,导电凸点由弹性材料构成,并且压焊到驱动IC,于是,第一导电凸点的回复可以补偿栅电极焊盘和驱动IC之间由于非导电树脂的热膨胀或其他因素导致的距离增加。所以,栅电极焊盘和驱动IC之间的电连接可以得到充分地确保。
虽然已经对本发明的示范性实施方案进行了描述,但是应该理解,本发明并不限于这些示范性实施方案,相反本领域的普通技术人员在本发明所要求保护的范围内可以进行各种变化和修改。

Claims (18)

1.一种薄膜晶体管衬底,包括:
多个电极焊盘,设置在布置于衬底上的栅线路和数据线路的端部上;以及
导电凸点,包括以预定厚度设置在所述电极焊盘上的凸出元件和设置在所述凸出元件上以电连接到所述电极焊盘的导电涂层,所述导电凸点通过使用非导电树脂电连接到为所述电极焊盘施加预定信号的驱动集成电路。
2.根据权利要求1所述的薄膜晶体管衬底,其中,所述凸出元件设置在所述电极焊盘上,使得所述电极焊盘的外围部分被暴露。
3.根据权利要求2所述的薄膜晶体管衬底,其中,所述凸出元件包括在它上表面上的凹凸图案。
4.根据权利要求1所述的薄膜晶体管衬底,其中,所述凸出元件包括由预定距离隔开的多个凸起,所述电极焊盘的部分通过所述凸起之间的空间被暴露。
5.一种制造薄膜晶体管衬底的方法,所述方法包括:
形成栅线路、数据线路、以及设置在所述栅线路和数据线路的端部上的多个电极焊盘;以及
形成导电凸点,所述导电凸点包括设置在电极焊盘上以具有预定厚度的凸出元件和设置在所述凸出元件上以电连接到所述电极焊盘的导电涂层,并且所述导电凸点通过使用非导电树脂电连接到为所述电极焊盘施加预定信号的驱动集成电路。
6.根据权利要求5所述的方法,其中所述导电凸点如下形成:
在所述电极焊盘上形成光致抗蚀剂有机层;
对所述光致抗蚀剂有机层构图以在所述电极焊盘上形成凸出元件;
形成覆盖所述凸出元件的导电层;以及
对所述导电层构图以形成所述凸出元件上的导电涂层,将所述导电涂层电连接到所述电极焊盘。
7.一种液晶显示装置,包括具有多个薄膜晶体管和连接到所述薄膜晶体管的导电线路的像素区域,以及包括具有多个电极焊盘的焊盘区域,所述液晶显示装置包括:
液晶显示面板,所述液晶显示面板包括薄膜晶体管衬底、对应于所述薄膜晶体管衬底的滤色器衬底、以及介于所述薄膜晶体管衬底和所述滤色器衬底之间的液晶层,所述薄膜晶体管衬底包括设置在所述电极焊盘上的凸出元件和设置在所述凸出元件上的导电凸点,所述导电凸点具有电连接到所述电极焊盘的导电涂层;
驱动集成电路,电连接到所述导电凸点以向所述电极焊盘施加预定信号;以及
粘附元件,置于所述导电凸点和所述驱动集成电路之间,所述粘附元件将所述驱动集成电路粘附到所述导电凸点以确保所述导电凸点和所述驱动集成电路之间的电连接。
8.根据权利要求7的液晶显示装置,其中,所述凸出元件包括弹性有机材料,使得在所述驱动集成电路被下压时使所述导电凸点被压缩一距离,在所述驱动集成电路被释放时使所述导电凸点对应于所述距离被回复,从而保持所述导电凸点和所述驱动集成电路之间的电连接。
9.根据权利要求8的液晶显示装置,其中,所述凸出元件设置在所述电极焊盘上,使得所述电极焊盘的外围部分被暴露。
10.根据权利要求9的液晶显示装置,其中,所述凸出元件包括在它上表面上的凹凸图案。
11.根据权利要求8的液晶显示装置,其中,所述凸出元件包括由预定距离隔开的多个凸起,所述电极焊盘的部分通过所述凸起之间的空间被暴露。
12.根据权利要求7的液晶显示装置,其中,所述粘附元件包括一非导电树脂,所述非导电树脂在对所述驱动集成电路的热压工艺期间软化并从所述热压工艺完成时逐渐硬化,使得所述驱动集成电路通过所述非导电树脂由于它的硬化所导致的收缩被粘附到所述导电凸点。
13.一种制造液晶显示装置的方法,所述液晶显示装置包括具有多个薄膜晶体管和连接到所述薄膜晶体管的导电线路的像素区域,以及包括具有多个电极焊盘的焊盘区域,所述液晶显示装置制造方法包括:
形成薄膜晶体管衬底,所述薄膜晶体管衬底包括形成在所述电极焊盘上的凸出元件和形成在所述凸出元件上的导电凸点,所述导电凸点具有电连接到所述电极焊盘的导电涂层;
形成与所述薄膜晶体管衬底相对组合的滤色器衬底;
形成在所述薄膜晶体管衬底和所述滤色器衬底之间的液晶层;以及
通过使用粘附元件将驱动集成电路电连接到所述导电凸点,所述驱动集成电路向所述电极焊盘施加预定信号。
14.根据权利要求13的方法,所述薄膜晶体管衬底如下形成:
在所述像素区域和焊盘区域中形成光致抗蚀剂有机层;
对所述光致抗蚀剂有机层构图以形成在所述像素区域中的绝缘层以及在所述焊盘区域中的凸出元件,所述绝缘层保护所述多个薄膜晶体管和所述导电线路,所述凸出元件形成在所述电极焊盘上;
在所述绝缘层和所述凸出元件之上形成导电层;以及
对所述导电层构图以在所述绝缘层上形成像素电极以及在所述凸出元件上形成电连接到所述电极焊盘的导电涂层。
15.根据权利要求14的方法,其中,所述导电层包括铟锡氧化物或铟锌氧化物。
16.根据权利要求14的方法,其中,所述导电层包括金属。
17.根据权利要求14的方法,其中,所述导电层包括具有第一层和第二层的叠层,所述第一层包括铟锡氧化物或铟锌氧化物,所述第二层包括金属。
18.根据权利要求13的方法,其中,所述粘附元件包括一非导电树脂,所述非导电树脂在对所述驱动集成电路的热压工艺期间软化并从所述热压工艺完成时逐渐硬化,使得所述驱动集成电路通过所述非导电树脂由于它的硬化所导致的收缩被粘附到所述导电凸点。
CNA2003801045955A 2002-12-09 2003-12-05 薄膜晶体管衬底及其制造方法、具有其的液晶显示装置以及制造该液晶显示装置的方法 Pending CN1717617A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020020078017A KR20040050245A (ko) 2002-12-09 2002-12-09 박막 트랜지스터 기판, 이의 제조방법, 이를 갖는액정표시장치 및 이의 제조방법
KR1020020078017 2002-12-09

Publications (1)

Publication Number Publication Date
CN1717617A true CN1717617A (zh) 2006-01-04

Family

ID=36165404

Family Applications (1)

Application Number Title Priority Date Filing Date
CNA2003801045955A Pending CN1717617A (zh) 2002-12-09 2003-12-05 薄膜晶体管衬底及其制造方法、具有其的液晶显示装置以及制造该液晶显示装置的方法

Country Status (6)

Country Link
US (1) US20060146214A1 (zh)
JP (1) JP2006509252A (zh)
KR (1) KR20040050245A (zh)
CN (1) CN1717617A (zh)
AU (1) AU2003302832A1 (zh)
WO (1) WO2004053585A1 (zh)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101043026B (zh) * 2006-03-20 2011-04-20 株式会社半导体能源研究所 晶体半导体薄膜,半导体器件及其制造方法
CN102487071A (zh) * 2010-12-02 2012-06-06 三星移动显示器株式会社 有机发光显示装置及其制造方法
CN105809720A (zh) * 2015-01-20 2016-07-27 台湾积体电路制造股份有限公司 用于无掩模直写光刻的系统和方法

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3841087B2 (ja) * 2004-03-17 2006-11-01 セイコーエプソン株式会社 電気光学装置用パネル及びその製造方法、電気光学装置、並びに電子機器
JP2006243724A (ja) * 2005-03-04 2006-09-14 Samsung Electronics Co Ltd 駆動チップ、表示装置及びその製造方法
JP4224717B2 (ja) 2005-07-11 2009-02-18 セイコーエプソン株式会社 半導体装置
KR20070043098A (ko) * 2005-10-20 2007-04-25 삼성전자주식회사 어레이 기판 및 이의 제조방법
KR101499120B1 (ko) * 2009-01-19 2015-03-06 삼성디스플레이 주식회사 표시 장치 및 이의 제조 방법
KR102373440B1 (ko) * 2017-03-17 2022-03-14 삼성디스플레이 주식회사 디스플레이 패널 및 이를 구비하는 디스플레이 장치
KR20210008277A (ko) * 2019-07-12 2021-01-21 삼성디스플레이 주식회사 표시 장치 및 표시 장치의 제조 방법
KR20240034970A (ko) * 2022-09-07 2024-03-15 삼성디스플레이 주식회사 표시 장치

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5089750A (en) * 1986-12-18 1992-02-18 Matsushita Electric Industrial Co., Ltd. Lead connection structure
NL9001982A (nl) * 1990-09-10 1992-04-01 Koninkl Philips Electronics Nv Interconnectiestructuur.
EP0827190A3 (en) * 1994-06-24 1998-09-02 Industrial Technology Research Institute Bump structure and methods for forming this structure
JPH0990397A (ja) * 1995-09-28 1997-04-04 Sharp Corp アクティブマトリクス基板およびそれを用いた表示装置
KR100251512B1 (ko) * 1997-07-12 2000-04-15 구본준 횡전계방식 액정표시장치
US6287899B1 (en) * 1998-12-31 2001-09-11 Samsung Electronics Co., Ltd. Thin film transistor array panels for a liquid crystal display and a method for manufacturing the same
US6380559B1 (en) * 1999-06-03 2002-04-30 Samsung Electronics Co., Ltd. Thin film transistor array substrate for a liquid crystal display
JP2001267371A (ja) * 2000-03-21 2001-09-28 Hitachi Ltd 液晶表示装置
JP2002244146A (ja) * 2001-02-01 2002-08-28 Ind Technol Res Inst 不透明基板を具えたフラットパネルディスプレイの内部連接方法とそれにより形成される装置
KR100685946B1 (ko) * 2001-03-02 2007-02-23 엘지.필립스 엘시디 주식회사 액정 디스플레이 패널 및 그 제조방법

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101043026B (zh) * 2006-03-20 2011-04-20 株式会社半导体能源研究所 晶体半导体薄膜,半导体器件及其制造方法
CN102487071A (zh) * 2010-12-02 2012-06-06 三星移动显示器株式会社 有机发光显示装置及其制造方法
CN105809720A (zh) * 2015-01-20 2016-07-27 台湾积体电路制造股份有限公司 用于无掩模直写光刻的系统和方法
CN105809720B (zh) * 2015-01-20 2019-09-06 台湾积体电路制造股份有限公司 用于无掩模直写光刻的系统和方法

Also Published As

Publication number Publication date
US20060146214A1 (en) 2006-07-06
KR20040050245A (ko) 2004-06-16
AU2003302832A1 (en) 2004-06-30
JP2006509252A (ja) 2006-03-16
WO2004053585A1 (en) 2004-06-24

Similar Documents

Publication Publication Date Title
CN1258114C (zh) 液晶显示器及其制造方法
CN1306333C (zh) 显示基板及具有该基板的液晶显示器
CN100350319C (zh) 液晶显示板及其制造方法
CN1184607C (zh) 液晶显示装置和用于制造所述液晶显示装置的方法
CN1294622C (zh) 具有薄膜晶体管上滤色器结构的阵列基板及其制造方法
CN1495477A (zh) 显示器基板、液晶显示器和制造该液晶显示器的方法
CN1782838A (zh) 液晶显示器件及其制造方法
CN101079429A (zh) 薄膜晶体管阵列基板及其制造方法
CN1875312A (zh) 具有触摸屏功能的液晶显示装置及其构造方法
CN1760738A (zh) 液晶显示装置及其制造方法
CN1921095A (zh) 半导体芯片、显示屏板及其制造方法
CN101059633A (zh) 用于液晶显示器件的阵列基板及其制造方法
CN1713057A (zh) 薄膜晶体管阵列基板及其制造方法
CN1555506A (zh) 用于液晶显示器的薄膜晶体管面板
CN101064318A (zh) 用于显示设备的薄膜晶体管阵列面板及其制造方法
CN1847940A (zh) 形成焊盘电极及液晶显示器件的方法
CN1744322A (zh) 薄膜晶体管阵列板
CN1716062A (zh) 液晶显示器件的阵列基板的制造方法
CN1897270A (zh) 布线结构、制造布线的方法、薄膜晶体管基板及其制造方法
CN1491442A (zh) 半导体器件的接触部分和包括该接触部分的用于显示器的薄膜晶体管阵列板
CN1991549A (zh) 共平面开关模式液晶显示器件的阵列基板及其制造方法
CN1991539A (zh) 液晶显示器件及其制造方法
CN1885549A (zh) 电光显示装置及其制造方法
CN1717617A (zh) 薄膜晶体管衬底及其制造方法、具有其的液晶显示装置以及制造该液晶显示装置的方法
CN1201183C (zh) 电光装置及其制造方法、电子设备

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C02 Deemed withdrawal of patent application after publication (patent law 2001)
WD01 Invention patent application deemed withdrawn after publication