CN1688019A - 内置软硬件系统的芯片及其制作方法 - Google Patents
内置软硬件系统的芯片及其制作方法 Download PDFInfo
- Publication number
- CN1688019A CN1688019A CNA2005100208871A CN200510020887A CN1688019A CN 1688019 A CN1688019 A CN 1688019A CN A2005100208871 A CNA2005100208871 A CN A2005100208871A CN 200510020887 A CN200510020887 A CN 200510020887A CN 1688019 A CN1688019 A CN 1688019A
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- 238000004519 manufacturing process Methods 0.000 claims abstract description 20
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- 238000013461 design Methods 0.000 abstract description 8
- 238000010586 diagram Methods 0.000 abstract description 5
- 238000003860 storage Methods 0.000 abstract description 4
- 238000004806 packaging method and process Methods 0.000 abstract 1
- 238000011161 development Methods 0.000 description 14
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Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15192—Resurf arrangement of the internal vias
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- Semiconductor Memories (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
Claims (10)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CNB2005100208871A CN100369224C (zh) | 2005-05-08 | 2005-05-08 | 内置软硬件系统的芯片及其制作方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CNB2005100208871A CN100369224C (zh) | 2005-05-08 | 2005-05-08 | 内置软硬件系统的芯片及其制作方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1688019A true CN1688019A (zh) | 2005-10-26 |
CN100369224C CN100369224C (zh) | 2008-02-13 |
Family
ID=35306060
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB2005100208871A Ceased CN100369224C (zh) | 2005-05-08 | 2005-05-08 | 内置软硬件系统的芯片及其制作方法 |
Country Status (1)
Country | Link |
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CN (1) | CN100369224C (zh) |
Cited By (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101430648A (zh) * | 2008-12-24 | 2009-05-13 | 北京中星微电子有限公司 | 一种固化、加载镜像的方法及装置 |
CN102567262A (zh) * | 2010-10-28 | 2012-07-11 | 马维尔国际贸易有限公司 | 可扩展嵌入式存储器编程 |
CN103219334A (zh) * | 2013-04-27 | 2013-07-24 | 北京兆易创新科技股份有限公司 | 一种闪存封装芯片 |
CN103219333A (zh) * | 2013-04-09 | 2013-07-24 | 北京兆易创新科技股份有限公司 | 增强型Flash芯片、封装方法和指令执行方法 |
CN103236428A (zh) * | 2013-04-09 | 2013-08-07 | 北京兆易创新科技股份有限公司 | 一种含有RPMC的增强型Flash芯片及其封装方法 |
CN103246553A (zh) * | 2013-04-09 | 2013-08-14 | 北京兆易创新科技股份有限公司 | 一种增强型Flash芯片和一种芯片封装方法 |
WO2014166165A1 (zh) * | 2013-04-09 | 2014-10-16 | 北京兆易创新科技股份有限公司 | 一种增强型flash芯片和一种芯片封装方法 |
CN104735919A (zh) * | 2015-01-26 | 2015-06-24 | 珠海欧比特控制工程股份有限公司 | 一种信号处理模块及其制作方法 |
CN108694364A (zh) * | 2017-04-12 | 2018-10-23 | 清华大学 | 一种指纹采集装置及其制备方法 |
WO2023213218A1 (zh) * | 2022-05-05 | 2023-11-09 | 上海沛塬电子有限公司 | 一种高频高功率密度模块电源、并联组合、制作方法及软硬结合组件 |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH08288453A (ja) * | 1995-04-17 | 1996-11-01 | Matsushita Electron Corp | 半導体装置 |
JP2830793B2 (ja) * | 1995-08-24 | 1998-12-02 | 日本電気株式会社 | マルチチップモジュール |
US5742844A (en) * | 1995-11-29 | 1998-04-21 | Zf Microsystems, Inc. | IBM PC compatible multi-chip module |
GB2308905A (en) * | 1996-01-08 | 1997-07-09 | John Robert Miller | Protected system processor |
US5841686A (en) * | 1996-11-22 | 1998-11-24 | Ma Laboratories, Inc. | Dual-bank memory module with shared capacitors and R-C elements integrated into the module substrate |
JPH1126732A (ja) * | 1997-06-30 | 1999-01-29 | Emiile Denshi Kaihatsushiya:Kk | 集積回路 |
JPH11345939A (ja) * | 1998-05-29 | 1999-12-14 | Sanyo Electric Co Ltd | 半導体集積回路装置及び半導体集積回路装置の開発方法 |
-
2005
- 2005-05-08 CN CNB2005100208871A patent/CN100369224C/zh not_active Ceased
Cited By (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101430648A (zh) * | 2008-12-24 | 2009-05-13 | 北京中星微电子有限公司 | 一种固化、加载镜像的方法及装置 |
CN102567262A (zh) * | 2010-10-28 | 2012-07-11 | 马维尔国际贸易有限公司 | 可扩展嵌入式存储器编程 |
CN102567262B (zh) * | 2010-10-28 | 2016-08-17 | 马维尔国际贸易有限公司 | 可扩展嵌入式存储器编程 |
US9396798B2 (en) | 2013-04-09 | 2016-07-19 | Gigadevice Semiconductor (Beijing) Inc. | Enhanced flash chip and method for packaging chip |
CN103219333B (zh) * | 2013-04-09 | 2015-11-25 | 北京兆易创新科技股份有限公司 | 增强型Flash芯片、封装方法和指令执行方法 |
CN103246553A (zh) * | 2013-04-09 | 2013-08-14 | 北京兆易创新科技股份有限公司 | 一种增强型Flash芯片和一种芯片封装方法 |
WO2014166167A1 (zh) * | 2013-04-09 | 2014-10-16 | 北京兆易创新科技股份有限公司 | 一种增强型Flash芯片和一种芯片封装方法 |
WO2014166165A1 (zh) * | 2013-04-09 | 2014-10-16 | 北京兆易创新科技股份有限公司 | 一种增强型flash芯片和一种芯片封装方法 |
US9728520B2 (en) | 2013-04-09 | 2017-08-08 | Gigadevice Semiconductor (Beijing) Inc. | Enhanced flash chip and method for packaging chip |
CN103236428B (zh) * | 2013-04-09 | 2015-11-25 | 北京兆易创新科技股份有限公司 | 一种含有RPMC的增强型Flash芯片及其封装方法 |
CN103236428A (zh) * | 2013-04-09 | 2013-08-07 | 北京兆易创新科技股份有限公司 | 一种含有RPMC的增强型Flash芯片及其封装方法 |
CN103219333A (zh) * | 2013-04-09 | 2013-07-24 | 北京兆易创新科技股份有限公司 | 增强型Flash芯片、封装方法和指令执行方法 |
CN103219334B (zh) * | 2013-04-27 | 2015-11-25 | 北京兆易创新科技股份有限公司 | 一种闪存封装芯片 |
CN103219334A (zh) * | 2013-04-27 | 2013-07-24 | 北京兆易创新科技股份有限公司 | 一种闪存封装芯片 |
CN104735919A (zh) * | 2015-01-26 | 2015-06-24 | 珠海欧比特控制工程股份有限公司 | 一种信号处理模块及其制作方法 |
CN104735919B (zh) * | 2015-01-26 | 2019-01-25 | 珠海欧比特控制工程股份有限公司 | 一种信号处理模块及其制作方法 |
CN108694364A (zh) * | 2017-04-12 | 2018-10-23 | 清华大学 | 一种指纹采集装置及其制备方法 |
WO2023213218A1 (zh) * | 2022-05-05 | 2023-11-09 | 上海沛塬电子有限公司 | 一种高频高功率密度模块电源、并联组合、制作方法及软硬结合组件 |
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Legal Events
Date | Code | Title | Description |
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ASS | Succession or assignment of patent right |
Owner name: DONG TAO ZHENG ZHOU KAIDA ELECTRONICS CO., LTD. Free format text: FORMER OWNER: DONG TAO Effective date: 20050826 |
|
C06 | Publication | ||
C41 | Transfer of patent application or patent right or utility model | ||
PB01 | Publication | ||
TA01 | Transfer of patent application right |
Effective date of registration: 20050826 Address after: Guangdong city of Shenzhen province Luohu District longan road Hongqun building 13-402 Applicant after: Xue Ping Co-applicant after: Dong Tao Co-applicant after: Zhengzhou Kaida Electronics Co., Ltd. Address before: Guangdong city of Shenzhen province Luohu District longan road Hongqun building 13-402 Applicant before: Xue Ping Co-applicant before: Dong Tao |
|
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C41 | Transfer of patent application or patent right or utility model | ||
TA01 | Transfer of patent application right |
Effective date of registration: 20070601 Address after: 518001 Guangdong city of Shenzhen province Luohu District longan road Hongqun building 13-402 Applicant after: Xue Ping Co-applicant after: Dong Tao Co-applicant after: Zhou Xuening Address before: 518001 Guangdong city of Shenzhen province Luohu District longan road Hongqun building 13-402 Applicant before: Xue Ping Co-applicant before: Dong Tao Co-applicant before: Zhengzhou Kaida Electronics Co., Ltd. |
|
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
C35 | Partial or whole invalidation of patent or utility model | ||
IW01 | Full invalidation of patent right |
Decision date of declaring invalidation: 20101222 Decision number of declaring invalidation: 15825 Granted publication date: 20080213 Decision date of declaring invalidation: 20101224 Decision number of declaring invalidation: 15853 Granted publication date: 20080213 |