TWI828121B - 多晶片封裝 - Google Patents
多晶片封裝 Download PDFInfo
- Publication number
- TWI828121B TWI828121B TW111115241A TW111115241A TWI828121B TW I828121 B TWI828121 B TW I828121B TW 111115241 A TW111115241 A TW 111115241A TW 111115241 A TW111115241 A TW 111115241A TW I828121 B TWI828121 B TW I828121B
- Authority
- TW
- Taiwan
- Prior art keywords
- die
- bridge
- hole
- interconnect
- molding material
- Prior art date
Links
- 238000004806 packaging method and process Methods 0.000 title description 3
- 239000000463 material Substances 0.000 claims abstract description 65
- 239000012778 molding material Substances 0.000 claims description 70
- 238000004519 manufacturing process Methods 0.000 claims description 46
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- 239000013078 crystal Substances 0.000 claims 2
- 238000004891 communication Methods 0.000 abstract description 45
- 229910000679 solder Inorganic materials 0.000 abstract description 22
- 239000000758 substrate Substances 0.000 description 77
- 238000000034 method Methods 0.000 description 45
- 239000010410 layer Substances 0.000 description 38
- 230000008878 coupling Effects 0.000 description 28
- 238000010168 coupling process Methods 0.000 description 28
- 238000005859 coupling reaction Methods 0.000 description 28
- 239000004020 conductor Substances 0.000 description 24
- 239000011295 pitch Substances 0.000 description 9
- 239000000853 adhesive Substances 0.000 description 8
- 230000001070 adhesive effect Effects 0.000 description 8
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 7
- 229910052802 copper Inorganic materials 0.000 description 7
- 239000010949 copper Substances 0.000 description 7
- 230000009471 action Effects 0.000 description 6
- 230000006870 function Effects 0.000 description 6
- 230000008569 process Effects 0.000 description 6
- 238000000227 grinding Methods 0.000 description 5
- 239000012780 transparent material Substances 0.000 description 5
- 239000004593 Epoxy Substances 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- 230000007246 mechanism Effects 0.000 description 4
- 238000000465 moulding Methods 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 239000002648 laminated material Substances 0.000 description 3
- 230000001066 destructive effect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 238000011156 evaluation Methods 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 239000002904 solvent Substances 0.000 description 2
- 239000012790 adhesive layer Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000001413 cellular effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000004590 computer program Methods 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000000608 laser ablation Methods 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 239000002923 metal particle Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000001902 propagating effect Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000031070 response to heat Effects 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 230000011218 segmentation Effects 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- 230000000007 visual effect Effects 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3135—Double encapsulation or coating and encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3185—Partial encapsulation or coating the coating covering also the sidewalls of the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5381—Crossover interconnections, e.g. bridge stepovers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5385—Assembly of a plurality of insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/0557—Disposition the external layer being disposed on a via connection of the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
- H01L2224/06181—On opposite sides of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
- H01L2224/081—Disposition
- H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/08135—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/08145—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
- H01L2224/081—Disposition
- H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/08151—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/08221—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/08225—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/11011—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
- H01L2224/11013—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the bump connector, e.g. solder flow barrier
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/13198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/13199—Material of the matrix
- H01L2224/1329—Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/13198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/13298—Fillers
- H01L2224/13299—Base material
- H01L2224/133—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16238—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
- H01L2224/1701—Structure
- H01L2224/1703—Bump connectors having different sizes, e.g. different diameters, heights or widths
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
- H01L2224/1705—Shape
- H01L2224/17051—Bump connectors having different shapes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
- H01L2224/171—Disposition
- H01L2224/1718—Disposition being disposed on at least two different sides of the body, e.g. dual array
- H01L2224/17181—On opposite sides of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73209—Bump and HDI connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/81001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus
- H01L2224/81005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81192—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/81986—Specific sequence of steps, e.g. repetition of manufacturing steps, time sequence
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
- H01L2224/82009—Pre-treatment of the connector or the bonding area
- H01L2224/8203—Reshaping, e.g. forming vias
- H01L2224/82035—Reshaping, e.g. forming vias by heating means
- H01L2224/82039—Reshaping, e.g. forming vias by heating means using a laser
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/9202—Forming additional connectors after the connecting process
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92222—Sequential connecting processes the first connecting process involving a bump connector
- H01L2224/92224—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a build-up interconnect
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/95001—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
- H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06582—Housing for the assembly, e.g. chip scale package [CSP]
- H01L2225/06586—Housing with external bump or bump-like connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L24/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15192—Resurf arrangement of the internal vias
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/162—Disposition
- H01L2924/16251—Connecting to an item not being a semiconductor or solid-state body, e.g. cap-to-substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Combinations Of Printed Boards (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Geometry (AREA)
- Wire Bonding (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Packaging Frangible Articles (AREA)
Abstract
電子裝置可包括第一晶粒,其可包括第一組晶粒接點。電子裝置可包括第二晶粒,其可包括第二組晶粒接點。電子裝置可包括橋互連,其可包括第一組橋接點且可包括第二組橋接點。第一組橋接點可直接地耦合至第一組晶粒接點(例如,利用互連材料,諸如焊料)。第二組橋接點可直接地耦合至第二組晶粒接點(例如,利用焊料)。橋互連可協助促進介於第一晶粒與第二晶粒之間的電通訊。
Description
本發明係關於多晶片封裝。
電子裝置可包括複數積體電路。積體電路可透過基材中之一或更多選路軌線而處於電通訊。晶粒可被包括於基材中以協助促進介於複數積體電路之間的電通訊。
本案發明人已辨識(除了別的以外):一待解決問題可包括增進介於複數晶粒之間的電通訊,諸如藉由減少介於複數晶粒之間的信號損失或干擾之量。本請求標的可協助提供對於此問題之解決方式,諸如藉由提供電子裝置。
電子裝置可包括第一晶粒,其可包括第一組晶粒接點。電子裝置可包括第二晶粒,其可包括第二組晶粒接點。電子裝置可包括橋互連,其可包括第一組橋接點且可包括第二組橋接點。第一組橋接點可直接地耦合至第一組晶粒接點(例如,利用互連材料,諸如焊料)。第二組橋接點可直接地耦合至第二組晶粒接點(例如,利用焊料)。橋互連可協助促進介於第一晶粒與第二晶粒之間的電通訊。
橋互連可協助減少應包括空腔於基材中以容納一用以電互連第一晶粒與第二晶粒之晶粒的需求。橋互連可協助減少介於第一晶粒與第二晶粒之間的信號損失及干擾,諸如藉由減少信號在第一晶粒與第二晶粒之間所行進的長度。橋互連可藉此協助減少與製造電子裝置關聯的製造成本,諸如藉由增進製程良率或減少與製造電子裝置關聯的製程之複雜度。
此概要係為了提供本專利申請案之請求標的之概要。其並非為了提供本發明之排他的或窮舉的解釋。詳細描述被包括以提供有關本專利申請案之進一步資訊。
圖1繪示電子裝置100之一範例的概圖。電子裝置可包括第一晶粒110,包括第二晶粒120,且可包括第三晶粒130。第一晶粒110、第二晶粒120、或第三晶粒130可包括半導體材料。第一晶粒110、第二晶粒120、及第三晶粒130可包括處理器晶粒、記憶體晶粒、通訊晶粒(例如,WiFi、藍牙、或蜂巢式裝置),等等。
電子裝置100可包括橋互連140。橋互連140可協助促進電子裝置100內之電通訊,諸如介於第一晶粒110與第二晶粒120之間的電通訊。橋互連140可與第一晶粒110、第二晶粒120、及/或第三晶粒130耦合,諸如利用互連材料(例如,焊料、導電環氧樹脂,等等)或利用晶粒與橋互連140之直接接合(例如,包括密切接觸之接合)。
電子裝置100可包括模製材料150。模製材料150可與第一晶粒110、第二晶粒120、第三晶粒130之一部分耦合(例如,與該部分形成直接介面、或囊封該部分),或者可與橋互連140之一部分耦合。模製材料150可協助提供對於電子裝置100之機械支撐。模製材料150可包括已填充聚合物材料。模製材料150可被沈積、形成、注射、旋塗,等等,並藉此與電子裝置100之組件(諸如第一晶粒110或橋互連140)耦合。
電子裝置100可包括基材160。基材160可包括電介質材料並可包括導電材料。基材160可包括一或更多選路層,其可被調適以傳輸電信號。第一晶粒110、第二晶粒120、及/或第三晶粒130可被耦合至基材160,諸如利用互連材料或利用晶粒與基材160之直接接合。基材160可被耦合至(及電通訊與)額外結構(例如,主機板、另一基材、系統單晶片,等等)。電子裝置100可包括焊料凸塊180,其可促進基材160與額外結構之耦合。焊料凸塊180可與基材160之選路層電通訊。
下填材料170可被置於基材160與橋互連140之間。下填材料170可直接相鄰於互連材料、或形成與互連材料之直接介面。氧化物層可被包括於下填170(或模製材料150)與電子裝置100的其他組件(諸如互連材料)之間。
圖2繪示於製造操作期間之電子裝置100的概圖,依據本請求標的之範例。如文中所述,電子裝置100可包括第一晶粒110、第二晶粒120,且可包括第三晶粒130。第一晶粒110、第二晶粒120、及第三晶粒130可被置於載體200上。第一晶粒110、第二晶粒120、及第三晶粒130之主動側可被耦合至載體200。第一晶粒110、第二晶粒120、及第三晶粒130之非主動側可被耦合至載體200。
載體200可協助提供用以履行製造操作(諸如製造電子裝置100)之基礎。載體200可提供平坦表面。載體200可包括透明材料,諸如玻璃、聚合物、藍寶石,等等。載體200可包括複數通孔。複數通孔可協助第一晶粒110、第二晶粒120、及第三晶粒130與載體200耦合。於一範例中,真空力被產生在載體200之第一側上且施加至位於載體200之第二側上的第一晶粒110、第二晶粒120、及第三晶粒130。
第一晶粒110、第二晶粒120、及第三晶粒130可被耦合至(例如,固定至、或固持在一起)載體200,諸如利用黏著劑210。黏著劑210可包括透明材料。黏著劑210可具有10至20微米之範圍內的厚度。黏著劑210可被調適以回應於熱或光(例如,UV或可見光)而鬆開(例如,介於第一晶粒110與載體200之間的接合力可減小)。黏著劑210可被置於第一晶粒110、第二晶粒120、及第三晶粒130的主動側與載體210之間。
第一晶粒110可包括接點220。接點220可與晶粒(例如,第一晶粒110)之電路電通訊,且可容許晶粒與外部裝置或結構之互連,包括(但不限定於)橋互連140。接點220可包括導電墊、導電凸塊、導電管腳、導電柱,等等。
第一晶粒110可包括第一組晶粒接點230、第二組晶粒接點240,且可包括第三組晶粒接點250。第二晶粒120可包括第四組晶粒接點260,且可包括第五組晶粒接點270。第三晶粒110可包括第六組晶粒接點280且可包括第七組晶粒接點290。晶粒接點(第一組晶粒接點230及第五組接點270)可延伸自晶粒(例如,第一晶粒110)且可具有相同高度、或可具有不同高度。
圖3繪示橋互連140之概圖。如文中更詳細地討論,橋互連140可協助促進介於第一晶粒110、第二晶粒120、及/或第三晶粒130之間的電通訊。橋互連140可包括半導體晶粒。橋互連140可處理橋互連140內所傳輸的電信號。橋互連140可包括有機封裝。
橋互連140可包括第一組橋接點310且可包括第二組橋接點320。第一組橋接點310可包括凸塊300。凸塊300可與橋互連140之電路電通訊且凸塊300可延伸自橋互連140。
橋互連140可包括橋通孔350。橋通孔350可包括穿越矽通孔。橋通孔350可協助傳輸電信號通過橋互連140。橋通孔350可電互連橋互連140之第一側330與橋互連140之第二側340。橋互連140可包括橋互連140之第一側330或第二側340上的接點(例如,第一組橋接點310)。例如,橋互連140可包括橋互連140之第一側330上的第一墊。橋互連140可包括橋互連140之第二側340上的第二墊。凸塊300可被耦合至第一墊或第二墊。橋通孔330可與凸塊300電通訊。
圖4繪示於製造操作期間之電子裝置100的概圖,依據本請求標的之範例。橋互連140可協助促進電子裝置100內之電通訊,諸如介於第一晶粒110與第三晶粒130之間的電通訊。橋互連140可協助建立介於第一晶粒110、第二晶粒120、第三晶粒130、及/或電子裝置100的額外晶粒之間的電通訊路徑。橋互連140可被調整大小並調整形狀以重疊第一晶粒110及第二晶粒120(或第一晶粒110及第三晶粒130)之一部分。
橋互連140可被直接地耦合至第一晶粒110、第二晶粒120、第三晶粒130、或額外晶粒。直接地耦合橋互連140可包括直接地接合橋互連140與第一晶粒110、第二晶粒120、及/或第三晶粒130。於一範例中,橋互連140包括半導體晶粒,且橋互連140之晶粒被直接地耦合至第一晶粒110。橋互連140可利用互連材料400(例如,焊料、導電環氧樹脂,等等)而被直接地耦合至第一晶粒110。
因為橋互連140被直接地與電子裝置100之晶粒(例如,第一晶粒110)耦合,所以橋互連140可協助減少RC損失或可協助減少互連傳播延遲。於一範例中,橋互連140可協助減少電信號在第一晶粒110與第二晶粒120之間所必須行進的長度。此外,橋互連140可容許電信號被傳輸以比(例如)藉由傳輸電信號通過基材中之選路軌線更大的速率。
因此,藉由直接地耦合橋互連140與第一晶粒110及第二晶粒120,其可被傳輸於第一晶粒110與第二晶粒110之間的電信號可經歷RC損失或互連傳播延遲之減少的量。橋互連140可協助增進電子裝置100之性能並可協助簡化用以製造電子裝置100之製程。
再次參考圖4,橋互連140之橋接點(例如,圖3之第一組橋接點310)可被直接地耦合至第一晶粒110、第二晶粒110、第三晶粒130、及/或額外晶粒之晶粒接點(例如,圖2之第一組晶粒接點230及第四組晶粒接點260)。於一範例中,以及如圖4中所示,第一橋互連140A之橋接點可被直接地耦合至第一晶粒110及第二晶粒120之橋接點(例如,利用互連材料,諸如焊料)。
第二橋互連140B可被直接地耦合至第一晶粒110及第三晶粒130。第一橋互連140A可協助促進第一晶粒110與第二晶粒120之電通訊。第二橋互連140B可協助促進介於第一晶粒110與第三晶粒130之間的電通訊。第一橋互連140A及第二橋互連140B可協助促進介於第二晶粒120與第三晶粒130之間的電通訊。
於另一範例中,第一橋互連140A之橋接點可被直接地耦合至第一晶粒110、第二晶粒120、及第三晶粒130之晶粒接點。第一橋互連140A可協助促進介於第一晶粒110、第二晶粒120、及第三晶粒130之間的電通訊。於又另一範例中,第一晶粒110、第二晶粒120、第三晶粒130、及第四晶粒被置於鄰近彼此(例如,配置於柵格中)。橋互連140之橋接點可被置於鄰近第一晶粒110、第二晶粒120、第三晶粒130、及第四晶粒之橋接點(例如,在晶粒的四個角落上)。橋互連140A可被直接地耦合至第一晶粒110、第二晶粒120、第三晶粒130、及第四晶粒;且可協助促進介於第一晶粒110、第二晶粒120、第三晶粒130、及第四晶粒的一或更多者之間的電通訊。第一晶粒110、第二晶粒120、第三晶粒130、及/或額外晶粒;以及橋互連(例如,第一橋互連140A及/或第二橋互連140B)之額外配置或組態是可能的且被考量為落入本請求標的之範圍內。
模製材料150可被耦合至(例如,沈積在其上、形成在其上,等等)電子裝置100。模製材料150可被耦合至第一晶粒110、第二晶粒120、第三晶粒130、橋互連140、及電子裝置100之互連。模製材料150可提供機械強度給電子裝置100並可增進電子裝置100之互連的彈性。
圖5繪示於製造操作期間之電子裝置100的概圖,依據本請求標的之範例。第一開口500或第二開口510可被形成在(例如,界定在)模製材料100中,諸如利用雷射消熔程序。第一開口500可與第一晶粒110之接點220互通。第二開口510可與第五組晶粒接點270互通。
基準標記可被用以對準第一開口500與(例如)接點220。如文中所述,載體200可包括透明材料。載體200可包括一或更多基準標記(點、標記、線、幾何形狀、非晶形狀,等等),其被使用為參考點以判定電子裝置100之組件相對於載體200的位置。例如,載體200之表面可包括基準線,其可被用以確定第一晶粒110相對於載體200之位置。載體200可被調整大小及調整形狀以包括複數耦合至載體200之表面的晶粒。第一晶粒110、第二晶粒120、及第三晶粒130可被耦合至載體200而成為第一組晶粒。載體200可包括基準標記,其係描繪鄰近第一晶粒110、第二晶粒120、及第三晶粒130之區域。第二組晶粒可被耦合至載體200。例如,第二組晶粒可被耦合至載體200(在與第一組晶粒相鄰的單元胞中),而載體200中所包括的基準標記可被用以識別第一組晶粒的位置或第二組晶粒的位置,相對於載體200。
類似地,第一晶粒110、第二晶粒120、或第三晶粒130可包括一或更多基準標記。於一範例中,第一晶粒110可包括第一晶粒110之主動側上的基準標記。載體200及黏著劑210可為透明的。第一晶粒110之主動側上的基準標記可通過載體200及黏著劑210而被觀察到。第一晶粒110之主動側上的基準標記可被使用為用於電子裝置100之其他製程中的參考點,包括(但不限定於)消熔模製材料150以形成第一開口500或第二開口510。
於另一範例中,載體200之一或更多基準標記可被置於載體200之第一表面上,而一或更多基準標記可通過載體200之第二側而被觀察到。文中所述之一或更多基準標記可被使用為參考點,用以判定電子裝置100之組件的位置,包括(但不限定於)第三晶粒110、接點220、或第五組晶粒接點270。
再次參考圖5,導電材料(例如,銅、鋁,等等)可被耦合至電子裝置100,包括(但不限定於)模製材料150或接點(例如,接點220)。於一範例中,導電材料可被沈積至電子裝置100上,諸如利用電鍍操作(例如,電解電鍍等等)。導電材料可填充第一開口500及第二開口510。導電材料與電子裝置100之耦合可形成一覆蓋模製材料150的導電材料之層。
圖6繪示於製造操作期間之電子裝置100的概圖,依據本請求標的之範例。如文中所述,導電材料可被耦合至電子裝置100。導電材料可填充第一開口500並形成一覆蓋模製材料150的導電材料之層。如文中所更詳細地描述,填充開口500(或開口510)的導電材料可提供晶粒通孔600。
導電材料之層(例如,覆蓋模製材料150)可被移除自電子裝置100,諸如利用研磨操作。模製材料150及導電材料可被同時地移除,且(如圖6中所示)晶粒通孔600之第一表面610可與模製材料150之第二表面620共面。
如文中所述,導電材料可與電子裝置100之接點(例如,圖5之接點220)耦合。晶粒通孔600可被耦合至接點。晶粒通孔600可協助促進電子裝置100之電通訊。於一範例中,晶粒通孔600提供通過第一晶粒110之模製材料150的電通訊路徑。電子裝置100可包括複數晶粒通孔,包括晶粒通孔600。
再次參考圖6,模製材料150之一部分可被移除自電子裝置100,諸如利用研磨操作。橋互連140之一部分可被移除自電子裝置100。模製材料150之第二表面620可與橋互連140之第三表面630共面,並可協助減少電子裝置100之高度。橋互連140之第三表面630可與晶粒通孔600之第一表面610(晶粒通孔600之表面)共面,並可協助減少電子裝置100之高度。
第一晶粒110、第二晶粒120、及第三晶粒130可從模製材料150被單片化為單元640。如文中所述,一或更多組晶粒(例如參考圖5所述之第一組晶粒)可被耦合至載體200(圖5中所示)。為了從載體200移除一或更多組晶粒,鄰近一或更多組晶粒之模製材料150可被移除(例如,切除或消熔,例如利用雷射)。例如,鄰近由第一晶粒110、第二晶粒120、及第三晶粒130所佔據的區域之周邊的模製材料150可被移除;而第一晶粒110、第二晶粒120、及第三晶粒130可從載體(例如,圖5之載體200)被分離為單元260。如文中所更詳細地描述,單元640可被使用於電子裝置100之額外製造操作中。
圖7繪示於製造操作期間之電子裝置100的概圖,依據本請求標的之範例。電子裝置100可包括基材150。如文中所述,基材160可包括一或更多選路層,其可被調適以傳輸電信號。基材160可協助促進介於第一晶粒110、第二晶粒120、及/或第三晶粒130之電通訊。
於一範例中,第一晶粒110、第二晶粒120、及第三晶粒130可被耦合至基材150。例如,單元640可被耦合至基材160。基材160可包括基材接點(例如,墊、凸塊、柱、管腳、插口,等等),其可與基材160之選路層電通訊。其可被包括於電子裝置100中之晶粒通孔600可被耦合至基材接點,例如,利用焊料凸塊710。電信號可被傳輸自第一晶粒110、第二晶粒120、及/或第三晶粒130;通過晶粒通孔600及焊料凸塊710;並可傳播通過基材160(及,例如,傳播通過圖1之焊料凸塊180)。
圖8繪示於圖7之圓圈8-8上的電子裝置100之詳細概圖,依據本請求標的之範例。如文中所述,第一晶粒110、第二晶粒120、或第三晶粒130可被耦合至基材160。於某些範例中,橋互連140可被耦合至基材160;且橋互連140可與基材160電通訊。橋互連140可被置於電子裝置的晶粒(例如,第一晶粒110)與基材160之間。
橋互連140可被耦合至基材140。例如,橋互連140可包括橋互連140之第一側330(顯示於圖3中)上的橋接點(例如,圖3中所示之第一組橋接點310)。橋互連140可包括橋互連140之第二側上的橋接點。例如,橋互連140可包括橋互連140之第二側上的第三組橋接點810。第三組橋接點810可被耦合至基材160之第一組基材接點820。橋接點(例如,第三組橋接點810)與基材接點(例如,第一組基材接點820)之耦合可協助促進橋互連140與基材160之電通訊。
橋互連140可包括橋通孔800(或圖3中所示之橋通孔350)。橋通孔800可協助促進介於電子裝置100的晶粒(例如,第一晶粒110)與基材160之間的電通訊。橋通孔800可為穿越矽通孔。橋通孔800可電互連橋互連之第一側(例如,圖3中所示之第一側330)與橋互連之第二側(例如,圖3中所示之第二側340)。橋互連140與基材之耦合可容許電信號被傳輸自電子裝置之晶粒(例如,第二晶粒120)、通過橋通孔800、並傳輸至基材160(例如,藉由傳播信號通過第一組基材接點820)。
耦合橋互連140與基材160可協助增加電子裝置中之電互連的密度。耦合橋互連140與基材160可提供介於第一晶粒110與基材160之間的額外電通訊路徑。例如,電信號可被傳輸於第一晶粒110與基材160之間,在橋互連140的足跡內。增加電子裝置100中之電互連的密度可協助增加電子裝置之性能;或可容許電子裝置100之尺寸被減小。
此外,耦合單元640(於圖6及7中顯示)至基材160可協助減少製造電子裝置100之難度並可協助減少電子裝置100之製造操作中的損失。
於一範例中,橋互連140可包括其具有第一節距之橋互連(例如,圖3中所示之第一組橋互連310)。第一晶粒110可包括其具有第一節距之晶粒接點(例如,圖2中所示之第二組晶粒接點240);且第一晶粒110可包括其具有第二節距之晶粒接點(例如,圖2中所示之第三組晶粒接點250)。第一節距可不同於第二節距。其具有第一節距之電子裝置100的結構可被電互連於第一操作中。其具有第二節距之電子裝置100的結構可被電互連於第二操作中。將具有第一節距及第二節距之結構的互連分離為第一操作及第二操作可簡化電子裝置100之製造操作並可協助減少與電子裝置100之製造操作關聯的浪費(例如,良率損失)。
圖9繪示於製造操作期間之電子裝置100的概圖,依據本請求標的之範例。一或更多晶粒,包括(但不限定於)第一晶粒110、第二晶粒120、及第三晶粒130,可被耦合至載體200(例如,利用黏著劑層210)。模製材料150之第一層150A可被耦合至第一晶粒110、第二晶粒120、及第三晶粒130。電子裝置100可包括晶粒接點900(例如,包括於第三晶粒130中),且晶粒接點900可包括晶粒接點表面910。晶粒接點表面910可與模製材料150之第一層150A的模製表面920共面。
圖10繪示於製造操作期間之電子裝置100的概圖,依據本請求標的之範例。層1000可被耦合至電子裝置100。例如,層1000可被耦合至晶粒接點表面910及模製表面920。接縫(例如,金屬微粒結構中之差異)可在導電材料及晶粒接點表面910之介面上為可檢測的(例如,透過非破壞性評估)。層1000可包括一耦合至電子裝置100之導電材料種晶層(例如,銅)。層1000可包括疊層材料。疊層材料可包括(但不限定於)乾膜抗蝕劑。疊層材料可被用於製造操作(例如,光微影等等)且可為光敏的。當暴露至光(例如,UV光)時,層1000可硬化(或軟化)。
圖11繪示於製造操作期間之電子裝置的概圖,依據本請求標的之範例。如文中所述,層1000可為光敏的。開口1100可被形成於層1000中。開口1100可與晶粒接點表面910互通。
於一範例中,遮罩可被塗敷在層1000之上,且遮罩可防止層1000之部分暴露至光。例如,遮罩可阻擋層1000吸收晶粒接點表面910上方之區域中的光。其吸收光之層1000的未遮蔽部分可能硬化。層1000之已遮蔽部分可被移除(例如,利用溶劑),且層1000之未遮蔽(或已硬化)部分保留。開口1100可被界定於層1000中。例如,開口1100可被形成於從電子裝置100移除層1000的未遮蔽部分期間。
導電材料可被耦合至電子裝置100,且導電材料可填充開口1100。其填充開口1100之導電材料可產生導電柱(例如,圖12中所示之導電柱1200),且導電柱可延伸自晶粒(例如,第一晶粒110)之表面。導電材料可被耦合至晶粒接點表面910。層1000可被移除(例如,分解)自電子裝置100,且導電材料可實質上未被移除操作所影響。導電柱可包括導電材料,其在層1000之移除後被耦合至晶粒接點表面910。
於一範例中,銅被電鍍入開口1100中且與晶粒接點表面910耦合。銅可與層1000之頂部表面共面。層1000可被移除(例如,利用溶劑)且其填充開口1100之銅將保持耦合至晶粒接點表面910。
圖12繪示於製造操作期間之電子裝置100的概圖,依據本請求標的之範例。電子裝置100可包括導電柱1200。電子裝置可包括複數導電柱,其包括導電柱1200。導電柱1200可包括導電材料(例如,銅),其可被耦合至晶粒(例如,第二晶粒120)之晶粒接點表面(例如,圖11之晶粒接點表面910)。導電柱1200可協助促進晶粒與外部結構之電通訊。例如,導電柱1200可被耦合至基材(例如,圖1中所示之基材160),且導電柱1200可協助促進晶粒(例如,第一晶粒110)與基材之電通訊。
如文中所討論,電子裝置100可包括橋互連140。橋互連140可被耦合至晶粒接點(例如,第一電子裝置100,例如,圖2中所示之第一組晶粒接點230及第四組晶粒接點260),且橋互連可促進電子裝置100之電通訊,包括(但不限定於)介於第一晶粒110與第二晶粒120之間的電通訊。於某些範例中,橋互連140可被耦合至電子裝置100,在層1000(顯示於圖10-11中)已從電子裝置100移除之後。橋互連140可與導電柱1200之一部分共面。導電柱1200可具有第一長度且可延伸自晶粒(例如,第一晶粒110)。導電柱1200可延伸超過橋互連140,其被耦合至電子裝置100。
圖13繪示於製造操作期間之電子裝置100的概圖,依據本請求標的之範例。如文中所討論,電子裝置100可包括模製材料150。模製材料150可協助提供對於電子裝置100之機械強度。模製材料150可被耦合至第一晶粒110、第二晶粒120、第三晶粒130、橋互連140,且可被耦合至導電柱1200。
如文中所討論,電子裝置100可包括模製材料150之第一層150A。電子裝置100可包括模製材料150之第二層150B。第一層150A可在第一操作中被耦合至電子裝置100,而第二層150B可在第二操作中被耦合至電子裝置100。接縫(例如,分子結構中之中斷)可在第一層150A及第二層150B之介面上為可檢測的(例如,透過電子裝置100之分段、或非破壞性評估)。
於一範例中,電子裝置包括複數導電柱,而模製材料150可被置於複數導電柱之間。模製材料150可被置於導電柱1200與橋互連140之間。模製材料可被置於橋互連140與晶粒(例如,第一晶粒110、第二晶粒120、或第三晶粒130)之間。模製材料150可被置於晶粒接點(例如,圖2中所示之第一組晶粒接點230)與橋接點(例如,第一組橋接點310)之間。
模製材料之一部分可被移除(例如,於研磨操作中)且導電柱1200之一部分可被移除。電子裝置100可被移除自載體200而成為一單元(例如,圖6-7之單元640)且可被使用於其他製造操作中。模製材料150之部分可被移除自電子裝置100之周邊。
圖14繪示於製造操作期間之電子裝置100的概圖,依據本請求標的之範例。如文中所述,電子裝置100可包括第一晶粒110、第二晶粒120、及第三晶粒130,其可包括晶粒接點220。模製材料150可被耦合至第一晶粒110、第二晶粒120、及第三晶粒130。晶粒接點220之晶粒接點表面910可與模製材料150之模製表面920共面。橋互連140可被耦合至電子裝置100(例如,耦合至第一晶粒110及第二晶粒120)。
電子裝置100可被分離自載體(例如,圖9之載體200)而成為單元640。單元640可包括一或更多晶粒(例如,第二晶粒120及第三晶粒130)。模製材料150之過量部分1400可被移除(例如,切割、消熔,等等)自單元640。模製表面920可與晶粒(例如,第三晶粒130)之第一表面1410(例如,主動側)共面。模製表面920可與晶粒之第二表面1420共面。晶粒之第一側1410可垂直於晶粒之第二側。
圖15繪示於製造操作期間之電子裝置100的概圖,依據本請求標的之範例。基材160可包括導電柱1510,且導電柱1510可延伸自基材160之表面(例如,延伸第一高度)。單元640可被耦合至基材160。例如,焊球1520可被置於晶粒接點220與導電柱1510之間。橋互連140可與導電柱1510之一部分共面。橋互連140可被置於基材160與晶粒(例如,第一晶粒110)之間。於一範例中,電子裝置100包括第一橋互連(例如,橋互連140)及第二橋互連;且第一橋互連可與第二橋互連共面。
如文中所述,電子裝置100可包括下填材料170。下填材料170可填充介於單元640與基材160之間的空間。於某些範例中,下填材料170具有比模製材料150更低的黏度。下填材料170可被調適以流入其模製材料150所無法流入的空間(例如,在單元640與基材160之間)。下填材料170可被耦合至單元640,且可被耦合至基材160。下填材料170可被置於模製材料150與橋互連140之間。下填材料170可被置於橋互連140的橋接點(例如,圖3的第一組橋接點310)之間。下填材料170可被置於橋互連140與導電柱1510之間。於一範例中,橋互連140可被置於鄰近導電柱1510,且下填材料170可填充介於橋互連140與導電柱1510之間的空間。下填材料170可被耦合至第一晶粒110、第二晶粒120、或第三晶粒130。
圖16繪示於製造操作期間之電子裝置100的概圖,依據本請求標的之範例。電子裝置100可包括熱槽,包括(但不限定於)集成散熱件1600。集成散熱件1600可被置於鄰近單元640。介面材料1610(例如,熱介面材料等等)可被置於單元640與集成散熱件1600之間,且可增進從晶粒(例如,第一晶粒110)至集成散熱件1600之熱轉移。介面材料1610可被置於晶粒(例如,第三晶粒110)的第一側1410(顯示於圖15中)與集成散熱件1600之間。
圖17繪示系統階圖,其係描繪一種包括如本揭露中所描述之電子裝置100的電子裝置(例如,系統)之範例。圖17被包括以顯示針對電子裝置100之較高階裝置應用的範例。於一實施例中,系統1700包括(但不限定於)桌上型電腦、膝上型電腦、小筆電、平板、筆記型電腦、個人數位助理(PDA)、伺服器、工作站、行動電話、行動計算裝置、智慧型手機、網際網路器具或任何其他類型的計算裝置。於某些實施例中,系統1700為系統單晶片(SOC)系統。
於一實施例中,處理器1710具有一或更多處理器核心1712及1712N,其中1712N代表處理器1710內部的第N個處理器核心,其中N為正整數。於一實施例中,系統1700包括多數處理器(包括1710及1705),其中處理器1705具有類似於或相同於處理器1710之邏輯的邏輯。於某些實施例中,處理核心1712包括(但不限定於)預提取邏輯(用以提取指令)、解碼邏輯(用以解碼指令)、執行邏輯(用以執行指令),等等。於某些實施例中,處理器1710具有用以快取系統1700之指令及/或資料的快取記憶體1716。快取記憶體1716可被組織成包括一或更多階快取記憶體的階層結構。
於某些實施例中,處理器1710包括記憶體控制器1714,其係可操作以履行致能處理器1710存取及通訊與記憶體1730(其包括揮發性記憶體1732及/或非揮發性記憶體1734)之功能。於某些實施例中,處理器1710係與記憶體1730及晶片組1720耦合。處理器1710亦可耦合至無線天線1778以與任何組態成傳輸及/或接收無線信號之裝置通訊。於一實施例中,無線天線1778之介面係依據(但不限定於)IEEE 802.11標準及其相關家族(家用插塞(Home Plug) AV(HPAV)、超寬頻帶(UWB)、藍牙、WiMax、或任何形式的無線通訊協定)而操作。
於某些實施例中,揮發性記憶體1732包括(但不限定於)同步動態隨機存取記憶體(SDRAM)、動態隨機存取記憶體(DRAM)、RAMBUS動態隨機存取記憶體(RDRAM)、及/或任何其他類型的隨機存取記憶體裝置。非揮發性記憶體1734包括(但不限定於)快閃記憶體、相變記憶體(PCM)、唯讀記憶體(ROM)、電可抹除可編程唯讀記憶體(EEPROM)、或任何其他類型的非揮發性記憶體裝置。
記憶體1730係儲存將由處理器1710所執行的資訊及指令。於一實施例中,記憶體1730亦可儲存暫時變數或其他中間資訊,在當處理器1710正執行指令時。於所示的實施例中,晶片組1720係經由點對點(PtP或P-P)介面1717及1722而與處理器1710連接。晶片組1720致能處理器1710連接至系統1700中之其他元件。於範例系統之某些實施例中,介面1717及1722係依據PtP通訊協定(諸如Intel® QuickPath Interconnect(QPI)等等)而操作。於其他實施例中,不同的互連可被使用。
於某些實施例中,晶片組1720係可操作以與以下通訊:處理器1710、1705N、顯示裝置1740、及其他裝置,包括匯流排橋1772、智慧型TV 1776、I/O裝置1774、非揮發性記憶體1760、儲存媒體(諸如一或更多大量儲存裝置)1762、鍵盤/滑鼠1764、網路介面1766、及各種形式的消費者電子設備1777(諸如PDA、智慧型手機、平板等等),等等)。於一實施例中,晶片組1720係透過介面1724而與這些裝置耦合。晶片組1720亦可耦合至無線天線1778以與任何組態成傳輸及/或接收無線信號之裝置通訊。
晶片組1720經由介面1726而連接至顯示裝置1740。顯示1740可為(例如)液晶顯示(LCD)、電漿顯示、陰極射線管(CRT)顯示、或任何其他形式的視覺顯示裝置。於範例系統之某些實施例中,處理器1710與晶片組1720被合併成單一SOC。此外,晶片組1720連接至一或更多匯流排1750及1755,其係互連系統各種系統元件,諸如I/O裝置1774、非揮發性記憶體1760、儲存媒體1762、鍵盤/滑鼠1764、及網路介面1766。匯流排1750及1755係經由匯流排橋1772而被互連在一起。
於一實施例中,大量儲存裝置1762包括(但不限定於)固態驅動、硬碟驅動、通用串列匯流排快閃記憶體驅動、或任何其他形式的電腦資料儲存媒體。於一實施例中,網路介面1766係藉由任何類型的眾所周知網路介面標準來實施,包括(但不限定於)乙太網路介面、通用串列匯流排(USB)介面、快速周邊組件互連(PCI)介面、無線介面及/或任何其他適當類型的介面。於一實施例中,無線介面係依據(但不限定於)IEEE 802.11標準及其相關家族(家用插塞(Home Plug)AV(HPAV)、超寬頻帶(UWB)、藍牙、WiMax、或任何形式的無線通訊協定)而操作。
雖然圖17中所示之模組被描繪為系統1700內之分離的區塊,但由這些區塊之部分所履行的功能可被集成於單一半導體電路內或者可使用二或更多分離的積體電路來實施。例如,雖然快取記憶體1716被描繪為處理器1710內之分離的區塊,但快取記憶體1716(或1716之選定的形態)可被結合入處理器核心1712內。
圖18顯示一種用以製造電子裝置(包括文中所述之電子裝置100的一或更多者)之方法1800的一範例。於描述方法1800時,參考了先前文中所述的一或更多組件、特徵、功能及操作。在方便時,係參考具有參考數字之組件、特徵、操作等等。所提供的參考數字是範例性的而非排他性的。例如,方法1800中所描述的組件、特徵、功能、操作等等包括(但不限定於)文中所提供的相應已編號元件及文中所述的其他相應元件(已編號及未編號兩者)以及其同等物。
在1802,方法1800可包括將第一晶粒110置於載體200之表面上。第一晶粒110可包括第一組晶粒接點(例如,圖2中所示之第一組晶粒接點230)。
在1804,方法1800可包括將第二晶粒120置於載體之表面上。第二晶粒120可被置於鄰近載體1200上之第一晶粒110。第二晶粒120可包括第二組晶粒接點(例如,圖2中所示之第四組晶粒接點260)。
在1806,方法1800可包括將第一橋互連140A置於鄰近第一晶粒110及第二晶粒120。第一橋互連140A可包括第一組橋接點310且可包括第二組橋接點320。
在1808,方法1800可包括將第一組橋接點310與第一晶粒110之第一組晶粒接點耦合。在1810,方法1800可包括將第二組橋接點320與第二晶粒120之第二組晶粒接點耦合。方法1800可包括將導電環氧樹脂塗敷至橋接點或晶粒接點,例如用以直接地耦合晶粒(例如,第一晶粒110)與橋互連140。
方法1800可包括將第三晶粒130置於鄰近第一晶粒120。第三晶粒130可包括第三組晶粒接點(例如,圖2中所示之第六組晶粒接點280)。第一晶粒110可包括第四組晶粒接點(例如,圖2中所示之第二組晶粒接點240)。
第三晶粒130可被置於第一晶粒110之第一側上,而第二晶粒120可被置於第一晶粒110之第二側上。第一晶粒110之第一側可與第一晶粒110之第二側相反。第四晶粒可被置於第一晶粒110之第三側上。額外晶粒(例如,第五晶粒)可被置於鄰近第一晶粒110。
方法1800可包括將第二橋互連140B置於鄰近第一晶粒110及第三晶粒130。第二橋互連140B可包括第三組橋接點及第四組橋接點。方法1800可包括將第三組橋接點與第三組晶粒接點耦合。方法1800可包括將第四組橋接點與第四組晶粒接點耦合。第一晶粒110與第三晶粒130可透過第二橋互連140B而電通訊。
橋互連140可促進介於二或更多晶粒之間的電通訊。方法1800可包括將第三晶粒130置於鄰近第二晶粒120。於一範例中,第一橋互連140A可被直接地耦合至第一晶粒110及第二晶粒120。第二橋互連140B可被直接地耦合至第二晶粒120及第三晶粒130。第三晶粒130可與第一晶粒110相通,包括(但不限定於)藉由透過第一橋互連140及第二橋互連140傳輸電信號以使第三晶粒130與第一晶粒110相通。
方法1800可包括直接地將第三組橋接點與(例如,第三晶粒130的)第三組晶粒接點耦合。橋互連140可促進介於第一晶粒110、第二晶粒120、及第三晶粒130之間的電通訊。
方法1800可包括將模製材料150與第一晶粒110、第二晶粒120、或橋互連140耦合。方法1800可包括形成(例如,利用消熔操作)第一開口(例如,圖5中所示之第一開口500),且第一開口可被界定於模製材料150中。於一範例中,載體200(顯示於圖2中)可包括透明材料。檢測器(例如,相機等等)可檢查來自載體200之第一側(例如,底部側)的基準標記。移除設備(例如,雷射)可被置於鄰近模製材料150(或電子裝置100)。移除設備可被置於載體200之第二側(例如,頂部側)上。其可從載體200之第一側觀察到的基準標記可被參考以放置移除設備。基準標記可被參考(例如)以使移除設備與晶粒(例如,第一晶粒110)之接點(例如,圖2之接點220)對準。移除設備可藉由移除模製材料150以形成開口,而開口可與電子裝置100之特徵(例如,接點)對準。電子裝置100可包括第二開口,且第二開口可暴露第二晶粒接點。
方法1800可包括藉由將導電材料(例如,銅等等)與第一開口及(例如)晶粒之接點耦合以在第一開口中形成通孔(例如,圖6中所示之第一通孔600)。方法1800可包括移除模製材料150之一部分及通孔(例如,藉由在研磨操作中移除材料)。橋互連之一部分可被移除(例如,研磨)自電子裝置100。模製材料150、通孔、及橋互連140之部分的移除可在相同操作中履行(例如,同時地研磨模製材料150、通孔、及橋互連140)。
方法1800可包括將第一晶粒110及第二晶粒120與基材160耦合。基材150可協助促進第一晶粒110及第二晶粒120與外部結構(例如,主機板或系統單晶片之組件)的互通。
方法1800可包括將橋互連通孔(例如,圖3中所示之橋通孔330)與基材160耦合。橋通孔可被包括在橋互連140中。橋通孔可協助建立介於第一晶粒110與基材160之間的電通訊路徑。方法1800可包括將下填材料置於橋互連140與基材160之間。
各個重點及範例
形態1可包括或使用請求標的(諸如設備、系統、裝置、方法、用以履行動作之機構、或裝置可讀取媒體,其包括當由裝置履行時可致使裝置履行動作之指令、或製造物件),諸如可包括或使用一種電子裝置。
該電子裝置可包括一第一晶粒。該第一晶粒可包括一第一組晶粒接點。該電子裝置可包括一第二晶粒。該第二晶粒可包括一第二組晶粒接點。該電子裝置可包括一橋互連。該橋互連可包括一第一組橋接點且可包括一第二組橋接點。
該第一組橋接點可被直接地耦合至該第一組晶粒接點,例如利用焊料。該第二組橋接點可被直接地耦合至該第二組晶粒接點,例如利用焊料。該橋互連可促進介於該第一晶粒與該第二晶粒之間的電通訊。
形態2可包括或使用(或可選擇性地與形態1之請求標的結合)以選擇性地包括或使用其該橋互連可包括一第三晶粒。該第三晶粒可被調整大小並調整形狀以重疊該第一晶粒之一部分及重疊該第二晶粒之一部分。
形態3可包括或使用,或可選擇性地與形態1或2之一者或任何組合的請求標的結合以選擇性地包括或使用其該第一晶粒與該第二晶粒可僅透過該橋互連而電通訊。
形態4可包括或使用,或可選擇性地與形態1至3之一者或任何組合的請求標的結合以選擇性地包括或使用一基材。該第一晶粒及該第二晶粒可被耦合至該基材。
形態5可包括或使用,或可選擇性地與形態4之請求標的結合以選擇性地包括或使用其該橋互連可被置於該第一晶粒與該基材之間。
形態6可包括或使用,或可選擇性地與形態5之請求標的結合以選擇性地包括或使用一下填材料,其可被置於該橋互連與該基材之間。
形態7可包括或使用,或可選擇性地與形態4之請求標的結合以選擇性地包括或使用一第一橋接點。該第一橋接點可被置於該橋互連之一第一表面上。該第一橋接點可被直接地耦合至該第一晶粒之一晶粒接點,例如利用焊料。該電子裝置100可包括一第二橋接點。該第二橋接點可被置於該橋互連之一第二表面上。該第二橋接點可被直接地耦合至該基材之一基材接點,例如利用焊料。
該電子裝置可包括一橋通孔。該橋通孔可被包括在該橋互連中。該橋通孔可將該第一橋接點與該第二橋接點電互連。該橋通孔可促進介於該第一晶粒與該基材之間的該電通訊。
形態8可包括或使用,或可選擇性地與形態7之請求標的結合以選擇性地包括或使用一下填材料。該下填材料可形成與該焊料之一直接介面,該焊料可將該第二橋接點與該基材接點直接地耦合。
形態9可包括或使用,或可選擇性地與形態1或8之一者或任何組合的請求標的結合以選擇性地包括或使用其該第一晶粒與該第二晶粒可為共面。
形態10可包括或使用,或可選擇性地與形態1至9之一者或任何組合的請求標的結合以選擇性地包括或使用一模製材料。該模製材料可形成與該第一晶粒、該第二晶粒、及該橋互連之一直接介面。
形態11可包括或使用,或可選擇性地與形態10之請求標的結合以選擇性地包括或使用一晶粒通孔。該晶粒通孔可與該第一晶粒耦合。該晶粒通孔可延伸通過該模製材料。
形態12可包括或使用,或可選擇性地與形態11之請求標的結合以選擇性地包括或使用其該橋互連可與該晶粒通孔之一部分共面。
形態13可包括或使用,或可選擇性地與形態11或12之一者或任何組合的請求標的結合以選擇性地包括或使用其該橋互連之一表面可與該模製材料之一表面共面。
形態14可包括或使用,或可選擇性地與形態1至13之一者或任何組合的請求標的結合以選擇性地包括或使用一第三組晶粒接點。該第三組晶粒接點可被包括在該第一晶粒中。該電子裝置可包括一晶粒通孔。該晶粒通孔可與該第三組晶粒接點耦合。該第一組晶粒接點可具有比該第三組晶粒接點更小的尺寸。
形態15可包括或使用請求標的(諸如設備、系統、裝置、方法、用以履行動作之機構、或裝置可讀取媒體,其包括當由裝置履行時可致使裝置履行動作之指令、或製造物件),諸如可包括或使用一種電子裝置。
該電子裝置可包括一基材。該電子裝置可包括一第一晶粒。該第一晶粒可被耦合至該基材。該第一晶粒可包括一第一組晶粒接點。該電子裝置可包括一第二晶粒。該第二晶粒可被耦合至該基材。該第二晶粒可包括一第二組晶粒接點。
該電子裝置可包括一第一橋互連。該第一橋互連可被分隔自該基材。該第一橋互連可包括一第一組橋接點。該第一橋互連可包括一第二組橋接點。該第一組橋接點可被直接地耦合至該第一組晶粒接點,例如利用一互連材料。該第二組橋接點可被直接地耦合至該第二組晶粒接點,例如利用該互連材料。該第一橋互連可促進介於該第一晶粒與該第二晶粒之間的電通訊。
形態16可包括或使用(或可選擇性地與形態15之請求標的結合)以選擇性地包括或使用其該第一橋互連可為一第三晶粒。
形態17可包括或使用,或可選擇性地與形態15或16之一者或任何組合的請求標的結合以選擇性地包括或使用其該第一晶粒與該第二晶粒可僅透過該第一橋互連而電通訊。
形態18可包括或使用,或可選擇性地與形態15至17之一者或任何組合的請求標的結合以選擇性地包括或使用一第三晶粒。該第三晶粒可被耦合至該基材。該第三晶粒可包括一第三組晶粒接點。該電子裝置可包括一第四組晶粒接點。該第四組晶粒接點可被包括在該第二晶粒中。
該電子裝置可包括一第二橋互連。該第二橋互連可被分隔自該基材。該第二橋互連可包括一第三組橋接點且可包括一第四組橋接點。該第三組橋接點可被直接地耦合至該第三組晶粒接點,例如利用該互連材料。該第四組橋接點可被直接地耦合至該第四組晶粒接點,例如利用該互連材料。該第二橋互連可促進介於該第二晶粒與該第三晶粒之間的電通訊。
形態19可包括或使用,或可選擇性地與形態18之請求標的結合以選擇性地包括或使用其該第一橋互連可與該第二橋互連共面。
形態20可包括或使用,或可選擇性地與形態15至19之一者或任何組合的請求標的結合以選擇性地包括或使用一第三晶粒。該第三晶粒可被耦合至該基材。該第三晶粒可包括一第三組晶粒接點。該電子裝置可包括一第三組橋接點。該第三組橋接點可被包括在該第一橋互連中。該第三組橋接點可被直接地耦合至該第三組晶粒接點,例如利用該互連材料。該第一橋互連可促進介於該第一晶粒、該第二晶粒、與該第三晶粒之間的電通訊。
形態21可包括或使用請求標的(諸如設備、系統、裝置、方法、用以履行動作之機構、或裝置可讀取媒體,其包括當由裝置履行時可致使裝置履行動作之指令、或製造物件),諸如可包括或使用一種用以製造電子裝置之方法。該方法可包括將一第一晶粒置於一載體之一表面上。該第一晶粒可包括一第一組晶粒接點。
該方法可包括將一第二晶粒置於該載體之該表面上。該第二晶粒可被置於鄰近(例如,相鄰等等)該載體上之該第一晶粒。該第二晶粒可包括一第二組晶粒接點。該方法可包括將一第一橋互連置於鄰近該第一晶粒及該第二晶粒。該第一橋互連可包括一第一組橋接點及一第二組橋接點。
該方法可包括將該第一組橋接點與該第一晶粒之該第一組晶粒接點直接地耦合。該方法可包括將該第二組橋接點與該第二晶粒之該第二組晶粒接點直接地耦合。
形態22可包括或使用,或可選擇性地與形態21之請求標的結合以選擇性地包括或使用將一第三晶粒置於鄰近該第一晶粒。該第三晶粒可包括一第三組晶粒接點。該第一晶粒可包括一第四組晶粒接點。該方法可包括將一第二橋互連置於鄰近該第一晶粒及該第三晶粒。該第二橋互連可包括一第三組橋接點且可包括一第四組橋接點。該方法可包括將該第三組橋接點與該第三組晶粒接點耦合。該方法可包括將該第四組橋接點與該第四組晶粒接點直接地耦合。
形態23可包括或使用,或可選擇性地與形態21或22之一者或任何組合的請求標的結合以選擇性地包括或使用將一模製材料與該第一晶粒、該第二晶粒、及該第一橋互連耦合。
形態24可包括或使用,或可選擇性地與形態23之請求標的結合以選擇性地包括或使用一形成一第一開口。該第一開口可被界定在該模製材料中。該第一開口可暴露該第一晶粒之一第一晶粒接點。
形態25可包括或使用,或可選擇性地與形態24之請求標的結合以選擇性地包括或使用其該載體可包括一透明材料。該第一開口之該形成可包括檢查來自該透明載體之一第一側的基準標記。該第一開口之該形成可包括將一移除設備置於鄰近該透明載體之一第二側上的該模製材料。放置該移除設備可包括參考該透明載體之該第一側上所檢查的基準標記。該第一開口之該形成可包括移除該模製材料之一部分並形成該第一開口。
形態26可包括或使用,或可選擇性地與形態23至25之一者或任何組合的請求標的結合以選擇性地包括或使用形成一第二開口。該第二開口可被界定在該模製材料中。該第二開口可暴露該第二晶粒之一第二晶粒接點。
形態27可包括或使用,或可選擇性地與形態23至26之一者或任何組合的請求標的結合以選擇性地包括或使用形成一通孔。該通孔可被形成在該第一開口中,例如藉由將一導電材料與該第一開口及該第一晶粒之該第一接點耦合。
形態28可包括或使用,或可選擇性地與形態23至27之一者或任何組合的請求標的結合以選擇性地包括或使用移除該模製材料及該通孔之一部分。
形態29可包括或使用,或可選擇性地與形態28之請求標的結合以選擇性地包括或使用移除該橋互連之一部分。
形態30可包括或使用,或可選擇性地與形態21或29之一者或任何組合的請求標的結合以選擇性地包括或使用其將該第一組橋接點與該第一組晶粒接點耦合可包括塗敷一導電環氧樹脂至該第一組橋接點或該第一組晶粒接點。
形態31可包括或使用,或可選擇性地與形態21至30之一者或任何組合的請求標的結合以選擇性地包括或使用將該第一晶粒及該第二晶粒與一基材耦合。
形態32可包括或使用,或可選擇性地與形態31之請求標的結合以選擇性地包括或使用將一橋通孔與該基材耦合。該橋通孔可被包括在該橋互連中。該橋通孔可建立介於該第一晶粒與該基材之間的電通訊路徑。
形態33可包括或使用,或可選擇性地與形態31或32之一者或任何組合的請求標的結合以選擇性地包括或使用將一下填材料置於該橋互連與該基材之間。
形態34可包括或使用,或可選擇性地與形態1至33之任何一或更多者的任何部分之任何部分或組合結合以包括或使用其可包括以下之請求標的:用以履行形態1至33之功能的任何一或更多者之機構、或包括指令之機器可讀取媒體,當由機器所履行時該等指令係致使該機器履行形態1至33之功能的任何一或更多者。
這些非限制性範例之各者可各自獨立,或者可與其他範例之一或更多者結合以各種排列或組合。
以上描述包括對於附圖之參考,該等附圖係形成詳細描述之一部分。該等圖形係顯示(藉由繪示之方式)其中可實現本發明的特定實施例。這些實施例於文中亦稱為「範例」。此等範例可包括除了那些已顯示或已描述者之外的元件。然而,本案發明人亦考量僅提供了那些已顯示或已描述之元件的範例。此外,本案發明人亦考量使用那些已顯示或已描述之元件(或其一或更多形態)的任何組合或排列之範例,無論是針對特定範例(或其一或更多形態),或者是針對其他範例(或其一或更多形態),如文中所述者。
在本文件與任何藉參考而併入的任何文件之間的不一致使用之情況中,以本文件之使用為主。
於此文件中,使用了術語「一(a)」或「一(an)」(如專利文件中所常見者)以包括一個或多於一個,無關於「至少一」或「一或更多」之任何其他實例或使用。於此文件中,使用了術語「或」以指稱非排他的或,以使得「A或B」包括了「A但非B」、「B但非A」、及「A與B」,除非另有指示。於此文件中,術語「包括」及「其中」被使用為個別術語「包含」及「其中」的一般英文同語詞。同時,於以下申請專利範圍中,術語「包括」及「包含」為開放式的,亦即,一種包括在申請專利範圍中之此一術語後所列出之那些以外的元件之系統、裝置、物件、組成、成分、或製程仍被視為落入該項申請專利範圍之範圍內。此外,於以下申請專利範圍中,術語「第一」、「第二」、及「第三」等等僅被使用為標籤,而不是為了要加諸數字的要求於其目標上。
幾何術語(諸如「平行」、「垂直」、「圓」、或「方」)並不想要要求絕對的數學上精確度,除非其背景另有指示。反之,此等幾何術語容許由於製造或同等功能之變異。例如,假如元件被描述為「圓的」或「一般地圓的」,則一並非精確地為圓形之組件(例如,稍微橢圓形者或多邊的多邊形者)仍由本描述所涵蓋。
文中所述之方法範例可為至少部分地機器或電腦實施的。一些範例可包括以指令編碼之電腦可讀取媒體或機器可讀取媒體,該等指令可操作以組態一種電子裝置來履行如以上範例中所述之方法。此等方法之實施方式可包括碼,諸如微碼、組合語言碼、較高階語言碼,等等。此碼可包括用以履行各種方法之電腦可讀取指令。該碼可形成電腦程式產品之部分。再者,於一範例中,該碼可被有形地儲存在一或更多揮發性、非暫態、或非揮發性有形電腦可讀取媒體上,諸如於執行期間或者在其他時間。這些有形電腦可讀取媒體之範例可包括(但不限定於)硬碟、可移除磁碟、可移除光碟(例如,光碟及數位視頻碟)、磁帶、記憶卡或棒、隨機存取記憶體(RAM)、唯讀記憶體(ROM),等等。
上述描述係為了說明性,而非限制性。例如,上述範例(或其一或更多形態)可彼此結合地使用。於閱讀以上描述後其他實施例可被使用,諸如由本技術領域中具有通常知識者。提供了摘要以符合37 C.F.R. §1.72(b),來容許讀者快速地確認技術內容之本質。應理解其不應被用來解讀或限制申請專利範圍之範圍或意義。同時,於以上詳細描述中,各種特徵可被群集在一起以簡化本發明。此不應被解讀為認為其未納入申請專利範圍之已揭露特徵為任何申請專利範圍之基本必要的。反之,具發明性的請求標的可存在於特定已揭露實施例之少於所有特徵內。因此,以下申請專利範圍於此被併入詳細描述而成為範例或實施例,以各申請專利範圍獨立為分離的實施例,已考量其此等實施例可以各種結合或排列方式來彼此結合。本發明之範圍應參考後附申請專利範圍(連同此等申請專利範圍所主張之同等物的完整範圍)來判定。
100:電子裝置
110:第一晶粒
120:第二晶粒
130:第三晶粒
140:橋互連
140A:第一橋互連
140B:第二橋互連
150:模製材料
150A:第一層
150B:第二層
160:基材
170:下填材料
180:焊料凸塊
200:載體
210:黏著劑
220:接點
230:第一組晶粒接點
240:第二組晶粒接點
250:第三組晶粒接點
260:第四組晶粒接點
270:第五組接點
280:第六組晶粒接點
290:第七組晶粒接點
300:凸塊
310:第一組橋接點
320:第二組橋接點
330:第一側
340:第二側
350:橋通孔
400:互連材料
500:第一開口
510:第二開口
600:晶粒通孔
610:第一表面
620:第二表面
630:第三表面
640:單元
710:焊料凸塊
800:橋通孔
900:晶粒接點
910:晶粒接點表面
920:模製表面
1000:層
1100:開口
1200:導電柱
1400:過量部分
1410:第一表面
1420:第二表面
1510:導電柱
1520:焊球
1600:集成散熱件
1610:介面材料
1700:系統
1705:處理器
1710:處理器
1712,1712N:處理器核心
1714:記憶體控制器
1716:快取記憶體
1717,1722:介面
1720:晶片組
1724,1726:介面
1730:記憶體
1732:揮發性記憶體
1734:非揮發性記憶體
1740:顯示裝置
1750,1755:匯流排
1760:非揮發性記憶體
1762:儲存媒體
1764:鍵盤/滑鼠
1766:網路介面
1772:匯流排橋
1774:I/O裝置
1776:智慧型TV
1777:消費者電子設備
1778:無線天線
於圖形(其不一定依比例繪製)中,類似的數字可描述不同視圖中之類似的組件。具有不同文字字尾之類似數字可代表類似組件之不同實例。圖形通常係繪示(以範例之方式,但非以限制之方式)本文件中所討論的各個實施例。
[圖1]繪示電子裝置之一範例的概圖,依據本請求標的之範例。
[圖2]繪示於製造操作期間之電子裝置的概圖,依據本請求標的之範例。
[圖3]繪示橋互連之概圖。
[圖4]繪示於製造操作期間之電子裝置的概圖,依據本請求標的之範例。
[圖5]繪示於製造操作期間之電子裝置的概圖,依據本請求標的之範例。
[圖6]繪示於製造操作期間之電子裝置的概圖,依據本請求標的之範例。
[圖7]繪示於製造操作期間之電子裝置的概圖,依據本請求標的之範例。
[圖8]繪示於圖7之圓圈8-8上的電子裝置100之詳細概圖,依據本請求標的之範例。
[圖9]繪示於製造操作期間之電子裝置的概圖,依據本請求標的之範例。
[圖10]繪示於製造操作期間之電子裝置的概圖,依據本請求標的之範例。
[圖11]繪示於製造操作期間之電子裝置的概圖,依據本請求標的之範例。
[圖12]繪示於製造操作期間之電子裝置的概圖,依據本請求標的之範例。
[圖13]繪示於製造操作期間之電子裝置的概圖,依據本請求標的之範例。
[圖14]繪示於製造操作期間之電子裝置的概圖,依據本請求標的之範例。
[圖15]繪示於製造操作期間之電子裝置的概圖,依據本請求標的之範例。
[圖16]繪示於製造操作期間之電子裝置的概圖,依據本請求標的之範例。
[圖17]繪示系統階圖,其係描繪一種包括如本揭露中所描述之電子裝置的電子系統之範例。
[圖18]繪示一種用以製造電子裝置之方法。
100:電子裝置
110:第一晶粒
120:第二晶粒
130:第三晶粒
140:橋互連
150:模製材料
160:基材
170:下填材料
180:焊料凸塊
Claims (23)
- 一種多晶片封裝,包含:一橋互連,在一模製材料中,該橋互連包含第一複數個橋接點及第二複數個橋接點,且該橋互連具有一最底表面;一第一晶粒通孔及一第二晶粒通孔,在該模製材料中,該第一晶粒通孔及該第二晶粒通孔橫向鄰近該橋互連的一第一側,且該第一晶粒通孔及該第二晶粒通孔各具有與該橋互連的該最底表面共面之一最底表面;一第三晶粒通孔及一第四晶粒通孔,在該模製材料中,該第三晶粒通孔及該第四晶粒通孔橫向鄰近該橋互連的一第二側,該第二側相對於該第一側,且該第三晶粒通孔及該第四晶粒通孔各具有與該橋互連的該最底表面共面之一最底表面;一第一晶粒電耦合至該橋互連之該第一複數個橋接點,且該第一晶粒電耦合至該第一晶粒通孔及該第二晶粒通孔;以及一第二晶粒電耦合至該橋互連之該第二複數個橋接點,且該第二晶粒電耦合至該第三晶粒通孔及該第四晶粒通孔。
- 如請求項1之多晶片封裝,其中,該橋互連與該模製材料直接接觸。
- 如請求項1之多晶片封裝,其中,該第一晶粒通孔、該第二晶粒通孔、該第三晶粒通孔及該第四晶 粒通孔與該模製材料直接接觸。
- 如請求項1之多晶片封裝,其中,該橋互連與該模製材料直接接觸,以及其中,該第一晶粒通孔、該第二晶粒通孔、該第三晶粒通孔及該第四晶粒通孔與該模製材料直接接觸。
- 如請求項1之多晶片封裝,其中,該模製材料具有與該橋互連的該最底表面共面之一最底表面。
- 如請求項1之多晶片封裝,更包含:一第二橋互連,在該模製材料中,其中該第一晶粒或該第二晶粒其中之一耦合至該第二橋互連;以及一第三晶粒電耦合至該第二橋互連。
- 如請求項1之多晶片封裝,更包含:一基材,在該模製材料下方;以及一下填材料,於該模製材料與該基材之間。
- 如請求項7之多晶片封裝,其中,該下填材料更沿該模製材料的一側。
- 如請求項1之多晶片封裝,其中,該橋互連更包含一橋通孔。
- 如請求項9之多晶片封裝,其中,該橋通孔係一穿越矽通孔。
- 如請求項1之多晶片封裝,其中,該第一晶粒通孔、該第二晶粒通孔、該第三晶粒通孔及該第四晶粒通孔延伸至該橋互連上方。
- 如請求項1之多晶片封裝,其中,該模 製材料更橫向位於該第一晶粒與該第二晶粒之間。
- 一種多晶片封裝,包含:一橋互連,在一模製材料中,該橋互連包含在一最上表面上的第一複數個橋接點及第二複數個橋接點,且該橋互連具有在一最底表面上的第三複數個橋接點;一第一晶粒通孔及一第二晶粒通孔,在該模製材料中,該第一晶粒通孔及該第二晶粒通孔橫向鄰近該橋互連的一第一側;一第三晶粒通孔及一第四晶粒通孔,在該模製材料中,該第三晶粒通孔及該第四晶粒通孔橫向鄰近該橋互連的一第二側,該第二側相對於該第一側;一第一晶粒電耦合該橋互連之該第一複數個橋接點,且該第一晶粒電耦合至該第一晶粒通孔及該第二晶粒通孔;以及一第二晶粒電耦合至該橋互連之該第二複數個橋接點,且該第二晶粒電耦合至該第三晶粒通孔及該第四晶粒通孔。
- 如請求項13之多晶片封裝,其中,該橋互連與該模製材料直接接觸。
- 如請求項13之多晶片封裝,其中,該第一晶粒通孔、該第二晶粒通孔、該第三晶粒通孔及該第四晶粒通孔與該模製材料直接接觸。
- 如請求項13之多晶片封裝,其中,該橋互連與該模製材料直接接觸,以及其中,該第一晶粒通 孔、該第二晶粒通孔、該第三晶粒通孔及該第四晶粒通孔與該模製材料直接接觸。
- 如請求項13之多晶片封裝,更包含:一第二橋互連,在該模製材料中,其中該第一晶粒或該第二晶粒其中之一耦合至該第二橋互連;以及一第三晶粒電耦合至該第二橋互連。
- 如請求項13之多晶片封裝,更包含:一基材,在該模製材料下方;以及一下填材料,於該模製材料與該基材之間。
- 如請求項18之多晶片封裝,其中,該下填材料更沿該模製材料的一側。
- 如請求項13之多晶片封裝,其中,該橋互連更包含一橋通孔。
- 如請求項20之多晶片封裝,其中,該橋通孔係一穿越矽通孔。
- 如請求項13之多晶片封裝,其中,該第一晶粒通孔、該第二晶粒通孔、該第三晶粒通孔及該第四晶粒通孔延伸至該橋互連上方。
- 如請求項13之多晶片封裝,其中,該模製材料更橫向位於該第一晶粒與該第二晶粒之間。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US15/996,870 US10700051B2 (en) | 2018-06-04 | 2018-06-04 | Multi-chip packaging |
US15/996,870 | 2018-06-04 |
Publications (2)
Publication Number | Publication Date |
---|---|
TW202232709A TW202232709A (zh) | 2022-08-16 |
TWI828121B true TWI828121B (zh) | 2024-01-01 |
Family
ID=68693618
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW111115241A TWI828121B (zh) | 2018-06-04 | 2019-04-25 | 多晶片封裝 |
TW108114442A TWI808163B (zh) | 2018-06-04 | 2019-04-25 | 多晶片封裝 |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW108114442A TWI808163B (zh) | 2018-06-04 | 2019-04-25 | 多晶片封裝 |
Country Status (6)
Country | Link |
---|---|
US (5) | US10700051B2 (zh) |
EP (5) | EP4325552A2 (zh) |
KR (3) | KR20220054893A (zh) |
CN (3) | CN111886693A (zh) |
TW (2) | TWI828121B (zh) |
WO (1) | WO2019236226A1 (zh) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR102397902B1 (ko) * | 2018-01-29 | 2022-05-13 | 삼성전자주식회사 | 반도체 패키지 |
US10700051B2 (en) | 2018-06-04 | 2020-06-30 | Intel Corporation | Multi-chip packaging |
US10879155B2 (en) * | 2019-05-09 | 2020-12-29 | Texas Instruments Incorporated | Electronic device with double-sided cooling |
US11315902B2 (en) * | 2020-02-12 | 2022-04-26 | International Business Machines Corporation | High bandwidth multichip module |
US11955448B2 (en) * | 2020-05-21 | 2024-04-09 | Intel Corporation | Architecture to manage FLI bump height delta and reliability needs for mixed EMIB pitches |
US11728254B2 (en) * | 2020-05-22 | 2023-08-15 | Taiwan Semiconductor Manufacturing Co., Ltd. | Giga interposer integration through chip-on-wafer-on-substrate |
US20220199562A1 (en) * | 2020-12-22 | 2022-06-23 | Intel Corporation | Assembly of 2xd module using high density interconnect bridges |
US20220208712A1 (en) * | 2020-12-28 | 2022-06-30 | Advanced Micro Devices, Inc. | Multi-level bridge interconnects |
US20230095134A1 (en) * | 2021-09-29 | 2023-03-30 | Taiwanj Semiconductor Manufacturing Co., Ltd. | Method and structure for a bridge interconnect |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20170110407A1 (en) * | 2015-10-16 | 2017-04-20 | Xilinx, Inc. | Interposer-less stack die interconnect |
US20170125379A1 (en) * | 2015-10-30 | 2017-05-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Stacked Integrated Circuit Structure and Method of Forming |
Family Cites Families (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4581768B2 (ja) * | 2005-03-16 | 2010-11-17 | ソニー株式会社 | 半導体装置の製造方法 |
CN101232004A (zh) * | 2007-01-23 | 2008-07-30 | 联华电子股份有限公司 | 芯片堆叠封装结构 |
US9059179B2 (en) * | 2011-12-28 | 2015-06-16 | Broadcom Corporation | Semiconductor package with a bridge interposer |
US8704364B2 (en) * | 2012-02-08 | 2014-04-22 | Xilinx, Inc. | Reducing stress in multi-die integrated circuit structures |
JP6195995B2 (ja) * | 2014-02-26 | 2017-09-20 | インテル コーポレイション | ブリッジ貫通導電ビア信号接続を有する埋込マルチデバイスブリッジ |
US20150364422A1 (en) * | 2014-06-13 | 2015-12-17 | Apple Inc. | Fan out wafer level package using silicon bridge |
US9595496B2 (en) | 2014-11-07 | 2017-03-14 | Qualcomm Incorporated | Integrated device package comprising silicon bridge in an encapsulation layer |
US9418966B1 (en) | 2015-03-23 | 2016-08-16 | Xilinx, Inc. | Semiconductor assembly having bridge module for die-to-die interconnection |
US9653428B1 (en) * | 2015-04-14 | 2017-05-16 | Amkor Technology, Inc. | Semiconductor package and fabricating method thereof |
US9595494B2 (en) | 2015-05-04 | 2017-03-14 | Qualcomm Incorporated | Semiconductor package with high density die to die connection and method of making the same |
US20160343685A1 (en) * | 2015-05-21 | 2016-11-24 | Mediatek Inc. | Semiconductor package assembly and method for forming the same |
CN108292654A (zh) * | 2015-12-11 | 2018-07-17 | 英特尔公司 | 具有利用嵌入微电子衬底中的微电子桥连接的多个微电子器件的微电子结构 |
TWI652778B (zh) * | 2016-01-27 | 2019-03-01 | 艾馬克科技公司 | 半導體封裝以及其製造方法 |
US9761559B1 (en) | 2016-04-21 | 2017-09-12 | Micron Technology, Inc. | Semiconductor package and fabrication method thereof |
WO2018009145A1 (en) * | 2016-07-08 | 2018-01-11 | Agency For Science, Technology And Research | A semiconductor package and methods of forming the same |
US10510721B2 (en) * | 2017-08-11 | 2019-12-17 | Advanced Micro Devices, Inc. | Molded chip combination |
US10700051B2 (en) | 2018-06-04 | 2020-06-30 | Intel Corporation | Multi-chip packaging |
-
2018
- 2018-06-04 US US15/996,870 patent/US10700051B2/en active Active
-
2019
- 2019-04-25 TW TW111115241A patent/TWI828121B/zh active
- 2019-04-25 TW TW108114442A patent/TWI808163B/zh active
- 2019-05-03 EP EP23219820.0A patent/EP4325552A2/en active Pending
- 2019-05-03 EP EP23176064.6A patent/EP4235755A3/en active Pending
- 2019-05-03 WO PCT/US2019/030614 patent/WO2019236226A1/en unknown
- 2019-05-03 KR KR1020227013121A patent/KR20220054893A/ko not_active Application Discontinuation
- 2019-05-03 CN CN201980021961.1A patent/CN111886693A/zh active Pending
- 2019-05-03 KR KR1020237042877A patent/KR20240001718A/ko not_active Application Discontinuation
- 2019-05-03 CN CN202311804371.0A patent/CN117794254A/zh active Pending
- 2019-05-03 EP EP19814378.6A patent/EP3803973A4/en not_active Withdrawn
- 2019-05-03 EP EP22171597.2A patent/EP4060733A3/en active Pending
- 2019-05-03 CN CN202311804375.9A patent/CN117794255A/zh active Pending
- 2019-05-03 EP EP21210501.9A patent/EP3982407A3/en active Pending
- 2019-05-03 KR KR1020207027577A patent/KR20210004963A/ko not_active Application Discontinuation
-
2020
- 2020-06-04 US US16/892,698 patent/US11348911B2/en active Active
-
2022
- 2022-01-28 US US17/587,657 patent/US11817444B2/en active Active
- 2022-04-08 US US17/716,934 patent/US20220231007A1/en active Pending
-
2023
- 2023-12-27 US US18/397,891 patent/US20240128256A1/en active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20170110407A1 (en) * | 2015-10-16 | 2017-04-20 | Xilinx, Inc. | Interposer-less stack die interconnect |
US20170125379A1 (en) * | 2015-10-30 | 2017-05-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Stacked Integrated Circuit Structure and Method of Forming |
Also Published As
Publication number | Publication date |
---|---|
EP3803973A4 (en) | 2022-06-29 |
TW202339177A (zh) | 2023-10-01 |
US10700051B2 (en) | 2020-06-30 |
EP4235755A3 (en) | 2024-02-21 |
US20220157803A1 (en) | 2022-05-19 |
TWI808163B (zh) | 2023-07-11 |
WO2019236226A1 (en) | 2019-12-12 |
EP3982407A3 (en) | 2022-07-20 |
EP4060733A3 (en) | 2022-11-16 |
KR20210004963A (ko) | 2021-01-13 |
US11348911B2 (en) | 2022-05-31 |
KR20220054893A (ko) | 2022-05-03 |
EP3803973A1 (en) | 2021-04-14 |
EP4325552A2 (en) | 2024-02-21 |
US20200395352A1 (en) | 2020-12-17 |
TW202232709A (zh) | 2022-08-16 |
US20190371778A1 (en) | 2019-12-05 |
EP4235755A2 (en) | 2023-08-30 |
EP3982407A2 (en) | 2022-04-13 |
TW202011559A (zh) | 2020-03-16 |
EP4060733A2 (en) | 2022-09-21 |
CN111886693A (zh) | 2020-11-03 |
KR20240001718A (ko) | 2024-01-03 |
US20240128256A1 (en) | 2024-04-18 |
US20220231007A1 (en) | 2022-07-21 |
US11817444B2 (en) | 2023-11-14 |
CN117794255A (zh) | 2024-03-29 |
CN117794254A (zh) | 2024-03-29 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TWI828121B (zh) | 多晶片封裝 | |
US11764158B2 (en) | Embedded multi-die interconnect bridge packages with lithographically formed bumps and methods of assembling same | |
US11270941B2 (en) | Bare-die smart bridge connected with copper pillars for system-in-package apparatus | |
US11658111B2 (en) | Stripped redistrubution-layer fabrication for package-top embedded multi-die interconnect bridge | |
TW202347661A (zh) | 晶粒鋪設技術 | |
TWI835658B (zh) | 多晶片封裝 | |
US20220238440A1 (en) | Bare-die smart bridge connected with copper pillars for system-in-package apparatus | |
TW202416494A (zh) | 多晶片封裝 | |
US20220115323A1 (en) | Bare-die smart bridge connected with copper pillars for system-in-package apparatus | |
TW202331991A (zh) | 嵌入式玻璃核心貼片 |