CN111886693A - 多芯片封装 - Google Patents

多芯片封装 Download PDF

Info

Publication number
CN111886693A
CN111886693A CN201980021961.1A CN201980021961A CN111886693A CN 111886693 A CN111886693 A CN 111886693A CN 201980021961 A CN201980021961 A CN 201980021961A CN 111886693 A CN111886693 A CN 111886693A
Authority
CN
China
Prior art keywords
die
bridge
contacts
electronic device
interconnect
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201980021961.1A
Other languages
English (en)
Inventor
R·L·桑克曼
S·阿格拉哈拉姆
欧盛荃
T·J·德博尼斯
T·斯彭策
孙扬
王国弢
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Priority to CN202311804371.0A priority Critical patent/CN117794254A/zh
Priority to CN202311804375.9A priority patent/CN117794255A/zh
Publication of CN111886693A publication Critical patent/CN111886693A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568Temporary substrate used as encapsulation process aid
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135Double encapsulation or coating and encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157Partial encapsulation or coating
    • H01L23/3185Partial encapsulation or coating the coating covering also the sidewalls of the semiconductor body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5381Crossover interconnections, e.g. bridge stepovers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5385Assembly of a plurality of insulating substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/07Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/08Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19Manufacturing methods of high density interconnect preforms
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0652Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544Marks applied to semiconductor devices or parts
    • H01L2223/54426Marks applied to semiconductor devices or parts for alignment
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0556Disposition
    • H01L2224/0557Disposition the external layer being disposed on a via connection of the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601Structure
    • H01L2224/0603Bonding areas having different sizes, e.g. different heights or widths
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061Disposition
    • H01L2224/0618Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/06181On opposite sides of the body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/07Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/081Disposition
    • H01L2224/0812Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/08135Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/08145Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/07Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/081Disposition
    • H01L2224/0812Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/08151Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/08221Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/08225Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/11011Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
    • H01L2224/11013Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the bump connector, e.g. solder flow barrier
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/13198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/13199Material of the matrix
    • H01L2224/1329Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/13198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/13298Fillers
    • H01L2224/13299Base material
    • H01L2224/133Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16135Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16238Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/1701Structure
    • H01L2224/1703Bump connectors having different sizes, e.g. different diameters, heights or widths
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/1705Shape
    • H01L2224/17051Bump connectors having different shapes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/171Disposition
    • H01L2224/1718Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/17181On opposite sides of the body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73209Bump and HDI connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73253Bump and layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81001Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/81005Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119Arrangement of the bump connectors prior to mounting
    • H01L2224/81191Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119Arrangement of the bump connectors prior to mounting
    • H01L2224/81192Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81986Specific sequence of steps, e.g. repetition of manufacturing steps, time sequence
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/82009Pre-treatment of the connector or the bonding area
    • H01L2224/8203Reshaping, e.g. forming vias
    • H01L2224/82035Reshaping, e.g. forming vias by heating means
    • H01L2224/82039Reshaping, e.g. forming vias by heating means using a laser
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/9202Forming additional connectors after the connecting process
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/922Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222Sequential connecting processes
    • H01L2224/92222Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92224Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a build-up interconnect
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/95001Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06513Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06517Bump or bump-like direct electrical connections from device to substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06541Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06555Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06562Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06582Housing for the assembly, e.g. chip scale package [CSP]
    • H01L2225/06586Housing with external bump or bump-like connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1517Multilayer substrate
    • H01L2924/15192Resurf arrangement of the internal vias
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/162Disposition
    • H01L2924/16251Connecting to an item not being a semiconductor or solid-state body, e.g. cap-to-substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • H01L2924/1815Shape
    • H01L2924/1816Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161Exposing the passive side of the semiconductor or solid-state body of a flip chip
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • H01L2924/1815Shape
    • H01L2924/1816Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Combinations Of Printed Boards (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Geometry (AREA)
  • Wire Bonding (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Packaging Frangible Articles (AREA)

Abstract

电子设备可以包括第一管芯,该第一管芯可以包括第一组管芯触点。该电子设备可以包括第二管芯,该第二管芯可以包括第二组管芯触点。该电子设备可以包括桥式互连件,该桥式互连件可以包括第一组桥式触点并且可以包括第二组桥式触点。第一组桥式触点可以直接耦合到第一组管芯触点(例如,利用诸如焊料之类的互连材料)。第二组桥式触点可以直接耦合到第二组管芯触点(例如,利用焊料)。桥式互连件可以帮助便于第一管芯与第二管芯之间的电连通。

Description

多芯片封装
优先权
本专利申请要求于2018年6月4日提交的美国申请序列号15/996,870的优先权权益,其全部内容通过引用合并于本文中。
背景技术
电子设备可以包括多个集成电路。集成电路可以通过衬底中的一个或多个布线迹线进行电连通。管芯可以被包括在衬底中以帮助便于多个集成电路之间的电连通。
附图说明
在不一定按比例绘制的附图中,相似的数字在不同的视图中可以描述相似的组件。具有不同字母后缀的相似数字可以表示类似组件的不同实例。附图作为示例而非作为限制大体上图示了本文档中所讨论的各种实施例。
图1图示了根据本主题的示例的电子设备的一个示例的示意图。
图2图示了根据本主题的示例的电子设备在制造操作期间的示意图。
图3图示了桥式互连件的示意图。
图4图示了根据本主题的示例的电子设备在制造操作期间的示意图。
图5图示了根据本主题的示例的电子设备在制造操作期间的示意图。
图6图示了根据本主题的示例的电子设备在制造操作期间的示意图。
图7图示了根据本主题的示例的电子设备在制造操作期间的示意图。
图8图示了根据本主题的示例的在图7的圆圈8-8处的电子设备100的详细示意图。
图9图示了根据本主题的示例的电子设备在制造操作期间的示意图。
图10图示了根据本主题的示例的电子设备在制造操作期间的示意图。
图11图示了根据本主题的示例的电子设备在制造操作期间的示意图。
图12图示了根据本主题的示例的电子设备在制造操作期间的示意图。
图13图示了根据本主题的示例的电子设备在制造操作期间的示意图。
图14图示了根据本主题的示例的电子设备在制造操作期间的示意图。
图15图示了根据本主题的示例的电子设备在制造操作期间的示意图。
图16图示了根据本主题的示例的电子设备在制造操作期间的示意图。
图17图示了系统级示图,其描绘了包括如本公开中所描述的电子设备的电子系统的示例。
图18图示了用于制造电子设备的方法。
具体实施方式
本发明的发明人已经意识到,除了其他之外,要解决的问题可以包括改进多个管芯之间的电连通,诸如通过减少多个管芯之间的信号损失或干扰的量。本主题可以诸如通过提供电子设备来帮助提供对该问题的解决方案。
该电子设备可以包括第一管芯,该第一管芯可以包括第一组管芯触点。该电子设备可以包括第二管芯,该第二管芯可以包括第二组管芯触点。该电子设备可以包括桥式互连件,该桥式互连件可以包括第一组桥式触点并且可以包括第二组桥式触点。第一组桥式触点可以直接耦合到第一组管芯触点(例如,利用诸如焊料之类的互连材料)。第二组桥式触点可以直接耦合到第二组管芯触点(例如,利用焊料)。桥式互连件可以帮助便于第一管芯与第二管芯之间的电连通。
桥式互连件可以帮助减少在衬底中包括用以容纳管芯的空腔从而将第一管芯与第二管芯电互连的需要。桥式互连件可以诸如通过减小信号在第一管芯与第二管芯之间行进的长度来帮助减少第一管芯与第二管芯之间的信号损失和干扰。桥式互连件由此可以帮助减少与制造电子设备相关联的制造成本,诸如通过改进制造过程成品率或减少与制造电子设备相关联的制造过程的复杂性。
该概述意图提供本专利申请的主题的概述。并不意图提供本发明的排他性或详尽的解释。详细描述被包括以提供关于本专利申请的进一步信息。
图1图示了电子设备100的一个示例的示意图。该电子设备可以包括第一管芯110,可以包括第二管芯120,并且可以包括第三管芯130。第一管芯110、第二管芯120或第三管芯130可以包括半导体材料。第一管芯110、第二管芯120和第三管芯130可以包括处理器管芯、存储器管芯、通信管芯(例如,WiFi、蓝牙或蜂窝的)等等。
电子设备100可以包括桥式互连件140。桥式互连件140可以帮助便于电子设备100内的电连通,诸如第一管芯110与第二管芯120之间的电连通。桥式互连件140可以诸如利用互连材料(例如,焊料、导电环氧树脂等等)、或者利用管芯和桥式互连件140的直接结合(例如,包括紧密触点的结合)来与第一管芯110、第二管芯120和/或第三管芯130耦合。
电子设备100可以包括模制材料150。模制材料150可以与第一管芯110、第二管芯120、第三管芯130的一部分耦合(例如,与其形成直接接口或封装它们),或者可以与桥式互连件140的一部分耦合。模制材料150可以帮助向电子设备100提供机械支撑。模制材料150可以包括填充的聚合物材料。模制材料150可以被沉积、形成、注入、旋转等等,并且由此与电子设备100的组件(诸如第一管芯110或桥式互连件140)耦合。
电子设备100可以包括衬底160。衬底160可以包括介电材料,并且可以包括导电材料。衬底160可以包括可以被适配成传输电信号的一个或多个路由层。第一管芯110、第二管芯120和/或第三管芯130可以诸如利用互连材料或利用管芯和衬底160的直接结合来耦合到衬底160。衬底160可以耦合到附加结构(例如,母板、另一衬底、片上系统等等)(并且与其电连通)。电子设备100可以包括焊料凸块180,该焊料凸块180可以便于衬底160与附加结构的耦合。焊料凸块180可以与衬底160的布线层电连通。
底部填充材料170可以定位在衬底160与桥式互连件140之间。底部填充材料170可以直接与互连材料邻近,或者与互连材料形成直接界面。氧化物层可以被包括在底部填充物170(或模制材料150)与电子设备100的其他组件(诸如互连材料)之间。
图2图示了根据本主题的示例的电子设备100在制造操作期间的示意图。如本文中描述的,电子设备100可以包括第一管芯110、第二管芯120,并且可以包括第三管芯130。第一管芯110、第二管芯120和第三管芯130可以定位在载体200上。第一管芯110、第二管芯120和第三管芯130的有源侧可以耦合到载体200。第一管芯110、第二管芯120和第三管芯130的非有源侧可以耦合到载体200。
载体200可以帮助提供用于实行诸如制造电子设备100之类的制造操作的基础。载体200可以提供平坦的表面。载体200可以包括透明材料,诸如玻璃、聚合物、蓝宝石等等。载体200可以包括多个通孔。多个通孔可以帮助将第一管芯110、第二管芯120和第三管芯130与载体200耦合。在示例中,真空力在载体200的第一侧上生成,并且被施加到定位在载体200的第二侧上的第一管芯110、第二管芯120和第三管芯130。
第一管芯110、第二管芯120和第三管芯130可以诸如利用粘合剂210耦合到载体200(例如,附着到载体200、或与载体200保持在一起)。粘合剂210可以包括透明材料。粘合剂210可以具有在10至20微米的范围内的厚度。粘合剂210可以被适配成响应于热或光(例如,UV或可见光)而释放(例如,第一管芯110与载体200之间的结合力可以减小)。粘合剂210可以定位在第一管芯110、第二管芯120和第三管芯130的有源侧与载体210之间。
第一管芯110可以包括触点220。触点220可以与管芯(例如,第一管芯110)的电路电连通,并且可以允许管芯与包括(但不限于)桥式互连件140的外部设备或结构进行互连。触点220可以包括导电焊盘、导电凸块、导电销、导电柱等等。
第一管芯110可以包括第一组管芯触点230、第二组管芯触点240,并且可以包括第三组管芯触点250。第二管芯120可以包括第四组管芯触点260,并且可以包括第五组管芯触点270。第三管芯110可以包括第六组管芯触点280,并且可以包括第七组管芯触点290。管芯触点(例如,第一组管芯触点230和第五组触点270)可以从管芯(例如,第一管芯110)延伸,并且可以具有相同的高度,或者可以具有变化的高度。
图3图示了桥式互连件140的示意图。如本文中更详细讨论的,桥式互连件140可以帮助便于第一管芯110、第二管芯120和/或第三管芯130之间的电连通。桥式互连件140可以包括半导体管芯。桥式互连件140可以处理在桥式互连件140内传输的电信号。桥式互连件140可以包括有机封装。
桥式互连件140可以包括第一组桥式触点310,并且可以包括第二组桥式触点320。第一组桥式触点310可以包括凸块300。凸块300可以与桥式互连件140的电路电连通,并且凸块300可以从桥式互连件140延伸。
桥式互连件140可以包括桥式通孔350。桥式通孔350可以包括穿硅通孔。桥式通孔350可以帮助通过桥式互连件140传输电信号。桥式通孔350可以将桥式互连件140的第一侧330与桥式互连件140的第二侧340电互连。桥式互连件140可以包括在桥式互连件140的第一侧330或第二侧340上的触点(例如,第一组桥式触点310)。例如,桥式互连件140可以包括在桥式互连件140的第一侧330上的第一焊盘。桥式互连件140可以包括在桥式互连件140的第二侧340上的第二焊盘。凸块300可以耦合到第一焊盘或第二焊盘。桥式通孔330可以与凸块300电连通。
图4图示了根据本主题的示例的电子设备100在制造操作期间的示意图。桥式互连件140可以帮助便于电子设备100内的电连通,诸如第一管芯110与第三管芯130之间的电连通。桥式互连件140可以帮助在电子设备100的第一管芯110、第二管芯120、第三管芯130和/或附加管芯之间建立电连通路径。桥式互连件140可以被定大小并且成形以便与第一管芯110和第二管芯120(或第一管芯110和第三管芯130)的一部分重叠。
桥式互连件140可以直接耦合到第一管芯110、第二管芯120、第三管芯130或附加管芯。对桥式互连件140进行直接耦合可以包括将桥式互连件140与第一管芯110、第二管芯120和/或第三管芯130直接结合。在示例中,桥式互连件140包括半导体管芯,并且桥式互连件140的管芯直接耦合到第一管芯110。桥式互连件140可以利用互连材料400(例如,焊料、导电环氧树脂等等)直接耦合到第一管芯110。
因为桥式互连件140与电子设备100的管芯(例如,第一管芯110)直接耦合,所以桥式互连件140可以帮助减少RC损耗,或者可以帮助减少互连传播延迟。在示例中,桥式互连件140可以帮助减小电信号必须在第一管芯110与第二管芯120之间行进的长度。附加地,与例如通过经由衬底中的布线迹线来传输电信号相比,桥式互连件140可以允许以更大的速率来传输电信号。
因此,通过将桥式互连件140与第一管芯110和第二管芯120直接耦合,可以在第一管芯110与第二管芯110之间传输的电信号可以经历减少的RC损耗量或互连传播延迟。桥式互连件140可以帮助改进电子设备100的性能,并且可以帮助简化用以制造电子设备100的制造过程。
再次参考图4,桥式互连件140的桥式触点(例如,图3的第一组桥式触点310)可以直接耦合到第一管芯110、第二管芯110、第三管芯的管芯触点和/或附加管芯(例如,图2的第一组管芯触点230和第四组管芯触点260)。在示例中,并且如图4所示,第一桥式互连件140A的桥式触点可以(例如,利用诸如焊料之类的互连材料)直接耦合到第一管芯110和第二管芯120的桥式触点。
第二桥式互连件140B可以直接耦合到第一管芯110和第三管芯130。第一桥式互连件140A可以帮助便于第一管芯110和第二管芯120的电连通。第二桥式互连件140B可以帮助便于第一管芯110与第三管芯130之间的电连通。第一桥式互连件140A和第二桥式互连件140B可以帮助便于第二管芯120与第三管芯130之间的电连通。
在另一个示例中,第一桥式互连件140A的桥式触点可以直接耦合到第一管芯110、第二管芯120和第三管芯130的管芯触点。第一桥式互连件140A可以帮助便于第一管芯110、第二管芯120和第三管芯130之间的电连通。在又另一个示例中,第一管芯110、第二管芯120、第三管芯130和第四管芯被定位成彼此靠近(例如,布置在网格中)。桥式互连件140A的桥式触点可以被定位成靠近第一管芯110、第二管芯120、第三管芯130和第四管芯的桥式触点(例如,在管芯的四个拐角处)。桥式互连件140A可以直接耦合到第一管芯110、第二管芯120、第三管芯130和第四管芯;并且可以帮助便于第一管芯110、第二管芯120、第三管芯130和第四管芯中的一个或多个之间的电连通。第一管芯110、第二管芯120、第三管芯130和/或附加管芯的附加布置或配置、以及桥式互连件(例如,第一桥式互连件140A和/或第二桥式互连件140B)是可能的,并且被认为在本主题的范围内。
模制材料150可以耦合到电子设备100(例如,沉积在其上、在其上形成等等)。模制材料150可以耦合到第一管芯110、第二管芯120、第三管芯130、桥式互连件140以及电子设备100的互连。模制材料150可以向电子设备100提供机械强度,并且可以改进电子设备100的互连的弹性。
图5图示了根据本主题的示例的电子设备100在制造操作期间的示意图。第一开口500或第二开口510可以诸如利用激光烧蚀过程而形成在(例如,限定在)模制材料100中。第一开口500可以与第一管芯110的触点220连通。第二开口510可以与第五组管芯触点270连通。
基准标记可以被用来使第一开口500与例如触点220对准。如本文中描述的,载体200可以包括透明材料。载体200可以包括一个或多个基准标记(点、标记、线、几何形状、无定形形状等等),它们被用作确定电子设备100的组件相对于载体200的位置的参考点。例如,载体200的表面可以包括基准线,该基准线可以被用来定位第一管芯110相对于载体200的方位。载体200被定大小并且成形以包括耦合到载体200的表面的多个管芯。第一管芯110、第二管芯120和第三管芯130可以作为第一组管芯耦合到载体200。载体200可以包括基准标记,该基准标记勾勒出第一管芯110、第二管芯120和第三管芯130附近的区域。第二组管芯可以耦合到载体200。例如,第二组管芯可以在与第一组管芯相邻的单位单元中耦合到载体200,并且载体200中包括的基准标记可以被用来标识第一组管芯或第二组管芯相对于载体200的位置。
类似地,第一管芯110、第二管芯120或第三管芯130可以包括一个或多个基准标记。在示例中,第一管芯110可以在第一管芯110的有源侧上包括基准标记。载体200和粘合剂210可以是透明的。可以通过载体200和粘合剂210观察到第一管芯110的有源侧上的基准标记。第一管芯110的有源侧上的基准标记可以被用作针对电子设备100的其他制造过程中的参考点,该其他制造过程包括(但不限于)烧蚀模制材料150以形成第一开口500或第二开口510。
在另一个示例中,可以将载体200的一个或多个基准标记定位在载体200的第一表面上,并且可以通过载体200的第二侧观察到一个或多个基准标记。本文中所描述的一个或多个基准标记可以被用作确定电子设备100的组件的方位的参考点,该组件包括(但不限于)第三管芯110、触点220或第五组管芯触点270。
再次参考图5,导电材料(例如,铜、铝等等)可以耦合到电子设备100,包括(但不限于)模制材料150或触点(例如,触点220)。在示例中,可以诸如利用镀覆操作(例如,电解镀覆等等)将导电材料沉积到电子设备100上。导电材料可以填充第一开口500和第二开口510。导电材料与电子设备100的耦合可以形成覆盖模制材料150的导电材料层。
图6图示了根据本主题的示例的电子设备100在制造操作期间的示意图。如本文中描述的,导电材料可以耦合到电子设备100。导电材料可以填充第一开口500,并且可以形成覆盖模制材料150的导电材料层。如本文中更详细描述的,填充开口500(或开口510)的导电材料可以提供管芯通孔600。
可以诸如利用研磨操作从电子设备100中去除导电材料层(例如,其覆盖模制材料150)。可以同时去除模制材料150和导电材料,并且如图6中所示,管芯通孔600的第一表面610可以与模制材料150的第二表面620共面。
如本文中描述的,导电材料可以与电子设备100的触点(例如,图5的触点220)耦合。管芯通孔600可以耦合到触点。管芯通孔600可以帮助便于电子设备100的电连通。在示例中,管芯通孔600针对第一管芯110提供了通过模制材料150的电连通路径。电子设备100可以包括多个管芯通孔,包括管芯通孔600。
再次参考图6,可以诸如利用研磨操作从电子设备100中去除模制材料150的一部分。可以从电子设备100中去除桥式互连件140的一部分。模制材料150的第二表面620可以与桥式互连件140的第三表面630共面,并且可以帮助减小电子设备100的高度。桥式互连件140的第三表面630可以与管芯通孔600的第一表面610(例如,管芯通孔600的表面)共面,并且可以帮助减小电子设备100的高度。
第一管芯110、第二管芯120和第三管芯130可以作为单元640从模制材料150单粒化。如本文中描述的,一组或多组管芯(例如,参照图5描述的第一组管芯)可以耦合到载体200(图5中所示)。为了从载体200中去除一组或多组管芯,可以去除(例如,利用激光来例如切割或烧蚀)一组或多组管芯附近的模制材料150。例如,可以去除在第一管芯110、第二管芯120和第三管芯130所占据的区域外围附近的模制材料150;并且第一管芯110、第二管芯120和第三管芯130可以作为单元260与载体(例如,图5的载体200)分离。如本文中更详细描述的,单元640可以被用在针对电子设备100的附加制造操作中。
图7图示了根据本主题的示例的电子设备100在制造操作期间的示意图。电子设备100可以包括衬底150。如本文中描述的,衬底160可以包括可以被适配成传输电信号的一个或多个路由层。衬底160可以帮助便于第一管芯110、第二管芯120和/或第三管芯130的电连通。
在示例中,第一管芯110、第二管芯120和第三管芯130可以耦合到衬底150。例如,单元640可以耦合到衬底160。衬底160可以包括衬底触点(例如,焊盘、凸块、柱、销、插座等等),衬底触点可以与衬底160的布线层电连通。可以被包括在电子设备100中的管芯通孔600可以例如利用焊料凸块710耦合到衬底触点。可以从第一管芯110、第二管芯120和/或第三管芯130传输电信号;通过管芯通孔600和焊料凸点710传输电信号;并且电信号可以传播通过衬底160(以及例如传播通过图1的焊料凸块180)。
图8图示了根据本主题的示例的在图7的圆圈8-8处的电子设备100的详细示意图。如本文中描述的,第一管芯110、第二管芯120或第三管芯130可以耦合到衬底160。在一些示例中,桥式互连件140可以耦合到衬底160;并且桥式互连件140可以与衬底160电连通。桥式互连件140可以定位在电子设备的管芯(例如,第一管芯110)与衬底160之间。
桥式互连件140可以耦合到衬底140。例如,桥式互连件140可以包括在桥式互连件140的第一侧330(如图3中所示)上的桥式触点(例如,图3中所示的第一组桥式触点310)。桥式互连件140可以包括在桥式互连件140的第二侧上的桥式触点。例如,桥式互连件140可以包括在桥式互连件140的第二侧上的第三组桥式触点810。第三组桥式触点810可以耦合到衬底160的第一组衬底触点820。桥式触点(例如,第三组桥式触点810)与衬底触点(例如,第一组衬底触点820)的耦合可以帮助便于桥式互连件140与衬底160的电连通。
桥式互连件140可以包括桥式通孔800(或图3中所示的桥式通孔350)。桥式通孔800可以帮助便于电子设备100的管芯(例如,第一管芯110)与衬底160之间的电连通。桥式通孔800可以是穿硅通孔。桥式通孔800可以将桥式互连件的第一侧(例如,图3中所示的第一侧330)与桥式互连件的第二侧(例如,图3中所示的第二侧340)电互连。桥式互连件140与衬底的耦合可以允许电信号从电子设备的管芯(例如,第二管芯120)通过桥式通孔800传输,并且被传输到衬底160(例如,通过经由第一组衬底触点820来传播信号)。
桥式互连件140与衬底160的耦合可以帮助增加电子设备中的电互连的密度。桥式互连件140与衬底160的耦合可以在第一管芯110与衬底110之间提供附加的电连通路径。例如,在桥式互连件140的占用空间内,电信号可以在第一管芯110与衬底160之间传输。增加电子设备100中的电互连的密度可以帮助增加电子设备的性能;或者可以允许减小电子设备100的尺寸。
附加地,单元640(在图6和图7中示出)到衬底160的耦合可以帮助降低制造电子设备100的难度,并且可以帮助减少针对电子设备100的制造操作中的损失。
在示例中,桥式互连件140可以包括具有第一节距的桥式互连件(例如,图3中所示的第一组桥式互连件310)。第一管芯110可以包括具有第一节距的管芯触点(例如,图2中所示的第二组管芯触点240);并且第一管芯110可以包括具有第二节距的管芯触点(例如,图2中所示的第三组管芯触点250)。第一节距可以不同于第二节距。具有第一节距的电子设备100的结构可以在第一操作中被电互连。具有第二节距的电子设备100的结构可以在第二操作中被电互连。将具有第一节距和第二节距的结构的互连分离到第一操作和第二操作中可以简化针对电子设备100的制造操作,并且可以帮助减少与针对电子设备100的制造操作相关联的浪费(例如,产量损失)。
图9图示了根据本主题的示例的电子设备100在制造操作期间的示意图。一个或多个管芯(包括(但不限于)第一管芯110、第二管芯120和第三管芯130)可以(例如,利用粘合剂层210)耦合到载体200。模制材料150的第一层150A可以耦合到第一管芯110、第二管芯120和第三管芯130。电子设备100可以包括管芯触点900(例如,被包括在第三管芯130中),并且管芯触点900可以包括管芯触点表面910。管芯触点表面910可以与模制材料150的第一层150A的模制表面920共面。
图10图示了根据本主题的示例的电子设备100在制造操作期间的示意图。层1000可以耦合到电子设备100。例如,层1000可以耦合到管芯触点表面910和模制表面920。在导电材料和管芯触点表面910的界面处,接缝(seam)(例如,金属晶粒结构中的差异)可以是可检测到的(例如,通过无损评估)。层1000可以包括耦合到电子设备100的导电材料种子层(例如,铜)。层1000可以包括层压材料。该层压材料可以包括(但不限于)干膜抗蚀剂。该层压材料可以被用在制造操作(例如,光刻法等等)中,并且可以是光敏的。当暴露于光(例如,UV光)时,层1000可以硬化(或软化)。
图11图示了根据本主题的示例的电子设备在制造操作期间的示意图。如本文中描述的,层1000可以是光敏的。开口1100可以在层1000中形成。开口1100可以与管芯触点表面910连通。
在示例中,可以在层1000上施加掩模,并且该掩模可以防止层1000的部分暴露于光。例如,掩模可以阻挡层1000吸收管芯触点表面910上方的区域中的光。吸收光的层1000的未被掩盖部分可以硬化。可以(例如,利用溶剂)去除层1000的被掩盖部分,并且保留层1000的未被掩盖(或硬化)部分。开口1100可以被限定在层1000中。例如,可以在从电子设备100去除层1000的未被掩盖部分期间形成开口1100。
导电材料可以耦合到电子设备100,并且导电材料可以填充开口1100。填充开口1100的导电材料可以创建导电柱(例如,图12中所示的导电柱1200),并且导电柱可以从管芯(例如,第一管芯110)的表面延伸。导电材料可以耦合到管芯触点表面910。可以从电子设备100中去除(例如,溶解)层1000,并且导电材料可以基本上不受去除操作影响。导电柱可以包括在去除层1000之后耦合到管芯触点表面910的导电材料。
在示例中,铜被电镀到开口1100中,并且与管芯触点表面910耦合。铜可以与层1000的顶表面共面。可以(例如,利用溶剂)去除层1000,并且填充开口1100的铜将保持耦合到管芯触点表面910。
图12图示了根据本主题的示例的电子设备100在制造操作期间的示意图。电子设备100可以包括导电柱1200。电子设备可以包括多个导电柱,该多个导电柱包括导电柱1200。导电柱1200可以包括如下导电材料(例如,铜),该导电材料可以耦合到管芯(例如,第二管芯120)的管芯触点表面(例如,图11的管芯触点表面910)。导电柱1200可以帮助便于管芯与外部结构的电连通。例如,导电柱1200可以耦合到衬底(例如,图1中所示的衬底160),并且导电柱1200可以帮助便于管芯(例如,第一管芯110)与衬底的电连通。
如本文中所讨论的,电子设备100可以包括桥式互连件140。桥式互连件140可以耦合到管芯触点(例如,第一电子设备100(例如,图2中所示的第一组管芯触点230和第四组管芯触点260)),并且桥式互连件可以便于电子设备100的电连通,包括(但不限于)第一管芯110与第二管芯120之间的电连通。在一些示例中,在已经从电子设备100中去除层1000(图10-11中所示)之后,桥式互连件140可以耦合到电子设备100。桥式互连件140可以与导电柱1200的一部分共面。导电柱1200可以具有第一长度,并且可以从管芯(例如,第一管芯110)延伸。导电柱1200可以延伸到桥式互连件140之外,该桥式互连件140耦合到电子设备100。
图13图示了根据本主题的示例的电子设备100在制造操作期间的示意图。如本文中描述的,电子设备100可以包括模制材料150。模制材料150可以帮助向电子设备100提供机械强度。模制材料150可以耦合到第一管芯110、第二管芯120、第三管芯130、桥式互连件140,并且可以耦合到导电柱1200。
如本文中描述的,电子设备100可以包括模制材料150的第一层150A。电子设备100可以包括模制材料150的第二层150B。第一层150A可以在第一操作中耦合到电子设备100,并且第二层150B可以在第二操作中耦合到电子设备100。在第一层150A和第二层150B的界面处,接缝(例如,分子结构中的不连续性)可以是可检测到的(例如,通过对电子设备100的剖切或无损评估)。
在示例中,电子设备包括多个导电柱,并且模制材料150可以定位在多个导电柱之间。模制材料150可以定位在导电柱1200与桥式互连件140之间。模制材料可以定位在桥式互连件140与管芯(例如,第一管芯110、第二管芯120或第三管芯130)之间。模制材料150可以定位在管芯触点(例如,图2中所示的第一组管芯触点230)与桥式触点(例如,第一组桥式触点310)之间。
可以去除模制材料的一部分(例如,在研磨操作中),并且可以去除导电柱1200的一部分。电子设备100可以作为一单元(例如,图6-7的单元640)从载体200中去除,并且可以在其他制造操作中被使用。可以从电子设备100的外围去除模制材料150的部分。
图14图示了根据本主题的示例的电子设备100在制造操作期间的示意图。如本文中描述的,电子设备100可以包括第一管芯110、第二管芯120和第三管芯130,第三管芯130可以包括管芯触点220。模制材料150可以耦合到第一管芯110、第二管芯120和第三管芯130。管芯触点220的管芯触点表面910可以与模制材料150的模制表面920共面。桥式互连件140可以耦合到电子设备100(例如,耦合到第一管芯110和第二管芯120)。
电子设备100可以与作为单元640的载体(例如,图9的载体200)分离。单元640可以包括一个或多个管芯(例如,第二管芯120和第三管芯130)。可以从单元640中去除(例如,切割、烧蚀等等)模制材料150的多余部分1400。模制表面920可以与管芯(例如,第三管芯130)的第一表面1410(例如,有源侧)共面。模制表面920可以与管芯的第二表面1420共面。管芯的第一侧1410可以垂直于管芯的第二侧。
图15图示了根据本主题的示例的电子设备100在制造操作期间的示意图。衬底160可以包括导电柱1510,并且导电柱1510可以从衬底160的表面延伸(例如,延伸第一高度)。单元640可以耦合到衬底160。例如,焊料球1520可以定位在管芯触点220与导电柱1510之间。桥式互连件140可以与导电柱1510的一部分共面。桥式互连件140可以定位在衬底160与管芯(例如,第一管芯110)之间。在示例中,电子设备100包括第一桥式互连件(例如,桥式互连件140)和第二桥式互连件;并且第一桥式互连件可以与第二桥式互连件共面。
如本文中描述的,电子设备100可以包括底部填充材料170。底部填充材料170可以填充单元640与衬底160之间的空间。在一些示例中,底部填充材料170具有比模制材料150更低的粘度。底部填充材料170可以被适配成流入模制材料150无法流入的空间(例如,在单元640与衬底160之间)中。底部填充材料170可以耦合到单元640,并且可以耦合到衬底160。底部填充材料170可以定位在模制材料150与桥式互连件140之间。底部填充材料170可以定位在桥式互连件140的桥式触点(例如,图3的第一组桥式触点310)之间。底部填充材料170可以定位在桥式互连件140与导电柱1510之间。在示例中,桥式互连件140可以被定位成靠近导电柱1510,并且底部填充材料170可以填充桥式互连件140与导电柱1510之间的空间。底部填充材料170可以耦合到第一管芯110、第二管芯120或第三管芯130。
图16图示了根据本主题的示例的电子设备100在制造操作期间的示意图。电子设备100可以包括散热片,该散热片包括(但不限于)集成散热器1600。集成散热器1600可以被定位成靠近单元640。界面材料1610(例如,热界面材料等等)可以定位在单元640与集成散热器1600之间,并且可以改进从管芯(例如,第一管芯110)到集成散热器1600的热传递。界面材料1610可以定位在管芯(例如,第三管芯110)的第一侧1410(在图15中所示)与集成散热器1600之间。
图17图示了系统级示图,其描绘了包括如本公开中所描述的电子设备100的电子设备(例如,系统)的示例。图17被包括以便示出用于电子设备100的更高级别设备应用的示例。在一个实施例中,系统1700包括但不限于台式计算机、膝上型计算机、上网本、平板设备、笔记本计算机、个人数字助理(PDA)、服务器、工作站、蜂窝电话、移动计算设备、智能电话、互联网电器或任何其他类型的计算设备。在一些实施例中,系统1700是片上系统(SOC)型系统。
在一个实施例中,处理器1710具有一个或多个处理器核心1712和1712N,其中1712N表示处理器1710内部的第N个处理器核心,其中N是正整数。在一个实施例中,系统1700包括多个处理器,包括1710和1705,其中处理器1705具有与处理器1710的逻辑类似或相同的逻辑。在一些实施例中,处理核心1712包括但不限于:用以对指令进行取指的预取指逻辑、用以解码指令的解码逻辑、用以执行指令的执行逻辑等等。在一些实施例中,处理器1710具有高速缓冲存储器1716,用以对系统1700的指令和/或数据进行高速缓存。可以将高速缓冲存储器1716组织到包括一级或多级高速缓冲存储器的分层结构中。
在一些实施例中,处理器1710包括存储器控制器1714,该存储器控制器1714可操作于实行使得处理器1710能够访问存储器1730并且与之通信的功能,存储器1730包括易失性存储器1732和/或非易失性存储器1734。在一些实施例中,处理器1710与存储器1730和芯片组1720耦合。处理器1710还可以耦合到无线天线1778,以便与被配置成传输和/或接收无线信号的任何设备进行通信。在一个实施例中,用于无线天线1778的接口根据但不限于IEEE 802.11标准及其相关族、家用插头AV(HPAV)、超宽带(UWB)、蓝牙、WiMax或任何形式的无线通信协议进行操作。
在一些实施例中,易失性存储器1732包括但不限于同步动态随机存取存储器(SDRAM)、动态随机存取存储器(DRAM)、RAMBUS动态随机存取存储器(RDRAM)和/或任何其他类型的随机存取存储器设备。非易失性存储器1734包括但不限于闪速存储器、相变存储器(PCM)、只读存储器(ROM)、电可擦除可编程只读存储器(EEPROM)或任何其他类型的非易失性存储器设备。
存储器1730存储将由处理器1710执行的信息和指令。在一个实施例中,存储器1730还可以在处理器1710正在执行指令的同时存储临时变量或其他中间信息。在图示的实施例中,芯片组1720经由点对点(PtP或P-P)接口1717和1722与处理器1710连接。芯片组1720使得处理器1710能够连接到系统1700中的其他元件。在示例系统的一些实施例中,接口1717和1722根据诸如Intel®快速路径互连(QPI)等等的PtP通信协议进行操作。在其他实施例中,可以使用不同的互连件。
在一些实施例中,芯片组1720可操作于与处理器1710、1705N、显示设备1740和其他设备进行通信,该其他设备包括总线桥1772、智能TV 1776、I/O设备1774、非易失性存储器1760、存储介质(诸如一个或多个大容量存储设备)1762、键盘/鼠标1764、网络接口1766、以及各种形式的消费者电子产品1777(诸如PDA、智能电话、平板设备等)等。在一个实施例中,芯片组1720通过接口1724与这些设备耦合。芯片组1720还可以耦合到无线天线1778,以便与被配置成传输和/或接收无线信号的任何设备进行通信。
芯片组1720经由接口1726连接到显示设备1740。显示器1740可以是例如液晶显示器(LCD)、等离子体显示器、阴极射线管(CRT)显示器或任何其他形式的视觉显示设备。在示例系统的一些实施例中,处理器1710和芯片组1720被合并到单个SOC中。此外,芯片组1720连接到一个或多个总线1750和1755,这些总线对各种系统元件进行互连,该各种系统元件诸如是I/O设备1774、非易失性存储器1760、存储介质1762、键盘/鼠标1764和网络接口1766。总线1750和1755可以经由总线桥1772互连在一起。
在一个实施例中,大容量存储设备1762包括但不限于固态驱动器、硬盘驱动器、通用串行总线闪速存储器驱动器、或任何其他形式的计算机数据存储介质。在一个实施例中,由任何类型的公知网络接口标准来实现网络接口1766,该公知网络接口标准包括但不限于以太网接口、通用串行总线(USB)接口、外围部件互连(PCI)快速接口、无线接口和/或任何其他适合类型的接口。在一个实施例中,无线接口根据但不限于IEEE 802.11标准及其相关族、家用插头AV(HPAV)、超宽带(UWB)、蓝牙、WiMax或任何形式的无线通信协议进行操作。
虽然将图17中所示的模块描绘为系统1700内的单独的块,但是由这些块中的一些实行的功能可以被集成在单个半导体电路内,或者可以使用两个或更多个单独的集成电路来实现。例如,尽管将高速缓冲存储器1716描绘为处理器1710内的单独的块,但是可以将高速缓冲存储器1716(或1716的所选方面)结合到处理器核心1712中。
图18示出了用于制造电子设备的方法1800的一个示例,该电子设备包括本文中所描述的电子设备100中的一个或多个。在描述方法1800时,参考本文中先前所描述的一个或多个组件、特征、功能和操作。在方便的情况下,用附图标记来对组件、特征、操作等等进行参考。所提供的附图标记是示例性的,而不是排他性的。例如,方法1800中所描述的组件、特征、功能、操作等等包括但不限于:本文中所提供的对应的经编号的要素和本文中所描述的其他对应要素(经编号和未经编号两者)以及它们的等同物。
在1802处,方法1800可以包括:将第一管芯110定位在载体200的表面上。第一管芯110可以包括第一组管芯触点(例如,图2中所示的第一组管芯触点230)。
在1804处,方法1800可以包括:将第二管芯120定位在载体的表面上。第二管芯120可以被定位在载体1200上的第一管芯110附近。第二管芯120可以包括第二组管芯触点(例如,图2中所示的第四组管芯触点260)。
在1806处,方法1800可以包括:将第一桥式互连件140A定位成靠近第一管芯110和第二管芯120。第一桥式互连件140A可以包括第一组桥式触点310,并且可以包括第二组桥式触点320。
在1808处,方法1800可以包括:将第一组桥式触点310与第一管芯110的第一组管芯触点耦合。在1810处,方法1800可以包括:将第二组桥式触点320与第二管芯120的第二组管芯触点耦合。方法1800可以包括:将导电环氧树脂施加到桥式触点或管芯触点,例如以将管芯(例如,第一管芯110)与桥式互连件140直接耦合。
方法1800可以包括:将第三管芯130定位成靠近第一管芯120。第三管芯130可以包括第三组管芯触点(例如,图2中所示的第六组管芯触点280)。第一管芯110可以包括第四组管芯触点(例如,图2中所示的第二组管芯触点240)。
第三管芯130可以定位在第一管芯110的第一侧上,并且第二管芯120可以定位在第一管芯110的第二侧上。第一管芯110的第一侧可以与第一管芯110的第二侧相对。第四管芯可以定位在第一管芯110的第三侧上。附加管芯(例如,第五管芯)可以定位成靠近第一管芯110。
方法1800可以包括:将第二桥式互连件140B定位成靠近第一管芯110和第三管芯130。第二桥式互连件140B可以包括第三组桥式触点和第四组桥式触点。方法1800可以包括:将第三组桥式触点与第三组管芯触点耦合。方法1800可以包括:将第四组桥式触点与第四组管芯触点耦合。第一管芯110和第三管芯130可以通过第二桥式互连件140B电连通。
桥式互连件140可以便于两个或更多个管芯之间的电连通。方法1800可以包括:将第三管芯130定位成靠近第二管芯120。在示例中,第一桥式互连件140A可以耦合到第一管芯110和第二管芯120。第二桥式互连件140B可以耦合到第二管芯120和第三管芯130。第三管芯130可以与第一管芯110通信,包括(但不限于):第三管芯130通过经由第一桥式互连件140和第二桥式互连件140来传输电信号从而与第一管芯110进行通信。
方法1800可以包括:将第三组桥式触点与(例如,第三管芯130的)第三组管芯触点直接耦合。桥式互连件140可以便于第一管芯110、第二管芯120和第三管芯130之间的电连通。
方法1800可以包括:将模制材料150与第一管芯110、第二管芯120或桥式互连件140耦合。方法1800可以包括:(例如,利用消融操作)形成第一开口(例如,图5中所示的第一开口500),并且第一开口可以被限定在模制材料150中。在示例中,载体200(图2中所示)可以包括透明材料。检测器(例如,相机等等)可以从载体200的第一侧(例如,底侧)检查基准标记。去除装置(例如,激光器)可以被定位成靠近模制材料150(或电子设备100)。该去除装置可以定位在载体200的第二侧(例如,顶侧)上。在定位去除装置时,可以参考基准标记,可以从载体200的第一侧观察到该基准标记。可以参考该基准标记,例如以使去除装置与管芯(例如,第一管芯110)的触点(例如,图2的触点220)对准。去除装置可以通过去除模制材料150来形成开口,并且开口可以与电子设备100的特征(例如,触点)对准。电子设备100可以包括第二开口,并且第二开口可以使第二管芯触点暴露。
方法1800可以包括:通过将导电材料(例如,铜等等)与第一开口以及例如管芯的触点进行耦合,从而在第一开口中形成通孔(例如,图6中所示的第一通孔600)。方法1800可以包括:去除通孔和模制材料150的一部分(例如,通过在研磨操作中去除材料)。可以从电子设备100中去除(例如,磨光)桥式互连件的一部分。可以以相同的操作(例如,同时研磨模制材料150、通孔和桥式互连件140)来实行模制材料150、通孔和桥式互连件140的部分的去除。
方法1800可以包括:将第一管芯110和第二管芯120与衬底160耦合。衬底150可以帮助便于第一管芯110和第二管芯120与外部结构(例如,片上系统的母板或组件)的连通。
方法1800可以包括:将桥式互连件通孔(例如,图3中所示的桥式通孔330)与衬底160耦合。桥式通孔可以被包括在桥式互连件140中。桥式通孔可以帮助在第一管芯110与衬底160之间建立电连通路径。方法1800可以包括:将底部填充材料定位在桥式互连件140与衬底160之间。
各种注释和示例
方面1可以包括或使用一种主题(诸如用于实行动作的装置、系统、设备、方法、部件,或者设备可读介质,其包括指令,所述指令在由所述设备实行时可以使所述设备实行动作,或者制品),诸如可以包括或使用电子设备。
电子设备可以包括第一管芯。该第一管芯可以包括第一组管芯触点。该电子设备可以包括第二管芯。该第二管芯可以包括第二组管芯触点。该电子设备可以包括桥式互连件。该桥式互连件可以包括第一组桥式触点,并且可以包括第二组桥式触点。
第一组桥式触点可以例如利用焊料直接耦合到第一组管芯触点。第二组桥式触点可以例如利用焊料直接耦合到第二组管芯触点。桥式互连件可以便于第一管芯与第二管芯之间的电连通。
方面2可以包括或使用方面1的主题,或者可以可选地与方面1的主题组合,以可选地包括或使用:桥式互连件可以包括第三管芯。该第三管芯可以被定大小并且成形以便与第一管芯的一部分重叠,并且与第二管芯的一部分重叠。
方面3可以包括或使用方面1或2之一或其任何组合的主题,或者可以可选地与方面1或2之一或其任何组合的主题组合,以可选地包括或使用:第一管芯和第二管芯可以仅通过桥式互连件电连通。
方面4可以包括或使用方面1至3之一或其任何组合的主题,或者可以可选地与方面1至3之一或其任何组合的主题组合,以可选地包括或使用衬底。第一管芯和第二管芯可以耦合到衬底。
方面5可以包括或使用方面4的主题,或者可以可选地与方面4的主题组合,以可选地包括或使用:桥式互连件可以定位在第一管芯与衬底之间。
方面6可以包括或使用方面5的主题,或者可以可选地与方面5的主题组合,以可选地包括或使用底部填充材料,该底部填充材料可以定位在桥式互连件与衬底之间。
方面7可以包括或使用方面4的主题,或者可以可选地与方面4的主题组合,以可选地包括或使用第一桥式触点。该第一桥式触点可以定位在桥式互连件的第一表面上。该第一桥式触点可以例如利用焊料直接耦合到第一管芯的管芯触点。电子设备100可以包括第二桥式触点。该第二桥式触点可以定位在桥式互连件的第二表面上。该第二桥式触点可以例如利用焊料直接耦合到衬底的衬底触点。
电子设备可以包括桥式通孔。该桥式通孔可以被包括在桥式互连件中。该桥式通孔可以将第一桥式触点与第二桥式触点电互连。该桥式通孔可以便于第一管芯与衬底之间的电连通。
方面8可以包括或使用方面7的主题,或者可以可选地与方面7的主题组合,以可选地包括或使用底部填充材料。该底部填充材料可以与焊料形成直接界面,该焊料可以将第二桥式触点与衬底触点直接耦合。
方面9可以包括或使用方面1至8之一或其任何组合的主题,或者可以可选地与方面1至8之一或其任何组合的主题组合,以可选地包括或使用:第一管芯和第二管芯可以是共面的。
方面10可以包括或使用方面1至9之一或其任何组合的主题,或者可以可选地与方面1至9之一或其任何组合的主题组合,以可选地包括或使用模制材料。该模制材料可以与第一管芯、第二管芯和桥式互连件形成直接界面。
方面11可以包括或使用方面10的主题,或者可以可选地与方面10的主题组合,以可选地包括或使用管芯通孔。该管芯通孔可以与第一管芯耦合。该管芯通孔可以延伸穿过模制材料。
方面12可以包括或使用方面11的主题,或者可以可选地与方面11的主题组合,以可选地包括或使用:桥式互连件可以与管芯通孔的一部分共面。
方面13可以包括或使用方面11或12之一或其任何组合的主题,或者可以可选地与方面11或12之一或其任何组合的主题组合,以可选地包括或使用:桥式互连件的表面可以与模制材料的表面共面。
方面14可以包括或使用方面1至13之一或其任何组合的主题,或者可以可选地与方面1至13之一或其任何组合的主题组合,以可选地包括或使用第三组管芯触点。该第三组管芯触点可以被包括在第一管芯中。电子设备可以包括管芯通孔。该管芯通孔可以与第三组管芯触点耦合。该第一组管芯触点可以具有小于第三组管芯触点的尺寸。
方面15可以包括或使用一种主题(诸如用于实行动作的装置、系统、设备、方法、部件,或者设备可读介质,其包括指令,所述指令在由所述设备实行时可以使所述设备实行动作,或者制品),诸如可以包括或使用电子设备。
该电子设备可以包括衬底。该电子设备可以包括第一管芯。该第一管芯可以耦合到衬底。该第一管芯可以包括第一组管芯触点。该电子设备可以包括第二管芯。该第二管芯可以耦合到衬底。该第二管芯可以包括第二组管芯触点。
该电子设备可以包括第一桥式互连件。该第一桥式互连件可以与衬底间隔开。该第一桥式互连件可以包括第一组桥式触点。该第一桥式互连件可以包括第二组桥式触点。该第一组桥式触点可以例如利用互连材料直接耦合到第一组管芯触点。该第二组桥式触点可以例如利用互连材料直接耦合到第二组管芯触点。该第一桥式互连件可以便于第一管芯与第二管芯之间的电连通。
方面16可以包括或使用方面15的主题,或者可以可选地与方面15的主题组合,以可选地包括或使用:第一桥式互连件可以是第三管芯。
方面17可以包括或使用方面15或16之一或其任何组合的主题,或者可以可选地与方面15或16之一或其任何组合的主题组合,以可选地包括或使用:第一管芯和第二管芯可以仅通过第一桥式互连件电连通。
方面18可以包括或使用方面15至17之一或其任何组合的主题,或者可以可选地与方面15至17之一或其任何组合的主题组合,以可选地包括或使用第三管芯。该第三管芯可以耦合到衬底。该第三管芯可以包括第三组管芯触点。该电子设备可以包括第四组管芯触点。该第四组管芯触点可以被包括在第二管芯中。
该电子设备可以包括第二桥式互连件。该第二桥式互连件可以与衬底间隔开。该第二桥式互连件可以包括第三组桥式触点,并且可以包括第四组桥式触点。该第三组桥式触点可以例如利用互连材料直接耦合到第三组管芯触点。该第四组桥式触点可以例如利用互连材料直接耦合到第四组管芯触点。第二桥式互连件可以便于第二管芯与第三管芯之间的电连通。
方面19可以包括或使用方面18的主题,或者可以可选地与方面18的主题组合,以可选地包括或使用:第一桥式互连件可以与第二桥式互连件共面。
方面20可以包括或使用方面15至19之一或其任何组合的主题,或者可以可选地与方面15至17之一或其任何组合的主题组合,以可选地包括或使用第三管芯。第三管芯可以耦合到衬底。第三管芯可以包括第三组管芯触点。该电子设备可以包括第三组桥式触点。该第三组桥式触点可以被包括在第一桥式互连件中。该第三组桥式触点可以例如利用互连材料直接耦合到第三组管芯触点。该第一桥式互连件可以便于第一管芯、第二管芯和第三管芯之间的电连通。
方面21可以包括或使用一种主题(诸如用于实行动作的装置、系统、设备、方法、部件,或者一种设备可读介质,其包括指令,所述指令在由所述设备实行时可以使所述设备实行动作,或者制品),诸如可以包括或使用用于制造电子设备的方法。该方法可以包括:将第一管芯定位在载体的表面上。第一管芯可以包括第一组管芯触点。
该方法可以包括:将第二管芯定位在载体的表面上。该第二管芯可以被定位成靠近(例如,邻近等等)载体上的第一管芯。该第二管芯可以包括第二组管芯触点。该方法可以包括:将第一桥式互连件定位成靠近第一管芯和第二管芯。该第一桥式互连件可以包括第一组桥式触点和第二组桥式触点。
该方法可以包括:将第一组桥式触点与第一管芯的第一组管芯触点直接耦合。该方法可以包括:将第二组桥式触点与第二管芯的第二组管芯触点直接耦合。
方面22可以包括或使用方面21的主题,或者可以可选地与方面21的主题组合,以可选地包括或使用:将第三管芯定位成靠近第一管芯。该第三管芯可以包括第三组管芯触点。该第一管芯可以包括第四组管芯触点。该方法可以包括:将第二桥式互连件定位成靠近第一管芯和第三管芯。该第二桥式互连件可以包括第三组桥式触点,并且可以包括第四组桥式触点。该方法可以包括:将第三组桥式触点与第三组管芯触点耦合。该方法可以包括:将第四组桥式触点与第四组管芯触点直接耦合。
方面23可以包括或使用方面21或22之一或其任何组合的主题,或者可以可选地与方面21或22之一或其任何组合的主题组合,以可选地包括或使用:将模制材料与第一管芯、第二管芯和第一桥式互连件进行耦合。
方面24可以包括或使用方面23的主题,或者可以可选地与方面23的主题组合,以可选地包括或使用:形成第一开口。该第一开口可以被限定在模制材料中。该第一开口可以使第一管芯的第一管芯触点暴露。
方面25可以包括或使用方面24的主题,或者可以可选地与方面24的主题组合,以可选地包括或使用:载体可以包括透明材料。第一开口的形成可以包括:从透明载体的第一侧检查基准标记。第一开口的形成可以包括:将靠近模制材料的去除装置定位在透明载体的第二侧上。定位去除装置可以包括:参考在透明载体的第一侧上检查的基准标记。第一开口的形成可以包括:去除模制材料的一部分并且形成第一开口。
方面26可以包括或使用方面23至25之一或其任何组合的主题,或者可以可选地与方面23至25之一或其任何组合的主题组合,以可选地包括或使用:形成第二开口。该第二开口可以被限定在模制材料中。该第二开口可以使第二管芯的第二管芯触点暴露。
方面27可以包括或使用方面23至26之一或其任何组合的主题,或者可以可选地与方面23至26之一或其任何组合的主题组合,以可选地包括或使用:形成通孔。可以例如通过将导电材料与第一开口和第一管芯的第一触点进行耦合而在第一开口中形成通孔。
方面28可以包括或使用方面23至27之一或其任何组合的主题,或者可以可选地与方面23至27之一或其任何组合的主题组合,以可选地包括或使用:去除通孔和模制材料的一部分。
方面29可以包括或使用方面28的主题,或者可以可选地与方面28的主题组合,以可选地包括或使用:去除桥式互连件的一部分。
方面30可以包括或使用方面21至29之一或其任何组合的主题,或者可以可选地与方面21至29之一或其任何组合的主题组合,以可选地包括或使用:将第一组桥式触点与第一组管芯触点进行耦合可以包括将导电环氧树脂施加到第一组桥式触点或第一组管芯触点。
方面31可以包括或使用方面21至30之一或其任何组合的主题,或者可以可选地与方面21至30之一或任何组合的主题组合,以可选地包括或使用:将第一管芯和第二管芯与衬底进行耦合。
方面32可以包括或使用方面31的主题,或者可以可选地与方面31的主题组合,以可选地包括或使用:将桥式通孔与衬底进行耦合。该桥式通孔可以被包括在桥式互连件中。该桥式通孔可以在第一管芯与衬底之间建立电连通路径。
方面33可以包括或使用方面31或32之一或其任何组合的主题,或者可以可选地与方面31或32之一或其任何组合的主题组合,以可选地包括或使用:将底部填充材料定位在桥式互连件与衬底之间。
方面34可以包括或使用方面1至33中的任何一个或多个的任何部分或其任何部分的组合,或者可以可选地与方面1至33中的任何一个或多个的任何部分或其任何部分的组合进行组合,以包括或使用如下主题:该主题可以包括用于实行方面1至33中的任何一个或多个功能的部件、或者包括指令的机器可读介质,所述指令在由机器实行时使所述机器实行方面1至33的任何一个或多个功能。
这些非限制性示例中的每一个可以独立存在,或者可以与一个或多个其他示例以各种排列或组合的形式进行组合。
上面的描述包括对形成该详细描述的一部分的附图的参考。附图通过说明的方式示出了其中可以实践本发明的特定实施例。这些实施例在本文中也被称为“示例”。这样的示例可以包括除了所示出或描述的那些元件之外的元件。然而,本发明人还设想到其中仅提供所示出或描述的那些元件的示例。此外,本发明人还设想到使用所示出或描述的那些元件(或其一个或多个方面)关于特定示例(或其一个或多个方面)或关于本文中示出或描述的其他示例(或其一个或多个方面)的任何组合或排列的示例。
在本文档与通过引用方式这样并入的任何文档之间有不一致的使用的情况下,以本文档中的使用为准。
在本文档中,如专利文件中常见的那样使用术语“一”或“一个”,以包括一个或多于一个,其独立于“至少一个”或“一个或多个”的任何其他实例或使用。在本文档中,术语“或”被用来指代非排他性的“或”,使得“A或B”包括“A但不是B”、“B但不是A”、以及“A和B”,除非另有指示。在本文档中,术语“包括”和“在其中”被用作相应术语“包含”和“其中”的简单英语等同表示。而且,在以下权利要求中,术语“包括”和“包含”是开放式的,即,包括除了在权利要求中的这种术语之后列出的那些元件之外的元件的系统、设备、物品、组成、配方(formulation)或过程仍然被视为落入该权利要求的范围内。此外,在所附权利要求中,术语“第一”、“第二”和“第三”等仅被用作标签,并且不意图对它们的对象强加数值要求。
除非上下文另行指出,否则诸如“平行”、“垂直”、“圆形”或“正方形”之类的几何术语并不意图要求绝对的数学精度。代替地,这样的几何术语允许由于制造或等同功能而引起的变化。例如,如果元件被描述为“圆形”或“大体上圆形的”,则该描述仍涵盖了不是精确圆形的组件(例如,稍微椭圆形或多面多边形的组件)。
本文中描述的方法示例可以是至少部分地机器或计算机实现的。一些示例可以包括利用指令编码的计算机可读介质或机器可读介质,所述指令可操作于配置电子设备以实行如以上示例中所描述的方法。这种方法的实现方式可以包括代码,诸如微代码、汇编语言代码、高级语言代码等等。这样的代码可以包括用于实行各种方法的计算机可读指令。该代码可以形成计算机程序产品的部分。另外,在示例中,代码可以有形地存储在一个或多个易失性、非暂时性或非易失性有形计算机可读介质上,诸如在执行期间或在其他时候存储。这些有形的计算机可读介质的示例可以包括但不限于:硬盘、可移动磁盘、可移动光盘(例如,紧凑盘和数字视频盘)、盒式磁带、存储器卡或棒、随机存取存储器(RAM)、只读存储器(ROM)等等。
以上描述意图是说明性的,而不是限制性的。例如,可以以彼此组合的方式使用上述示例(或其一个或多个方面)。可以诸如通过本领域普通技术人员在回顾以上描述之后使用其他实施例。提供摘要以符合37 C.F.R.§1.72(b),从而允许读者快速查明该技术公开内容的实质。所提出的理解是,它将不被用来解释或限制权利要求的范围或含义。而且,在以上详细描述中,各种特征可以被分组在一起以简化本公开。这不应当被解释为意图未要求保护的所公开特征对于任何权利要求都是必不可少的。而是,发明主题可以在比特定的公开实施例的所有特征更少的情况下存在。因此,将所附权利要求由此并入具体实施方式中作为示例或实施例,其中每个权利要求独立地作为单独的实施例,以及所预料到的是,可以按照各种组合或排列将这样的实施例彼此组合。本发明的范围应当参考所附权利要求以及这种权利要求所授予权利的等同方式的完整范围来确定。

Claims (20)

1.一种电子设备,包括:
第一管芯,其包括第一组管芯触点;
第二管芯,其包括第二组管芯触点;
桥式互连件,其包括第一组桥式触点和第二组桥式触点;以及
其中,第一组桥式触点利用焊料直接耦合到第一组管芯触点,第二组桥式触点利用焊料直接耦合到第二组管芯触点,并且桥式互连件便于第一管芯与第一管芯之间的电连通。
2.根据权利要求1所述的电子设备,其中,桥式互连件是第三管芯,并且第三管芯被定大小并且成形以便与第一管芯的一部分重叠并且与第二管芯的一部分重叠。
3.根据权利要求1所述的电子设备,其中,第一管芯和第二管芯仅通过桥式互连件而电连通。
4.根据权利要求1所述的电子设备,进一步包括:衬底,其中,第一管芯和第二管芯耦合到衬底。
5.根据权利要求4所述的电子设备,其中,桥式互连件定位在第一管芯与衬底之间。
6.根据权利要求5所述的电子设备,进一步包括:定位在桥式互连件与衬底之间的底部填充材料。
7.根据权利要求4所述的电子设备,进一步包括:
第一桥式触点,其定位在桥式互连件的第一表面上,其中,第一桥式触点利用焊料直接耦合到第一管芯的管芯触点;
第二桥式触点,其定位在桥式互连件的第二表面上,其中,第二桥式触点利用焊料直接耦合到衬底的衬底触点;
桥式通孔,其被包括在桥式互连件中,其中,桥式通孔将第一桥式触点与第二桥式触点电互连;以及
其中,桥式通孔便于第一管芯与衬底之间的电连通。
8.根据权利要求7所述的电子设备,进一步包括:底部填充材料,其与焊料形成直接界面,所述焊料将第二桥式触点与衬底触点直接耦合。
9.根据权利要求1所述的电子设备,其中,第一管芯和第二管芯是共面的。
10.根据权利要求1所述的电子设备,进一步包括:模制材料,其中,模制材料与第一管芯、第二管芯和桥式互连件形成直接界面。
11.根据权利要求10所述的电子设备,进一步包括:管芯通孔,其中,管芯通孔与第一管芯耦合,并且管芯通孔延伸穿过模制材料。
12.根据权利要求11所述的电子设备,其中,桥式互连件与管芯通孔的一部分共面。
13.根据权利要求11所述的电子设备,其中,桥式互连件的表面与模制材料的表面共面。
14.根据权利要求1所述的电子设备,进一步包括:
第三组管芯触点,其被包括在第一管芯中;
管芯通孔,其与第三组管芯触点耦合;以及
其中,第一组管芯触点具有小于第三组管芯触点的尺寸。
15.一种电子设备,包括:
衬底;
第一管芯,其耦合到衬底,第一管芯包括第一组管芯触点;
第二管芯,其耦合到衬底,第二管芯包括第二组管芯触点;
第一桥式互连件,其与衬底间隔开,第一桥式互连件包括第一组桥式触点和第二组桥式触点;以及
其中,第一组桥式触点利用互连材料直接耦合到第一组管芯触点,第二组桥式触点利用互连材料直接耦合到第二组管芯触点,并且第一桥式互连件便于第一管芯与第一管芯之间的电连通。
16.根据权利要求15所述的电子设备,其中,第一桥式互连件是第三管芯。
17.根据权利要求15所述的电子设备,其中,第一管芯和第二管芯仅通过第一桥式互连件而电连通。
18.根据权利要求15所述的电子设备,进一步包括:
第三管芯,其耦合到衬底,第三管芯包括第三组管芯触点;
第四组管芯触点,其被包括在第二管芯中;
第二桥式互连件,其与衬底间隔开,第二桥式互连件包括第三组桥式触点和第四组桥式触点;以及
其中,第三组桥式触点利用互连材料直接耦合到第三组管芯触点,第四组桥式触点利用互连材料直接耦合到第四组管芯触点,并且第二桥式互连件便于第二管芯与第三管芯之间的电连通。
19.根据权利要求18所述的电子设备,其中,第一桥式互连件与第二桥式互连件共面。
20.根据权利要求15所述的电子设备,进一步包括:
第三管芯,其耦合到衬底,第三管芯包括第三组管芯触点;以及
第三组桥式触点,其被包括在第一桥式互连件中,其中:
第三组桥式触点利用互连材料直接耦合到第三组管芯触点,以及
第一桥式互连件便于第一管芯、第二管芯和第三管芯之间的电连通。
CN201980021961.1A 2018-06-04 2019-05-03 多芯片封装 Pending CN111886693A (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN202311804371.0A CN117794254A (zh) 2018-06-04 2019-05-03 多芯片封装
CN202311804375.9A CN117794255A (zh) 2018-06-04 2019-05-03 多芯片封装

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US15/996870 2018-06-04
US15/996,870 US10700051B2 (en) 2018-06-04 2018-06-04 Multi-chip packaging
PCT/US2019/030614 WO2019236226A1 (en) 2018-06-04 2019-05-03 Multi-chip packaging

Related Child Applications (2)

Application Number Title Priority Date Filing Date
CN202311804375.9A Division CN117794255A (zh) 2018-06-04 2019-05-03 多芯片封装
CN202311804371.0A Division CN117794254A (zh) 2018-06-04 2019-05-03 多芯片封装

Publications (1)

Publication Number Publication Date
CN111886693A true CN111886693A (zh) 2020-11-03

Family

ID=68693618

Family Applications (3)

Application Number Title Priority Date Filing Date
CN201980021961.1A Pending CN111886693A (zh) 2018-06-04 2019-05-03 多芯片封装
CN202311804371.0A Pending CN117794254A (zh) 2018-06-04 2019-05-03 多芯片封装
CN202311804375.9A Pending CN117794255A (zh) 2018-06-04 2019-05-03 多芯片封装

Family Applications After (2)

Application Number Title Priority Date Filing Date
CN202311804371.0A Pending CN117794254A (zh) 2018-06-04 2019-05-03 多芯片封装
CN202311804375.9A Pending CN117794255A (zh) 2018-06-04 2019-05-03 多芯片封装

Country Status (6)

Country Link
US (5) US10700051B2 (zh)
EP (5) EP4325552A2 (zh)
KR (3) KR20220054893A (zh)
CN (3) CN111886693A (zh)
TW (2) TWI828121B (zh)
WO (1) WO2019236226A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11348911B2 (en) 2018-06-04 2022-05-31 Intel Corporation Multi-chip packaging

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102397902B1 (ko) * 2018-01-29 2022-05-13 삼성전자주식회사 반도체 패키지
US10879155B2 (en) * 2019-05-09 2020-12-29 Texas Instruments Incorporated Electronic device with double-sided cooling
US11315902B2 (en) * 2020-02-12 2022-04-26 International Business Machines Corporation High bandwidth multichip module
US11955448B2 (en) * 2020-05-21 2024-04-09 Intel Corporation Architecture to manage FLI bump height delta and reliability needs for mixed EMIB pitches
US11728254B2 (en) * 2020-05-22 2023-08-15 Taiwan Semiconductor Manufacturing Co., Ltd. Giga interposer integration through chip-on-wafer-on-substrate
US20220199562A1 (en) * 2020-12-22 2022-06-23 Intel Corporation Assembly of 2xd module using high density interconnect bridges
US20220208712A1 (en) * 2020-12-28 2022-06-30 Advanced Micro Devices, Inc. Multi-level bridge interconnects
US20230095134A1 (en) * 2021-09-29 2023-03-30 Taiwanj Semiconductor Manufacturing Co., Ltd. Method and structure for a bridge interconnect

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4581768B2 (ja) * 2005-03-16 2010-11-17 ソニー株式会社 半導体装置の製造方法
CN101232004A (zh) * 2007-01-23 2008-07-30 联华电子股份有限公司 芯片堆叠封装结构
US9059179B2 (en) * 2011-12-28 2015-06-16 Broadcom Corporation Semiconductor package with a bridge interposer
US8704364B2 (en) * 2012-02-08 2014-04-22 Xilinx, Inc. Reducing stress in multi-die integrated circuit structures
JP6195995B2 (ja) * 2014-02-26 2017-09-20 インテル コーポレイション ブリッジ貫通導電ビア信号接続を有する埋込マルチデバイスブリッジ
US20150364422A1 (en) * 2014-06-13 2015-12-17 Apple Inc. Fan out wafer level package using silicon bridge
US9595496B2 (en) 2014-11-07 2017-03-14 Qualcomm Incorporated Integrated device package comprising silicon bridge in an encapsulation layer
US9418966B1 (en) 2015-03-23 2016-08-16 Xilinx, Inc. Semiconductor assembly having bridge module for die-to-die interconnection
US9653428B1 (en) * 2015-04-14 2017-05-16 Amkor Technology, Inc. Semiconductor package and fabricating method thereof
US9595494B2 (en) 2015-05-04 2017-03-14 Qualcomm Incorporated Semiconductor package with high density die to die connection and method of making the same
US20160343685A1 (en) * 2015-05-21 2016-11-24 Mediatek Inc. Semiconductor package assembly and method for forming the same
US9761533B2 (en) * 2015-10-16 2017-09-12 Xilinx, Inc. Interposer-less stack die interconnect
US10163856B2 (en) * 2015-10-30 2018-12-25 Taiwan Semiconductor Manufacturing Company, Ltd. Stacked integrated circuit structure and method of forming
CN108292654A (zh) * 2015-12-11 2018-07-17 英特尔公司 具有利用嵌入微电子衬底中的微电子桥连接的多个微电子器件的微电子结构
TWI652778B (zh) * 2016-01-27 2019-03-01 艾馬克科技公司 半導體封裝以及其製造方法
US9761559B1 (en) 2016-04-21 2017-09-12 Micron Technology, Inc. Semiconductor package and fabrication method thereof
WO2018009145A1 (en) * 2016-07-08 2018-01-11 Agency For Science, Technology And Research A semiconductor package and methods of forming the same
US10510721B2 (en) * 2017-08-11 2019-12-17 Advanced Micro Devices, Inc. Molded chip combination
US10700051B2 (en) 2018-06-04 2020-06-30 Intel Corporation Multi-chip packaging

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11348911B2 (en) 2018-06-04 2022-05-31 Intel Corporation Multi-chip packaging
US11817444B2 (en) 2018-06-04 2023-11-14 Intel Corporation Multi-chip packaging

Also Published As

Publication number Publication date
EP3803973A4 (en) 2022-06-29
TW202339177A (zh) 2023-10-01
US10700051B2 (en) 2020-06-30
EP4235755A3 (en) 2024-02-21
US20220157803A1 (en) 2022-05-19
TWI808163B (zh) 2023-07-11
WO2019236226A1 (en) 2019-12-12
EP3982407A3 (en) 2022-07-20
EP4060733A3 (en) 2022-11-16
KR20210004963A (ko) 2021-01-13
US11348911B2 (en) 2022-05-31
KR20220054893A (ko) 2022-05-03
EP3803973A1 (en) 2021-04-14
EP4325552A2 (en) 2024-02-21
US20200395352A1 (en) 2020-12-17
TW202232709A (zh) 2022-08-16
US20190371778A1 (en) 2019-12-05
EP4235755A2 (en) 2023-08-30
EP3982407A2 (en) 2022-04-13
TW202011559A (zh) 2020-03-16
EP4060733A2 (en) 2022-09-21
TWI828121B (zh) 2024-01-01
KR20240001718A (ko) 2024-01-03
US20240128256A1 (en) 2024-04-18
US20220231007A1 (en) 2022-07-21
US11817444B2 (en) 2023-11-14
CN117794255A (zh) 2024-03-29
CN117794254A (zh) 2024-03-29

Similar Documents

Publication Publication Date Title
TWI828121B (zh) 多晶片封裝
US11764158B2 (en) Embedded multi-die interconnect bridge packages with lithographically formed bumps and methods of assembling same
US11270941B2 (en) Bare-die smart bridge connected with copper pillars for system-in-package apparatus
US20210225807A1 (en) Scalable embedded silicon bridge via pillars in lithographically defined vias, and methods of making same
US11658111B2 (en) Stripped redistrubution-layer fabrication for package-top embedded multi-die interconnect bridge
US20220238440A1 (en) Bare-die smart bridge connected with copper pillars for system-in-package apparatus
TWI835658B (zh) 多晶片封裝
TW202416494A (zh) 多晶片封裝

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination