CN1685513A - 光电二极管阵列及其制造方法 - Google Patents
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Abstract
光电二极管阵列的特征在于,具有:在光入射面侧矩阵状形成pn结型多个光电二极管的、入射面的相反面由(100)面构成的半导体基板;在由光电二极管彼此所夹着的区域形成的、从半导体基板的入射面侧贯通到相反面侧的贯通孔;从入射面开始通过贯通孔的壁面到相反面连接的导电体层,贯通孔通过将在入射面侧相对入射面大致垂直地形成的垂直孔部和在相反面侧形成的四角锥形的孔部,在半导体基板内部连接而形成,四角锥形的孔部的壁面形成为(111)面。
Description
技术领域
本发明涉及光电二极管阵列及其制造方法。
背景技术
CT(computed tomography)用光电二极管阵列被要求大面积化,为了除去光电二极管阵列的不敏感区域,需要进行三维安装,将信号处理部配置在光入射面的相反侧(里面侧)。为此,需要使用贯通布线,将入射面侧(表面侧)形成的电极引导到入射面的相反侧(里面侧)。
使用了这样的贯通布线的半导体元件,在例如下述专利文献1、专利文献2等中得到公开。在专利文献1中公开的半导体元件,为形成贯通孔,要使用碱性溶液的湿蚀刻来蚀刻基板,所以基板要以相对基板表面成54.7°的角度,被进行蚀刻。
专利文献1:特开平5-29483号公报
专利文献2:特开平6-177201号公报
但是,如果使用该技术,利用贯通布线来连接光电二极管阵列的各个光电二极管的电极,贯通孔就会随着从表面侧进入里面侧,孔径逐渐扩大。为此,光电二极管相互之间不能太靠近地形成,开口率受到限制。
图14是现有技术的光电二极管阵列的截面图。
如图14所示,在仅使用上述蚀刻的情况下,基板表面侧的面,和贯通孔内壁和表面所成的θ角是锐角。因此,在由贯通布线17覆盖规定该锐角的角20的情况下,容易引起在角20的部分由于布线的敷层不佳导致的导通不良。
另一方面,也考虑使用干蚀刻来形成与基板表面垂直的贯通孔的方法,但在厚度250~400μm的基板上,形成孔径均等的贯通孔在现实中是不可能的。另外,由于干蚀刻加工的速度较慢,如果是贯通厚度为250~400μm的基板,就需要较长的处理时间。
发明内容
因此,本发明的目的在于,解决上述问题,提供一种不易引起贯通布线的导通不良,开口率高的光电二极管阵列。
为了解决上述问题,本发明的光电二极管阵列,具有在第一导电型基板的被检测光的入射面侧矩阵状形成pn结型多个光电二极管、入射面的相反面由(100)面构成的半导体基板,具有在光电二极管彼此所夹的区域所形成的、从半导体基板的入射面侧贯通到相反面侧的贯通孔,其特征在于,
具有从入射面通过贯通孔的壁面到相反面连通的导电体层,该贯通孔具有在入射面侧相对入射面大致垂直地形成的垂直孔部、在相反面侧形成的四角锥形的锥形孔部,垂直孔部和锥形孔部在半导体基板内部连接,锥形孔部的壁面为(111)面。
而且,大致垂直的意思是85°~90°的角度范围内的交叉状态。
根据上述光电二极管阵列,从入射面通过贯通孔的壁面到相反面连接的导电体层的覆盖角,全部是90°以上,所以,不易引起由导电体层的敷层不佳导致的导通不良。另外,由于能够使光电二极管彼此接近,所以能够提高开口率。
本发明的光电二极管阵列的特征在于,在半导体基板内具有包围上述贯通孔形成的第一导电型高杂质浓度层。
上述光电二极管阵列在贯通孔的周围具有高杂质浓度层,所以既使发生由贯通孔的机械损坏导致的不必要的载流子,也能够在层内截止,能够抑制泄漏电流、暗电流。
本发明的光电二极管阵列的制造方法,其特征在于,具有以下工序:
第一工序,准备第一面是(100)面的半导体基板,在第一面的相反面的第二面的规定区域,矩阵状地形成pn结型多个光电二极管;
第二工序,对多个光电二极管的每一个,通过各向异性蚀刻,形成从半导体基板的第一面侧开始的不到半导体基板厚度的深度的四角锥形的锥形凹部;
第三工序,从与锥形凹部对应的位置的第二面侧开始,通过干蚀刻,在第二面形成大致垂直的垂直孔,通过连接锥形凹部和垂直孔,形成从半导体基板的第二面贯通到第一面的贯通孔;
第四工序,形成从第二面开始通过贯通孔到第一面连接的导电体层。
如根据上述制造方法,在形成四角锥形的锥形凹部后,形成垂直孔。由于形成的锥形凹部的深度不到半导体基板的厚度,所以蚀刻溶液不泄漏到第二面侧,所以不会对第二面侧的光电二极管造成不良影响。
附图说明
图1是第一实施方式的光电二极管阵列的平面图。
图2是第一实施方式的光电二极管阵列的截面图。
图3A是形成贯通孔的部分的平面图。
图3B是形成贯通孔的部分的III-III箭头纵截面图。
图3C是形成贯通孔的部分的立体图。
图4是光电二极管阵列的截面图。
图5是光电二极管阵列的截面图。
图6是光电二极管阵列的截面图。
图7是用于说明光电二极管阵列的制造工序的光电二极管阵列的截面图。
图8是用于说明光电二极管阵列的制造工序的光电二极管阵列的截面图。
图9是用于说明光电二极管阵列的制造工序的光电二极管阵列的截面图。
图10是用于说明光电二极管阵列的制造工序的光电二极管阵列的截面图。
图11是用于说明光电二极管阵列的制造工序的光电二极管阵列的截面图。
图12是光电二极管阵列的截面图。
图13A是光电二极管阵列的贯通孔部分的截面图。
图13B是光电二极管阵列的贯通孔部分的截面图。
图14是现有技术的光电二极管阵列的截面图。
具体实施方式
下面,说明本发明的实施方式。另外,对相同元件使用相同的符号,省略重复说明。
图1是将本发明的第一实施方式的光电二极管阵列的一部分放大的平面图,图2是其截面图。
在下面的说明中,将入射光的面设为表面,将其相对的面设为里面。本实施方式的光电二极管阵列1,在表面侧,纵横有规则地以矩阵状排列多个pn结(光电二极管)4,每个pn结都具有作为光电二极管阵列的一个受光像素的功能。
光电二极管阵列1包括厚度为270μm、杂质浓度为1×1012~1015/cm3的n型硅基板3,以大小为500μm×500μm、深度为0.5~1μm、间距为1.5mm左右,来配置杂质浓度为1×1013~1020/cm3的多个p型杂质扩散层5。
通过由n型硅基板3和多个p型杂质扩散层5形成的pn结4,构成上述受光像素。另外,在同样的p型杂质扩散层5之间,配置用来通过分离光电二极管之间,截止不需要的载流子而降低暗电流的n+型杂质区域(分离层)7。另外,在里面侧配置n+侧的电极21。
在相邻的pn结4彼此之间,在表面侧形成第一孔部11(垂直孔部),在里面侧形成第二孔部13(锥形孔部)。
图3A是形成贯通孔的部分的平面图,图3B是形成贯通孔的部分的III-III箭头的纵截面图,图3C是形成贯通孔的部分的立体图。
贯通孔12是连结第一孔部11、第二孔部13而形成,第一孔部11是直径为10μm,在基板的表面侧,与基板的厚度方向大致平行地被打开。第一孔部11,与基板的厚度方向大致平行且呈圆柱状地形成,在贯通分离层7的位置形成。另外,孔的深度形成为达到p型杂质扩散层5所形成的深度以上。由此,第二孔部13就会不限制从pn结4延伸的耗尽层,而能够接近p型杂质扩散层5来设置。
第二孔部13从基板里面侧形成四角锥形,孔径越向里面侧越大,越向表面侧越小。第二孔部13是从里面侧开始,通过各向异性蚀刻来形成,所以在孔部壁面露出(111)面,壁面相对光电二极管阵列的表面,大致形成54.7°的角度(图3B的角度α54.7°)。第二孔部13形成四角锥形,由此容易在孔部内壁上设置导电体层(贯通布线)。
第一孔部11和第二孔部13在基板内部连接,形成一个贯通孔12。基板表面和里面,包括贯通孔12的壁面、p型杂质扩散层5的表面侧,由硅的热氧化膜9来覆盖。而且,不限于硅氧化膜,也可以根据需要的光电二极管的波长灵敏度,形成AR(Antireflection)敷层。AR敷层可以是SiO2、SiNx单层,和包含它们的绝缘体复合膜或者叠层膜。
贯通布线17在上述热氧化膜9的上层用铝形成,通过在热氧化膜9上挖空的接触孔15,与p型杂质扩散层5接触。此外也可以通过贯通孔12的壁面,与里面侧相连而形成,使得与p型杂质扩散层5的电接触能够从里面侧来进行。此时的第一孔部11由贯通布线17的金属来填充,既使基板表面侧和里面侧,在空间上形成分开的结构,由于没有失去p型杂质扩散层5和里面侧的电接触,所以也没有关系(参照图4)。
图4是光电二极管阵列的截面图,在该光电二极管阵列中,第一孔部11的内部,由贯通布线17填充,光电二极管阵列的里面,与p型杂质扩散层5电连接。
这里,贯通布线17的材料不限于铝,也可以使用铜、镍、金、钨、钛、多晶硅等、或者含有它们的合金或者叠层金属。而且,也可以使用CVD的氧化膜代替上述热氧化膜9。另外,也可以在上述热氧化膜9和贯通布线17之间,介插CVD的氧化膜或者氮化膜。这样,就能够确保硅基板和贯通布线17之间的高绝缘性。
图5是光电二极管阵列的截面图。在该光电二极管阵列中,通过在贯通孔12内部,在贯通布线17的上层填充树脂等充填材料10,使得贯通孔12被填埋。这样,基板表面侧和里面侧在空间上被断开,而p型杂质扩散层5和里面侧没有失去电接触,就会提高光电二极管阵列1的机械强度。
此时,作为充填贯通孔12的材料,使用含有环氧、聚酰亚胺、丙烯酸、硅、尿烷等树脂系列绝缘材料,或者,使用在这些绝缘材料中含有电导电性填料的电导电性树脂。
图6是光电二极管阵列的截面图。
也可以通过在贯通孔12内部充填导电性材料10来填埋贯通孔12。充填的导电性材料,不仅可提高光电二极管阵列1的机械强度,而且如图6所示,超过第二孔部13的里面的边缘隆起,超过里面的边缘的部分形成半球状,还能够原样作为凸起电极来使用。导电性材料10也可以使用含有焊料或电导电性填料的电导电性树脂等。
接着,说明所述光电二极管阵列的制造方法。
下面,说明向贯通孔12的内部充填聚酰亚胺树脂的光电二极管阵列(参照图5)的制造方法。
图7是用于说明光电二极管阵列的制造工序的光电二极管阵列的截面图。
首先,准备结晶面(100)的n型半导体基板3,在基板表面上形成热氧化膜9,作为下一工序的n+热扩散掩膜来使用。将成为分离层7的位置的热氧化膜,通过光蚀刻处理而开口,使磷热扩散、热氧化。此时,在里面整个区域的磷被扩散,形成n+型杂质浓度层19。
图8是用于说明光电二极管阵列的制造工序的光电二极管阵列的截面图。
接着,同样将形成pn结4的区域的热氧化膜开口,将硼热扩散、热氧化。该pn结4的区域成为与受光像素对应的部分。在里面通过等离子CVD或者LP-CVD来形成氮化硅膜(SiNx)23(参照图8),通过蚀刻除去形成第二孔部13的部分的氮化硅膜23和热氧化膜9。形成第二孔部13的部分成为与分离层7对应的里面侧的位置。
此时,氮化硅膜23的除去部分的形状和尺寸预先设计成,使得第二孔部13的四角锥顶点,通过后述的碱性蚀刻,达不到基板表面侧,而且,四角锥顶点成为与表面侧的分离层7对应的位置。
图9是用于说明光电二极管阵列的制造工序的光电二极管阵列的截面图。
而且,通过碱性(例如氢氧化钾溶液、TMAH、联氨、EDP等)蚀刻,从里面侧对半导体基板3进行各向异性蚀刻,形成第二孔部13。即,从基板的结晶面(100)进行蚀刻,露出(111)面。第二孔部13通过蚀刻形成四角锥形(金字塔形),当蚀刻到四角锥形的顶点时,自动停止(参照图9)。
另外,也可以在到达四角锥形的顶点之前,停止蚀刻。接着,通过在与形成的四角锥形的顶点对应的部分,从表面侧进行干蚀刻,形成第一孔部11,由此进行蚀刻直到与第二孔部13的四角锥形顶点连接,形成由第一孔部11和第二孔部13所形成的贯通孔12。
图10是用于说明光电二极管阵列的制造工序的光电二极管阵列的截面图。
而且,从基板表面进行离子注入或者扩散,形成包围贯通孔12的n+层25。该n+层25与分离层7和里面侧的n+型杂质浓度层19连接。之后,为了确保侧壁的绝缘,通过热氧化形成SIO2膜27(参照图10)。侧壁的绝缘膜也可以是除该SiO2膜27之外的SiNx的叠层膜、CVD的SiO2膜等。
接着,在p+、n+层设计接触孔15后,为了形成贯通布线17,通过溅射装置从两面沉积铝,形成抗蚀剂,通过蚀刻形成希望的图案。贯通布线17的材料不限于铝,另外,布线的形成方法也不限于溅射法。例如,也可以由CVD对多晶硅进行降低电阻抗的扩散。这种情况下,可以仅在接触孔部分使用铝,与上述多晶硅电连接。
图11是用于说明光电二极管阵列的制造工序的光电二极管阵列的截面图。
在里面侧形成感光性聚酰亚胺层29,仅在想配置凸起电极33的位置开口。同时,n+侧电极21的部分也开口,在此设置凸起电极33。而且,通过由与凸起电极33电·物理连接优异的金属形成的Under BumpMetal(下面称为“UBM”)37来形成凸起电极33。例如,在将凸起电极33形成为焊料凸起的情况下,由于焊料不与铝浸润,所以需要形成浸润性金属作为中介。这种情况下的UBM,有时通过非电解电镀形成Ni-Au,有时通过剥离法来形成Ti-Pt-Au或者Cr-Au来实现。
也可以使用丙烯酸层或者环氧层或者含有它们的复合材料层来代替聚酰亚胺层。焊料凸起,能够通过由焊料球搭载法或者印刷法在规定的UBM部分形成焊料倒流而形成。凸起电极33不限于焊料凸起,也可以使用金凸起、镍凸起、铜凸起、导电性树脂凸起等包含金属的导电性凸起。
图12是光电二极管阵列的截面图。
在上述制造方法中,首先,通过准备n型半导体基板进行热扩散,形成n+型杂质浓度层,但如图12所示,也可以通过预先热扩散或者外延式生长,准备设置了n+型杂质浓度层的n型半导体基板。由此,能够将光电二极管阵列的n+型杂质浓度层的厚度变厚,实质p型杂质扩散层5和n+型杂质浓度层19之间变窄,这样,能够降低电阻成分,提高高速应答性。
另外,通过调节实质p型杂质扩散层5和n+型杂质浓度层19的间隔,能够得到与式样对应的分光灵敏度曲线特性。
下面,说明上述光电二极管阵列和其制造方法的作用。
上述光电二极管阵列先通过碱性蚀刻从里面侧形成第二孔部13,之后,通过形成第一孔部11来形成贯通孔12。因此,在碱性蚀刻工序的时候,由于还没有完成贯通孔12,不会由碱性蚀刻导致对表面侧进行侵蚀,特别是不会对受光面造成不良影响,所以能够防止成品率的降低。
另外,在碱性蚀刻工序中,当第二孔部13被蚀刻到四角锥形的顶点时停止,所以,不需要另外设置蚀刻停止层等。此外,由于贯通孔12的大部分(第二孔部13)是通过各向异性蚀刻来形成的,所以能够得到壁面上凹凸少的、光滑的贯通孔壁面。因此,由于贯通孔壁面的损坏而导致的不必要的载流子的发生也会变少,能够减少暗电流。
图13A和图13B是光电二极管阵列的贯通孔的部分的截面图。
第二孔部13的壁面相对光电二极管阵列的表面,形成54.7°的角度,第一孔部11的壁面相对上述阵列方向大致垂直。
在仅使用碱性蚀刻,贯通孔仅由第二孔部13形成的情况下,第二孔部和光电二极管阵列表面直接连接,它们的面彼此所形成的角度θ是锐角。
另一方面,在图13A所示的光电二极管阵列中,连接两个孔部形成贯通孔12,所以孔部的连接部分所形成的角度B是90°以上。此外,第二孔部13和光电二极管阵列里面所成的角度A也是90°以上,第一孔部11和光电二极管阵列表面所成的角度C为大致90°。
由此,从表面到贯通孔12的壁面、里面连接的贯通布线17没有弯曲成锐角的部分,能够抑制形成时的敷层不佳所导致的导通不良的发生。此外,根据第一孔部11形成时的干蚀刻的条件,如图13B所示,能够将第一孔部11形成锥形,能够将角度C形成为90°以上。由此,能够进一步抑制导通不良。
在上述光电二极管阵列中,由于第二孔部13通过碱性蚀刻来形成,能够向贯通孔12的壁面进行离子注入,通过离子注入,能够容易地形成n+层25。形成的n+层25,实现了作为分离各个光电二极管的分离层的目的,同时实现了截止不需要的载流子、降低暗电流的目的。
在上述光电二极管阵列中,形成第一孔部11使得贯通分离层7。由此,在进行形成第一孔部11的干蚀刻时,既使孔部内壁有损害等,所产生的不必要的载流子也会由分离层7截止。因此,上述光电二极管阵列,能够防止贯通布线形成时的损害所导致的泄漏电流等。
按照上面所述,根据本发明,能够提供不易引起贯通布线的导通不佳,开口率高的光电二极管阵列。
产业上的可利用性
本发明能够用于光电二极管阵列和其制造方法。
Claims (3)
1.一种光电二极管阵列,具有在第一导电型基板的被检测光的入射面侧矩阵状形成pn结型多个光电二极管的、所述入射面的相反面由(100)面构成的半导体基板,所述半导体基板,具有在所述光电二极管彼此所夹的区域所形成的、从所述半导体基板的所述入射面侧贯通到所述相反面侧的贯通孔,其特征在于,
具有从所述入射面通过所述贯通孔的壁面到所述相反面连通的导电体层,
所述贯通孔具有:在所述入射面侧相对所述入射面大致垂直地形成的垂直孔部、在所述相反面侧形成的四角锥形的锥形孔部,
所述垂直孔部和所述锥形孔部在所述半导体基板内部连接,
所述锥形孔部的壁面形成为(111)面。
2.根据权利要求1所述的光电二极管阵列,其特征在于,
在所述半导体基板内具有包围所述贯通孔形成的第一导电型的高杂质浓度层。
3.一种光电二极管阵列的制造方法,其特征在于,具有以下工序:
第一工序,准备第一面是(100)面的半导体基板,在作为所述第一面的相反面的第二面的规定区域,矩阵状地形成pn结型多个光电二极管;
第二工序,对所述多个光电二极管的每一个,通过各向异性蚀刻,形成从所述半导体基板的第一面侧开始的不到所述半导体基板厚度的深度的四角锥形的锥形凹部;
第三工序,从与所述锥形凹部对应的位置的第二面侧开始,通过干蚀刻在所述第一面,形成大致垂直的垂直孔,通过连接所述锥形凹部和所述垂直孔,形成从所述半导体基板的所述第二面,贯通到所述第一面的贯通孔;
第四工序,形成从所述第二面开始,通过所述贯通孔到所述第一面连接的导电体层。
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AU (1) | AU2003268667A1 (zh) |
IL (1) | IL167626A (zh) |
WO (1) | WO2004030102A1 (zh) |
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CN110379766A (zh) * | 2019-06-26 | 2019-10-25 | 中国电子科技集团公司第三十八研究所 | 一种倒金字塔型硅通孔垂直互联结构及制备方法 |
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- 2003-09-24 JP JP2004539506A patent/JP4554368B2/ja not_active Expired - Fee Related
- 2003-09-24 KR KR1020057004880A patent/KR101087866B1/ko not_active IP Right Cessation
- 2003-09-24 EP EP03748574A patent/EP1551060B1/en not_active Expired - Fee Related
- 2003-09-24 EP EP14168605.5A patent/EP2768025B1/en not_active Expired - Fee Related
- 2003-09-24 WO PCT/JP2003/012163 patent/WO2004030102A1/ja active Application Filing
- 2003-09-24 CN CNB038226863A patent/CN100399570C/zh not_active Expired - Lifetime
- 2003-09-24 EP EP12173415.6A patent/EP2506305B1/en not_active Expired - Fee Related
- 2003-09-24 AU AU2003268667A patent/AU2003268667A1/en not_active Abandoned
- 2003-09-24 EP EP15192319.0A patent/EP2996148B1/en not_active Expired - Fee Related
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2005
- 2005-03-23 IL IL167626A patent/IL167626A/en unknown
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Also Published As
Publication number | Publication date |
---|---|
EP1551060A1 (en) | 2005-07-06 |
JP2010034591A (ja) | 2010-02-12 |
EP2768025B1 (en) | 2016-01-06 |
WO2004030102A1 (ja) | 2004-04-08 |
JP5198411B2 (ja) | 2013-05-15 |
EP1551060A4 (en) | 2008-03-12 |
JP4554368B2 (ja) | 2010-09-29 |
EP2996148B1 (en) | 2018-11-07 |
EP2506305B1 (en) | 2014-11-05 |
JPWO2004030102A1 (ja) | 2006-01-26 |
IL167626A (en) | 2010-11-30 |
EP2996148A1 (en) | 2016-03-16 |
EP2768025A1 (en) | 2014-08-20 |
CN100399570C (zh) | 2008-07-02 |
KR20050057533A (ko) | 2005-06-16 |
KR101087866B1 (ko) | 2011-11-30 |
EP2506305A1 (en) | 2012-10-03 |
EP1551060B1 (en) | 2012-08-15 |
AU2003268667A1 (en) | 2004-04-19 |
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