TW594983B - Method for manufacturing photodiode and the structure thereof - Google Patents

Abstract

A method for manufacturing photodiode and the structure thereof, wherein the photodiode is divided into two major regions, comprising: one pixel array region with an amorphous silicon layer of a first polarity and the other region without the amorphous silicon layer of the first polarity. Besides, a rear electrode (the amorphous silicon layer of the first polarity and a metal layer) is connected to an intrinsic amorphous silicon layer via dielectric holes having large area. Moreover, a transparent electrode is electrically connected to a solder bump subsequently formed in a pad hole via the metal layer located on a ground pad region. Furthermore, the passivation on the transparent electrode in the pixel array region is removed by etching, thereby forming a window to accept incident light.

Description

594983 V. Description of the invention (1) ~ The technical field to which the invention belongs: The present invention relates to a photodiode (1)]: 1〇1: 〇 (1 丨 〇 (16) manufacturing method and structure, particularly The invention relates to a manufacturing method and structure of an elevated (Elevated) p + type amorphous silicon / intrinsic amorphous silicon / N + type amorphous silicon (ρίΝ) thin film photodiode. Prior technology: conventional image sense Sensor (Image Sensor) or pixel (pi X e 1) elements, such as photodiodes, are fabricated directly on silicon substrates. However, as the size of pixel elements is miniaturized, multiple layers are used. Interconnection structure to increase circuit density. In this way, the photosensitivity will decrease due to the effects of light scattering and low fill factor, and then affect the ability of the pixel element to capture In order to solve the problem caused by the miniaturization of the pixel element size, an elevated PIN film pixel element has been developed to increase the fill factor and thereby increase the light sensitivity. The so-called elevated pixel element It means that the photodetector 9 is lifted from the silicon substrate to the upper conductor layer above the interconnect structure. In this way, the light sensed by the photodetector does not need to pass through the interconnect structure, and the light intensity can be avoided It is affected by the generated light scattering. In addition, when the photodetector is fabricated on the upper conductor layer above the interconnect structure, the production area of the photodetector can be greatly increased, so that the fill factor can be greatly increased, thereby effectively improving the capacity. Captured light intensity. Please refer to Figure 1 to Figure 4, which are cross-sectional views showing the process of a conventional elevated film photodiode. First, the substrate 100 is provided. The substrate provided here

594983

100 can be formed with necessary components for forming a photosensitive element, such as a transistor and a main b moving region, and since the photosensitive diode is an overhead type, the substrate 10 also includes an interconnect structure located above On the transistor or active area. Then, the metal layer 102 shown in FIG. 1 is formed to cover the substrate 100 and expose the substrate 100, so that the metal layer with the desired pattern is formed on the substrate 1 0 2 ′ to form the structure shown in FIG. 1. Then, an N + -type amorphous silicon layer 104 is deposited to cover the metal layer 102 and the exposed substrate 100 at the same time to form a structure as shown in FIG. 2. The lithography and etching techniques are then used to define the N + -type amorphous silicon layer 104, thereby exposing a portion of the substrate 100 to pattern the N + -type amorphous stone layer 104. The patterned n + -type amorphous stone layer 104 is only coated on the periphery of the metal layer, and the N + -type amorphous silicon layer is coated with the metal layer 102 to form a back electrode (Rear Electr). 〇deM〇f, and the structure as shown in Figure 3. In order to ensure the reliability of the process, with a view to making the N + type amorphous stone layer 104 completely cover the metal layer 10 after the patterning process is completed 'Therefore, the pattern width of the N + -type amorphous silicon layer 104 must be larger than the pattern width of the metal layer \ 002. The width 10 shown in Figure 4 is about 02 # ^, so that the ^ -type amorphous silicon layer The size of 1 04 will be much larger than the size of the metal layer 1 02 covered by it. After the back electrode 105 is formed, an intrinsic amorphous silicon layer 10 and a p + type amorphous layer 108 are sequentially formed to cover the N + type. Amorphous stone layer 104 and exposed substrate 100. Among them, P + -type amorphous silicon layer 108, intrinsic amorphous silicon layer 106, and N + -type amorphous silicon layer 104 together constitutes the PI N thin film stack structure. After the PIN thin film stack structure is formed, a transparent electrode 110 is formed to cover the P + type amorphous silicon layer 108 as an electrode on the pixel element, and so on. Production of the pixel elements (e.g., first

594983 V. Description of the invention (3) (4). In the above-mentioned conventional method for manufacturing a photodiode, the reason why the N + -type amorphous silicon layer 104 can completely cover the metal layer 102 is necessary. The reason is that in order to avoid the direct contact between the metal layer 102 and the intrinsic amorphous silicon layer 106 formed later, a Schottky junction interface is generated to prevent the generation of vertical leakage current. Therefore, how to make the metal layer 102 of the back electrode 105 and the intrinsic amorphous silicon layer 106 not conductive with each other to prevent the occurrence of vertical leakage current is the main consideration when manufacturing an overhead thin film photodiode. In addition, the subsequent interconnection process of the transparent electrode 110 is another important consideration when manufacturing such a photodiode. Summary of the Invention: In view of the above background of the invention, the process of interconnecting the transparent electrode, the insulation between the metal layer of the back electrode and the intrinsic amorphous silicon layer, and the prevention of vertical leakage current are the main considerations for the process of the overhead thin film photodiode. . Therefore, an object of the present invention is to provide a method and structure for manufacturing a photodiode, which can eliminate the Schottky interface 'between the metal layer of the back electrode and the intrinsic amorphous silicon layer to reduce vertical leakage current. Another object of the present invention is to provide a manufacturing method and structure of a photodiode, which can form a ground pad with high reliability and low resistance. Another object of the present invention is to provide a method and a structure for manufacturing a photodiode, by which a high-sensitivity image sensor with high reliability can be manufactured. According to the above object of the present invention, the present invention provides a method for manufacturing a photodiode f, which includes at least the following steps. First provided with ground pad area, pixel array area, and special application integrated circuit (Appl icat i〇n

594983 V. Description of Invention (4)

Specific integrated circuit · KTrw forms a metal layer to cover the substrate. Then, take the # 2 substrate. A metal layer is then formed in the region. Formed with a number of non-said Shi Xi layer covering the pixel array amorphous silicon layer and metal layer, and a first layer of dielectric layer covering the first round, thereby respectively exposing gold: = = = 和 "阵” ΐ m Shi Xi layer covers and fills the pixel array area ":: 'in the opening. Then, a second electrode is formed, and a transparent electrode is formed to cover the third non-Brij y layer in the first opening of the ground pad region. The above-mentioned purpose of "9" electric layer and filling in the position "the manufacturing method provided by the present invention" includes at least the following steps. =-The pole body material includes at least the ground pad area, the pixel, and the earth material. Then, a part of the first electrical application integrated circuit area is formed with a special part of the metal JB Miao 14 14 14 14 Japanese and Japanese silicon layer 'fine to expose the metal sound of the part ^ remove the first electrical properties The amorphous silicon layer and the second part = belong to i, the first metal layer pattern is located in the ground welding area, the first metal layer pattern is located on the pixel array area, and the third gold is located in the special application integrated circuit area And then exposed a part of the substrate: =, f becomes a dielectric layer, and this dielectric layer covers the exposed part of the substrate, the second metal layer, and the first electrically amorphous silicon layer, and This dielectric layer further includes a first dielectric layer hole (Dielectric Hoie) penetrating the dielectric layer located on the ground pad area, and a plurality of second dielectric layer holes penetrating a portion of the dielectric layer located on the pixel array area. To expose part of the metal layer and part of the

Li, Zhi, Ming explained that the brother of an electric amorphous second layer. Tingri Shixi g soil straight X Chu people, forming an intrinsic amorphous silicon layer, this; ^ «π said that the silicon layer is filled with a hole in the dielectric layer and the second dielectric sound :: : The layer is covered with the above-mentioned dielectric layer. Next, the shape of the second intrinsic non-integrated circuit area; the dielectric region and the intrinsic amorphous silicon layer exposed in the sexual region and the special application, and later formed a transparent electrode: = in the hole Part of the metal layer. However, the second electro-crystalline amorphous stone pole is filled into the first dielectric layer hole order, and the dielectric layer is formed on and in accordance with the present invention. It is described by the society, so the present invention provides a 礞 光 -lapse # ,,, and mouth structure, including at least the substrate, and α light monopole = and special application integrated circuit area: =] It seems: array area, layer A gold plated substrate covering the pixel array area. The first amorphous silicon covers the metal of the -amorphous silicon layer; the dielectric layers of the first-openings and the pixel array region are formed by an opening in the ground pad region. The second amorphous stone ^ * I do not burst out of the metal layer and the first amorphous silicon opening. First: the first layer of the dielectric layer filled in the pixel array area: the first: "the evening layer covers the second amorphous stone layer. And, the" transparent "second-non -... and the dielectric layer , And fill in the grounding; ϋ

According to the structures of $ μ, +, and Q of the present invention, to the present invention, a photodiode substrate is provided. The metal layer covers the substrate, where = the substrate of the graphic pixel array region and the third metal on the substrate of the special application integrated circuit region. Article No. 594983 V. Description of the Invention (6) The silicon layer is located on the metal layer of the pixel array region. Yun Qiu Ba Iu is like eight '丨 electricity'. This dielectric layer is covered with a p-knife substrate, a metal layer of a trowel, and a part of an electrical silicon layer. The dielectric layer in the ground pad region A dielectric layer hole is provided; the crystalline layer is located on a part of the dielectric layer of the pixel array region and :; Dai-Lei, 14 = Jlr said T / »a said / ㈢ 上 弟-an electrically conductive amorphous silicon layer, which is located on the intrinsic non-crystalline layer. And, a transparent electrode, which is filled in the dielectric hole, and is covered with a second electrically amorphous silicon layer and a part of the dielectric layer. Embodiment: The present invention relates to a method for manufacturing an elevated PIN film photodiode and its structure. Please refer to FIGS. 5 to 丨 丨, which are cross-sectional views of a photodiode manufacturing process according to a preferred embodiment of the present invention. First, as shown in FIG. 5, a substrate 200 is provided. The substrate 200 may be formed with components (not shown) necessary for constituting a photosensitive element, such as a transistor and an active region, and since the photosensitive diode in the present invention is an overhead type, the substrate 200 It also includes an interconnect structure (not shown) located on the transistor or active area. In addition, the substrate 200 can be further divided into a ground pad region 17 with different functions, a pixel array region 180, and a special application integrated circuit region 19, and so on. Next, a metal layer 21 is formed to cover the substrate 200. This step can be achieved by, for example, a deposition method, and the material of the metal layer 2 can be aluminum. Next, for example, an amorphous silicon layer 22 is formed by a deposition method (in this embodiment, the N + type amorphous silicon layer 220 is used as an example; the amorphous silicon layer 22 may also be a p + type) to cover the metal layer 210. Then ’sequentially perform the lithography and etching steps to remove the N + type amorphous silicon layer 22 located in the ground pad region 170 and the special application integrated circuit region 19 portion.

Page 12 594983 V. Description of the invention (7) ----- To form the N + type amorphous stone layer 222 as shown in Fig. 6, and expose a part of the metal layer 210. The purpose of this step is to define the previously mentioned column area 180. Then, lithography and etching steps are sequentially performed to remove a part of the oblique non-silicon layer 222 and the metal layer 210, so as to form the gaps 230, 232, 234, and 230 as shown in FIG. 7. And 236, and the metal layer and the amorphous silicon layer are changed into metal layers 212, 214, 216, 218, and 219, and N + type non-Japanese crystal silicon layers 224, 226, and 228, respectively. At this time, a part of the substrate 200 located at the bottom of the gaps 230, 232, 234, and 236 is in an exposed state. In addition, the metal layer 2 i 4 and the N + type amorphous silicon layer 224 together form a pixel back electrode. Similarly, the metal layer 216 and the N + type amorphous silicon layer 226 together form the back electrode of another pixel / and the metal layer 218 and the N + type amorphous silicon layer 228 form the back electrode of the third pixel together. 'Then, as shown in FIG. 8, a dielectric layer 24 is formed through the following process. First, a dielectric layer 240 is formed, for example, by a deposition method to cover all the elements in FIG. Then, for example, the dielectric layer 240 is polished to a predetermined height by a chemical mechanical polishing method (C h e m i c a 1 M e c h a n i c a 1 Polishing; CMP) (as illustrated in FIG. 8). Next, the lithography and etching processes are performed in order to define and remove a part of the dielectric layer 240, and become a structure as shown in FIG. At this time, the dielectric layer 240 has dielectric layer holes 250, 252, 254, and 256. Among them, the dielectric layer hole 250 penetrates the dielectric layer 240 located on the ground pad region 170 to expose a part of the metal layer 212, and the dielectric layer holes 252, 254, and 256 respectively penetrate the N + type amorphous silicon layer. The dielectric layers 240 on 224, 226, and 228 expose portions of the N + type amorphous silicon layers 224, 226, and 228.

Page 13 594983 V. Description of the invention (8), == If the amorphous silicon layer 260 is formed by a deposition method (for example, an amorphous silicon semiconductor layer containing no foreign impurities, that is, an intrinsic amorphous silicon layer) ^ f The dielectric layer holes 25, 252, 254, and 256 are filled. In other words, the material of the amorphous silicon layer 26 is pure silicon. Therefore, the electrical properties of such an intrinsic amorphous silicon layer 2 60 reflect its own characteristics. On the contrary, extrinsic semiconductor & is just the opposite; because it contains a considerable amount of foreign impurities, the electrical properties of the extrinsic semiconductor will not fully reflect its own characteristics, such as the N + amorphous Shi Xi layer and p + type extrinsic semiconductor which will be mentioned later. For example, the deposition method 270 (amorphous silicon layer 27 () in this embodiment is an example of a p + type. However, when the amorphous silicon layer 220 is a p + type, the amorphous silicon layer 27 may be N +. Type) covering the intrinsic amorphous silicon layer 2 6 0. Then, for example, the lithography / etching process is used to remove the P + -type amorphous silicon layer 270 and the intrinsic amorphous silicon layer 260 located on the ground pad region 710 and the special application integrated circuit region 190 to form as shown in FIG. 9. The p + -type amorphous silicon layer 272 and the intrinsic amorphous stone layer 262 are shown, and the metal layer 212 in the dielectric layer 240 and the dielectric layer hole 250 is exposed. Then, as shown in FIG. 10, For example, processes such as deposition, lithography, and etching are sequentially performed to form a transparent electrode 280 to cover the P + -type amorphous silicon layer 272 and a portion of the dielectric layer 240, and fill the dielectric layer hole 250. In addition, the material of the transparent electrode 280 is, for example, indium tin oxide (ITO) or other materials having similar properties. Then, for example, a passivation layer 290 shown in FIG. 1 丨 is formed by the following process. First, a protective layer is formed, for example, by a deposition method

Page 14 594983 V. Description of the invention (9) 290 covers all the elements in Figure 10. Among them, the protective layer 29 can be composed of the first protective layer and the second protective layer (not shown in green) of Sequential Stack®. That is, the first protective layer is located on all the elements in the 10th figure, and the second protective layer is located on the second and seventh protective layers. In addition, the material of the first protective layer is, for example, two oxides, and the material of the second protective layer is, for example, nitride. Then, for example, the lithography / etching process is used to remove the protective layer 29o on the pixel array region 180, so as to form a photosensitive window garment 310 to receive an external light source and expose the transparent electrode 28. In addition, this lithography / etching process can simultaneously remove a part of the protective layer and a part of the dielectric layer 240 on the ground pad area 700, thereby forming a pad hole 300 and exposing the metal layer θ212. Therefore, the part of the transparent electrode 28 filled in the dielectric layer hole 25 can be electrically connected to the crystal ball in the pad hole 300 through the metal layer 212 on the ground pad region 170 (not shown). . In the absence, 'the present invention has the following features. Firstly, by using the manufacturing method of the sensing monopole of the present invention, the photodiode can be formed into two different regions 11 as a pixel array region having an N + type amorphous silicon layer; the other is not ::: ί 非Other areas of the crystalline silicon layer. Secondly, the back electrode (that is, the metal layer with a non-crystalline amorphous structure) can be connected to the intrinsic connection through a large-area dielectric layer hole; after:: \ 电; Gold array area through ΐ :: crystal ball formed in the hole of the fresh 塾. In addition, the “pixels are formed to form the protective layer and are removed by the process”, so as to receive the external light. point. 1: 4 According to the above features of the present invention, the present invention can have the following advantages without contacting the metal layer of the back electrode and the intrinsic amorphous silicon layer in the present invention. Therefore, there is no metal layer of the back electrode and Intrinsic amorphous silicon layer

594983 V. Description of the invention (10) It can reduce vertical leakage current. Secondly, the use of this invention can produce high-sensitivity image perception with higher reliability:;. Using one of the preferred embodiments of Xin Zhenyue (ie, Figures 5 to 11), ... crystal modification 4 series = = image:: back;: layer; 14 and J-based layer 216 and material amorphous The silicon layer 226 together forms the back electrical element of another pixel; i: Layer 2 and the N + type amorphous stone layer m together form a third imager governor 2 to form a pixel array region 18 The number of pixels of 〇 can be four. Like Xin: 埴: The pixel array area 180 is composed of four pixels, then this one :: is separated by a dielectric layer filled in three gaps. For another example: the pixel array region 180 is composed of two pixels, and the two =-gap dielectric layers are separated. The extreme image and matrix are composed of Γ / Λ " " pixels, and of course, there is no dielectric layer separating the two pixels. It is worth mentioning that, in addition to the N + type layer, the present invention can be applied to an elevated piN thin film that is based on an N + type amorphous stone layer and a non- = layer on an amorphous silicon layer. Outside the diode, even if the positions of the N + -type amorphous crystal and the P + -type amorphous stone are reversed, they still belong to the protection scope of the present application. That is, the p + -type amorphous silicon layer in the present invention may be located on the bottom layer of the photo-polarization structure of the PIN film, the intrinsic amorphous silicon layer is located on the type amorphous silicon layer, and the N + -type amorphous silicon layer is located on the intrinsic Leaked on the amorphous silicon layer. For example, those skilled in the art understand that the above description is only a comparative example of the present invention 'and is not intended to limit the scope of patent application of the present invention; where page 16 594983

Page 17

594983 Brief description of the drawings Figures 1 to 4 are cross-sectional views showing the manufacturing process of a conventional elevated film photosensitive diode; and Figures 5 to 11 are photosensitive 2 diagrams illustrating a preferred embodiment of the present invention. Sectional view of the polar body process. Comparative description of drawing numbers: 100 substrate 102 metal layer 104N + type amorphous silicon layer 1 0 5 back electrode I 0 6 intrinsic amorphous silicon layer 108P + type amorphous silicon layer 109 width II 0 transparent electrode 1 7 0 ground pad area 180 pixel array area 190 special application integrated circuit area 2 0 0 substrate 210 metal layer 212 metal layer 214 metal layer 216 metal layer 218 metal layer

Page 594983 Brief description of the diagram 2 1 9 Metal layer 2 2 〇 N + type amorphous silicon layer 2 2 2 N + type amorphous silicon layer 2 2 4 N + type amorphous silicon layer 2 2 6 N + type non Crystalline silicon layer 228N + type amorphous silicon layer 2 30 gap 2 32 gap 234 gap 2 36 gap 2 4 0 dielectric layer 2 5 0 dielectric layer hole 2 5 2 dielectric layer hole 2 5 4 dielectric layer hole 2 5 6 Dielectric layer holes 2 6 0 Intrinsic amorphous silicon layer 262 Intrinsic amorphous silicon layer 270P + type amorphous silicon layer 272P + type amorphous silicon layer 2 8 0 Transparent electrode 2 9 0 Protective layer 3 0 0 Pad hole 3 1 0 Photosensitive window

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Claims (1)

594983 6. The method of applying for a patent includes at least: a pixel array area, a substrate provided with a specific 1 · photodiode system, including at least a grounding pad area, and a special application product Circuit (AppllcatiOn Integrated Circuit; ASIC) region; forming a metal layer to cover the substrate; forming a first amorphous silicon layer to cover the metal layer of the pixel array region; forming a dielectric layer having a plurality of first openings Covering the first amorphous stone layer and the metal layer, and the first openings are located on the ground pad region and the pixel array region, thereby exposing the metal layer and the first amorphous stone layer respectively; Forming an amorphous silicon layer covering and filling the dielectric layer and the first openings in the pixel array region; θ forming a third amorphous silicon layer covering the second amorphous silicon layer; and forming A transparent electrode covers the second amorphous stone layer and the dielectric layer, and fills the first openings located in the ground pad region. 2. The method for manufacturing a photodiode as described in item 1 of the scope of patent application, wherein the step of forming the first amorphous silicon layer and the step of forming the dielectric layer further include defining the first amorphous silicon layer. The silicon layer and the metal layer form a plurality of openings on the ground region, the pixel array region, and the special application integrated circuit region, and the substrate is exposed. 3. The method for manufacturing a photodiode according to item 1 of the scope of the patent application, wherein the second amorphous silicon layer is an intrinsic amorphous silicon layer. Page 20 594983 6. Scope of patent application 4. The method for manufacturing a photodiode as described in item 1 of the scope of patent application, wherein the first amorphous silicon layer and the third amorphous silicon layer have opposite electrical properties. 5. The method of manufacturing a photodiode according to item 4 of the scope of the patent application, wherein the first amorphous silicon layer is an N + type or a P + type amorphous silicon layer. 6. The method for manufacturing a photodiode according to item 5 of the scope of the patent application, wherein the third amorphous silicon layer is a P + -type or N + -type amorphous silicon layer. 7. The method for manufacturing a photodiode as described in item 1 of the scope of patent application, wherein the material of the transparent electrode is indium tin oxide (IT0). 8. The method for manufacturing a photodiode according to item 1 of the scope of patent application, wherein after forming the transparent electrode, the method further includes at least: forming a protective layer covering the transparent electrode and the dielectric layer; and forming a photoresist The window exposes the transparent electrode on the cover layer of the pixel array area, and forms a pad hole on the cover layer and the dielectric layer of the ground pad area, thereby exposing the metal layer, which is filled with the The transparent electrodes in the first openings are electrically connected to a crystal ball subsequently formed in the pad hole through the metal layer on the ground pad region. 9. The method for manufacturing a photodiode according to item 8 of the scope of the patent application, wherein the protective layer further includes at least a first protective layer and a second protective layer stacked. Page 21 594983 VI. Patent application scope 10 · The manufacturer of the photodiode as described in item 9 of the patent application scope, wherein the material of the first protective layer is an oxide and the material of the second protective layer: a legal compound . Ahbe is nitrogen 11. A photodiode material, the substrate provides a base area, and a special application to form a gold formation a first removal located in the 'amorphous second removal portion a first gold shape is formed in the special application product formation A “amorphous” ground is broken, the pixel array is formed by an amorphous second, and a first layer is formed to cover the amorphous second layer and the ground pad layer, so that the first non-metal layer pattern bit is exposed. The pixel array region and the body circuit region are covered with an electrical layer over the storm layer, and the layer on the dielectric region is on the dielectric region; the two amorphous stone layer dielectric layer; the manufacturing of the two amorphous stone layer is at least an inclusion body Electrical base material; a method for covering the area and the exposed chipped layer on the exposed and exposed electrical layer and the dielectric layer, including at least one ground bonding circuit area, including: a pad area, a pixel Array metal layer; special application integrated circuit metal layer; and a part of the metal layer on the recording area, a first and a third metal layer are exposed to the substrate; the substrate and the metal layer further include a first An opening and plural 'To expose the second on the gold area to open the first' to form a metal layer pattern located in the special, and the first through the mouth through the first layer and the second fill in the first opening and the second The opening is covered with the second amorphous stone layer; Page 22 594983 VI. Patent application scope Remove the third amorphous stone layer and the second amorphous silicon layer on the ground pad area and the special application integrated circuit area to expose the dielectric layer And the metal layer in the first opening; and forming a transparent electrode to fill the first opening and covering the third amorphous silicon layer and the dielectric layer. 12. The method for manufacturing a photodiode as described in item η of the patent claim, wherein the material of the metal layer is aluminum. 13. The method for manufacturing a photodiode according to item 丨 丨 in the scope of the patent application, wherein the material of the transparent electrode is indium tin oxide (IT 0). 14. The method for manufacturing a photodiode according to item 11 of the scope of patent application, wherein after forming the transparent electrode, the method further includes: forming a protective layer covering the transparent electrode and the dielectric layer; and forming a photoresist The window exposes the transparent electrode on the cover layer in the pixel array area, and forms a pad hole in the cover layer and the dielectric layer in the ground pad area to expose the metal layer, which is filled with the The transparent electrode in the first opening is electrically connected to a crystal ball subsequently formed in the pad hole through the metal layer on the ground pad region. 15. The method for manufacturing a photodiode according to item 14 of the scope of patent application, wherein the protective layer further includes at least a first protective layer and a second protective layer, and the second protective layer is located on the first On the cover. Page 23 594983 6. Scope of patent application 16. The manufacturing method of the photodiode described in item 15 of the scope of patent application, wherein the material of the first protective layer is an oxide. 17. The method for manufacturing a photodiode as described in item 15 of the scope of patent application, wherein the material of the second protective layer is nitride. 18. The method for manufacturing a photodiode according to item 11 of the scope of the patent application, wherein the second amorphous silicon layer is an intrinsic amorphous silicon layer. 19. The method of manufacturing a photodiode according to item 11 of the scope of the patent application, wherein the first amorphous silicon layer and the third amorphous silicon layer have different electrical properties. 20. A photodiode structure including at least: a substrate having a ground pad region, a pixel array region, and a special application integrated circuit region; a metal layer covering the substrate; a first An amorphous silicon layer covers the metal layer in the pixel array region; a dielectric layer having a plurality of first openings covers the first amorphous silicon layer and the metal layer, and the first openings are located in the ground pad region and A metal layer and the first amorphous silicon layer are respectively exposed on the pixel array region; a second amorphous silicon layer covers and fills the dielectric layer and the first openings in the pixel array region; Page 24 594983 6. Application scope: a third amorphous silicon layer covers the second amorphous silicon layer; and a transparent electrode covers the third amorphous silicon layer and the dielectric layer, and is filled in the ground bonding pad. Into the first openings in the pad area. 21. The structure of the photodiode according to item 20 of the scope of patent application, wherein the metal layer and the first layer are located on the ground pad region, the pixel array region, and the special application integrated circuit region. The amorphous silicon layer further includes a plurality of second openings exposing the substrate; 22. The structure of the photodiode as described in item 20 of the patent application scope, wherein the second amorphous silicon layer is intrinsically non-existent. Crystal silicon layer. 23. The structure of the photodiode according to item 20 of the scope of patent application, wherein the first amorphous silicon layer and the third amorphous silicon layer have opposite electrical properties. 24. The structure of the photodiode according to item 23 of the scope of the patent application, wherein the first amorphous stone layer is an N + -type or P + -type amorphous stone layer. 25. The structure of the photodiode according to item 24 of the scope of the patent application, wherein the third amorphous silicon layer is a P + -type or N + -type amorphous silicon layer. 26. The structure of the photodiode according to item 20 of the scope of the patent application, wherein the material of the transparent electrode is indium tin oxide (I TO). Page 25 594983 6. The structure of the scope of the patent application, 27. The photosensitive diode described in item 20 of the scope of the patent application at least includes: a protective layer having a photosensitive window, which exposes the pixel array area. A transparent electrode, and the protective layer further has a pad hole exposing the metal layer on the ground pad area, so that the transparent two filled in the first openings are located on the ground pad area The metal layer is electrically connected to a crystal ball in the hole. In this welding technique 28, the photodiode in the photodiode described in item 27 of the patent application patent garden further includes at least one of the first protective layer and the first protective layer and the second protective layer. a 2 9. The material of the first protective layer in the photodiode described in item 28 of the Shenyan patent scope is an oxide and the structure of the second protective layer is the same. The quality of the substrate is 30. Kinds of substrates are applied. The integrated layer is located on the special electrical layer. A metal layer pattern is located on the second dielectric inductor. The structure has a circuit covering the element array application diode. At least: a ground pad. Region, a pixel array region, a region; the substrate, wherein the metal layer further includes the ground pad region on the substrate, a second inflammation region region on the substrate, and a third metal region The layered pattern integrated circuit area is on the substrate; the layered pattern is a special metal silicon layer, which is located in the pixel array area of the metal non-orifice 7 / day 1 W not dry 1! Hai gold, covering part of the substrate, part Of the metal layer, on the layer, and part Page 26 594983 VI. The patented σHildi electric amorphous stone layer, wherein the dielectric layer in the ground region has a dielectric hole; 9 an intrinsic amorphous silicon layer is located in the On the dielectric layer and the electrically amorphous layer in the pixel array region; an amorphous-second electrically amorphous silicon layer on the intrinsic amorphous silicon layer; and a transparent electrode filled in the dielectric The electric layer hole covers the second electric stone layer and a part of the dielectric layer. 3 1 · The structure of the photodiode according to item 30 of the scope of patent application, wherein the material of the metal layer is aluminum. 3 2 · The structure of the photodiode described in item 30 of the scope of patent application, wherein the material of the transparent electrode is ITO. 33. The structure of the photodiode according to item 30 of the scope of the patent application, which further includes a protective layer having a photosensitive window, exposing the transparent electrode in the pixel array region. 34. The structure of the photodiode according to item 33 of the scope of the patent application, wherein the protective layer and the dielectric layer of the ground pad region further have a pad hole, and the dielectric is filled in. The transparent electrode in the layer hole is electrically connected to a crystal ball formed in the welding hole through the metal layer located in the ground pad region. 3 5. The structure of the photodiode as described in item 33 of the scope of patent application, which Page 27 594983 6. In the scope of patent application, the protective layer further includes at least a first protective layer and a second protective layer stacked, and the second protective layer is located on the first protective layer. 36. The structure of the photodiode according to item 35 of the scope of patent application, wherein the material of the first protective layer is an oxide. 37. The structure of the photodiode according to item 36 of the scope of the patent application, wherein the material of the second protective layer is nitride. Page 28