KR100936102B1 - Image Sensor and Method for Manufacturing Thereof - Google Patents

Abstract

An image sensor according to an embodiment includes a semiconductor substrate including a pixel region and a peripheral circuit region; An interlayer insulating film including a metal wiring formed on the semiconductor substrate; An isolation layer formed on the interlayer insulating film; An upper electrode connected to the metal wiring and disposed on the device isolation layer; And a photodiode disposed on the interlayer insulating film of the pixel region, wherein the metal wiring includes the metal film pattern and the plug, and the widths of the plugs formed in the pixel region and the peripheral circuit region are all the same. do.

Image sensor, photodiode,

Description

Image Sensor and Method for Manufacturing Thereof}

In an embodiment, an image sensor and a method of manufacturing the same are disclosed.

The image sensor is a semiconductor device that converts an optical image into an electrical signal, and includes a charge coupled device (CCD) image sensor and a complementary metal oxide silicon (CMOS) image sensor (CIS). do.

The CMOS image sensor implements an image by sequentially detecting an electrical signal of each unit pixel by a switching method by forming a photodiode and a MOS transistor in the unit pixel.

The CMOS image sensor is a structure in which a photo diode area for receiving a light signal and converting it into an electric signal and a transistor area for processing the electric signal are horizontally disposed.

According to the horizontal CMOS image sensor, a photodiode and a transistor are formed adjacent to each other horizontally on a substrate.

Accordingly, an additional area for photodiode formation is required, thereby reducing the fill factor area and limiting the possibility of resolution.

Embodiments provide an image sensor capable of providing vertical integration of a transistor circuit and a photodiode and a method of manufacturing the same.

In addition, the embodiment provides an image sensor and a method of manufacturing the same that can be improved together with the resolution (Resolution) and sensor sensitivity (sensitivity).

In addition, the embodiment is to provide an image sensor and a manufacturing method thereof that can prevent the defect in the photodiode while employing a vertical photodiode.

An image sensor according to an embodiment includes a semiconductor substrate including a pixel region and a peripheral circuit region; An interlayer insulating film including a metal wiring formed on the semiconductor substrate; An isolation layer formed on the interlayer insulating film; An upper electrode connected to the metal wiring and disposed on the device isolation layer; And a photodiode disposed on the interlayer insulating film of the pixel region, wherein the metal wiring includes the metal film pattern and the plug, and the widths of the plugs formed in the pixel region and the peripheral circuit region are all the same. do.

A method of manufacturing an image sensor according to an embodiment includes forming a metal wiring and an interlayer insulating film including a metal film pattern and a plug on a first substrate including a pixel area and a peripheral circuit area; Forming a second substrate comprising a photodiode; Bonding a second substrate including the photodiode on the interlayer dielectric layer; Removing the second substrate such that photodiodes remain on the first substrate; Forming an isolation layer on the photodiode; And forming an upper electrode on the device isolation layer, wherein the widths of the plugs formed in the pixel area and the peripheral circuit area are all the same.

The image sensor and the method of manufacturing the same according to the embodiment can form a narrow width of the plug exposed on the interlayer insulating film of the peripheral circuit region, thereby preventing dishing of the plug, thereby improving contact characteristics with the upper electrode. have.

In addition, when the device isolation layer formed between the plug and the upper electrode is formed, a width of the via hole formed on the plug is sufficiently wide to ensure sufficient contact margin between the upper electrode and the plug. Vertical integration of circuitry and photodiodes can be provided.

In addition, according to the embodiment, the fill factor can be approached to 100% by vertical integration of the transistor circuit and the photodiode.

Further, according to the embodiment, it is possible to provide higher sensitivity at the same pixel size by vertical integration than in the prior art.

In addition, according to the embodiment it is possible to reduce the process cost for the same resolution (Resolution) than the prior art.

In addition, according to the exemplary embodiment, each unit pixel may implement a more complicated circuit without reducing the sensitivity.

In addition, the additional on-chip circuitry that can be integrated by the embodiment can increase the performance of the image sensor and further reduce the size and manufacturing cost of the device.

An image sensor and a method of manufacturing the same according to an embodiment will be described in detail with reference to the accompanying drawings.

In the description of the embodiments, where described as being formed "on / over" of each layer, the on / over may be directly or through another layer ( indirectly) includes everything formed.

In the drawings, the thickness or size of each layer is exaggerated, omitted, or schematically illustrated for convenience and clarity of description. In addition, the size of each component does not necessarily reflect the actual size.

10 is a cross-sectional view illustrating an image sensor according to an embodiment.

As shown in FIG. 11, an image sensor according to an embodiment includes a first substrate 10 including a pixel area A and a peripheral circuit area B; An interlayer insulating film 20 including a metal wiring 30 formed on the first substrate 10; An isolation layer 250 formed on the interlayer insulating film 20; An upper electrode 260 connected to the metal wiring 30 and disposed on the device isolation layer 250; And a photodiode 200 disposed on the interlayer insulating film 20 in the pixel region A.

The metal wiring 30 includes the metal layer pattern 14 and the plug 18, and is formed in the width Q and the peripheral circuit region B of the plug 18 formed in the pixel region A. FIG. The widths P of the formed plugs 18 are all the same.

The device isolation layer 250 includes a via hole 257, and the upper electrode 260 is electrically connected to the metal wiring 30 formed in the peripheral circuit region B through the via hole 257. Connected.

The width R of the via hole 257 is formed to be wider than the width P of the plug 18.

The photodiode 200 may be formed by doping p-type or n-type impurities to a substrate formed of a single crystal or polycrystal.

The device isolation layer 250 may be formed on the device isolation trench 235 formed on the photodiode 200 and on the photodiode 200.

The upper electrode 260 may be electrically connected to the photodiode 200 formed in the pixel region A and the metal wiring 30 formed in the peripheral circuit region B.

The first passivation layer 270 and the second passivation layer 280 are disposed on the first substrate 10 including the upper electrode 260.

According to the image sensor according to the embodiment, the photodiode 200 may be formed on the first substrate 10 including the metal wiring 30 to achieve vertical integration of the image sensor.

In addition, the photodiode 200 may be formed inside the crystalline semiconductor to reduce the defect of the photodiode.

In addition, the device isolation layer 250 may be formed on the photodiode 200 to separate the photodiode 200 for each pixel.

A method of manufacturing an image sensor according to an embodiment will be described with reference to FIGS. 1 to 10.

As shown in FIG. 1, the first insulating layer 22 and the second metal wiring 14 on which the first metal wiring 12 is formed are formed on the first substrate 10.

The first substrate 10 includes a pixel area A and a peripheral circuit area B. In the pixel region A, a transistor circuit may be formed for each unit pixel in order to convert photoelectric charges received by being connected to a photodiode to be described later into an electric signal.

For example, the CMOS circuit may be any one of 3Tr, 4Tr, and 5Tr. In the peripheral circuit region B, a transistor circuit for realizing an image by sequentially detecting an electrical signal of each unit pixel of the pixel region A may be formed.

The second metal wire 14 may be formed by forming a first metal film on the first insulating layer 22 and then patterning the second metal wire 14.

The second metal wire 14 may be a final metal wire positioned at the top of the interlayer insulating layer. The first metal wire 12 and the second metal wire 14 may include metal, alloy, or salicide. It may be formed of various conductive materials, namely aluminum, copper, cobalt or tungsten.

The first insulating layer 22 may be formed of an oxide film or a nitride film.

As shown in FIG. 2, the second insulating layer 24 including the first via hole 16 and the second via hole 17 is formed on the first insulating layer 22 on which the second metal wiring 14 is formed. To form.

The second insulating layer 24 may be formed of an oxide film or a nitride film.

The first via hole 16 is formed on the first metal wiring 14 formed in the pixel region A, and the second via hole 17 is formed on the first metal wiring formed in the peripheral circuit region B. 14) is formed on.

In this case, the width Q of the first via hole 16 and the width P of the second via hole 17 may be the same.

As shown in FIG. 3, the first via hole 16 and the second via hole 17 are filled with a metal material to form a plug 18 connected to the second metal wire 14.

The plug 18 may be formed by forming a metal material on the second insulating layer 24 including the first via hole 16 and the second via hole 17 and performing a planarization process.

In this case, when the width P of the second via hole 17 formed in the peripheral circuit region B is wide, a dishing phenomenon occurs on the surface of the plug 18 during the planarization process. The middle area of (18) is pitted.

This may cause a destabilization of the contact with the upper wiring to be formed later. However, in the present embodiment, the width P of the second via hole 17 formed in the peripheral circuit region B is the pixel region A. FIG. It is formed to be equal to the width Q of the first via hole 16 formed in the (), the dishing phenomenon does not occur.

The plug 18 may be exposed to the surface of the interlayer insulating layer 20 by the planarization process.

As a result, an interlayer insulating film 20 on which the metal wiring 30 is formed is formed on the first substrate 10 to be connected to the power line or the signal line.

The metal wire 30 serves to transfer electrons generated from the photodiode to the lower CMOS circuit. Although not shown, the metal wire 30 may be connected to a region doped with impurities formed under the first substrate 10.

As shown in FIG. 4, a photodiode 200 is formed on the second substrate 20.

The second substrate 20 may be a single crystal or polycrystalline silicon substrate, and may be a substrate doped with p-type impurities or n-type impurities. In an embodiment, the second substrate 20 may be a p-type substrate. In addition, the first substrate 10 and the second substrate 20 may be formed in the same size. In addition, an epitaxial layer may be formed on the second substrate 20.

The photodiode 200 is formed in the second substrate 20. The photodiode 200 may include an n-type impurity region and a p-type impurity region. The n-type impurity and the p-type impurity region are formed to be in contact with each other to form a photodiode 200 having a PN junction.

Although not shown, a hydrogen ion layer may be formed between the second substrate 20 and the photodiode 200. The hydrogen ion layer is to separate the second substrate 20 and the photodiode 200 and may be formed by ion implantation of hydrogen ions.

Although the photodiode 200 is formed by bonding the second substrate 20 on which the photodiode 200 is formed on the first substrate 10, the photodiode 200 is not limited thereto. ) Is formed by stacking an n-type amorphous silicon layer, an intrinsic amorphous silicon layer and a p-type amorphous silicon layer on the first substrate 10. Can be.

Subsequently, as shown in FIG. 5, the photodiode 200 is formed on the first substrate 10, and the device isolation pattern 240 is formed on the photodiode 200.

The second substrate 20 includes the first substrate 10 and the second substrate 20 including the photodiode 200, so that the photodiode 200 remains on the first substrate 10. It can be formed by removing the substrate 20.

The first substrate 10 and the second substrate 20 may be combined by a bonding process.

Specifically, the surface of the photodiode 200 formed on the second substrate 20 is positioned on the interlayer insulating layer 20, which is the surface of the first substrate 10, and then bonded to bond to the first substrate. 10 and the second substrate 20 may be combined.

When the first substrate 10 and the second substrate 20 are coupled to each other, the metal wiring 30 of the interlayer insulating layer 20 and the photodiode 20 are electrically connected to each other.

When the second substrate 20 is removed, the photodiode 200 remains on the first substrate 10.

Therefore, since the interlayer insulating film 20 and the photodiode 200 remain on the first substrate 10, the first substrate 10 and the photodiode 200 are vertically integrated.

Since a hydrogen ion layer is formed between the second substrate 20 and the photodiode 200, the second substrate 20 and the photodiode 200 are separated along a portion where the hydrogen ion layer is formed.

The device isolation pattern 240 forms an insulating layer such as an oxide layer on the photodiode 200. The insulating layer 240 is patterned to be separated by unit pixels to form an isolation pattern 240 for selectively exposing the photodiode 200. In addition, the device isolation pattern 240 may expose the photodiode 200 on the peripheral circuit region B. FIG.

Subsequently, as shown in FIG. 6, a device isolation trench is formed in the photodiode 200.

The device isolation trench may be formed by etching the photodiode 200 using the device isolation pattern 250 as an etching mask.

Then, the photodiode 200 on the pixel area A may be connected to the lower wiring 30 separated by the device isolation trench and separated by unit pixel.

In addition, the photodiode 200 of the peripheral circuit region B is removed to expose the plug connected to the interlayer insulating layer 110 and the lower wiring 30 on the peripheral circuit region B.

Subsequently, as shown in FIG. 7, the device isolation layer 250 is formed on the first substrate 10 including the device isolation trench.

The device isolation layer 250 may be formed by depositing an insulating layer such as an oxide film on the first substrate 10. The device isolation layer 250 is formed on the first substrate 10 while filling the inside of the device isolation trench, so that the photodiode 200 may be separated by unit pixels.

In addition, the device isolation layer 250 is formed on the entire upper surface of the first substrate 10, thereby forming on the surface of the photodiode 200 and the interlayer insulating film 20 of the peripheral circuit region (B). To protect the device.

As shown in FIG. 8, first and second via holes 255 and 257 are formed in the device isolation layer 250.

That is, the first via hole 255 exposes a part of the surface of the photodiode 200, and the second via hole 257 connects the plug 18 connected to the lower wiring 30 of the peripheral circuit region B. It is formed to expose.

In this case, the width R of the second via hole 257 is formed to be wider than the width P of the plug 18 connected to the lower wiring 30 of the peripheral circuit region B.

This is to secure a margin of contact between the upper electrode to be formed on the plug 18 and the plug 18 formed below.

Subsequently, as shown in FIG. 9, an upper electrode 260 including an exposed portion 265 is formed on the device isolation layer 250 including the first and second via holes 255 and 257.

The upper electrode 260 may be formed by depositing a conductive material on the device isolation layer 250 including the first and second via holes 255 and 257. For example, the upper electrode 260 may be formed of a conductive material such as titanium, aluminum, copper, cobalt, and tungsten.

The upper electrode 260 may be electrically connected to the photodiode 200 through the first via hole 255. In addition, the upper electrode 260 may be electrically connected to the lower wiring 30 of the peripheral circuit region B through the second via hole 257.

At this time, the width P of the plug 18 formed in the lower portion of the peripheral circuit region B is narrowed so that dishing does not occur and the width of the second via hole 257 is reduced. By forming R) wider, contact with the upper electrode 260 is improved.

The exposed part 265 may be formed by patterning the upper electrode 260.

The exposed part 265 may secure the light receiving area of the photodiode 200 by removing the upper electrode 260 on the photodiode formed for each unit pixel.

Subsequently, as shown in FIG. 10, a first passivation layer 270 and a second passivation layer 280 are formed on the first substrate 10 including the exposed portion 265.

The first passivation layer 270 may contact the device isolation layer 250 through the first exposed portion 265. For example, the first protective layer 280 may be formed of an oxide film or a nitride film.

A second passivation layer 280 is formed on the first substrate 10 including the first passivation layer 270. For example, the second protective layer 280 may be formed of a nitride film or an oxide film.

Although not shown, a color filter and a micro lens may be formed on the first protective layer 270 and the second protective layer 280.

The color filters are formed one by one for each pixel to separate colors from incident light, and may be formed in three colors of red, green, and blue.

As described above, the image sensor and the method of manufacturing the same according to the embodiment form a narrow width of the plug exposed on the interlayer insulating film of the peripheral circuit region, thereby preventing dishing of the plug and preventing the plug from being disposed with the upper electrode. The contact characteristic can be improved.

In addition, when the device isolation layer formed between the plug and the upper electrode is formed, a width of the via hole formed on the plug is sufficiently wide to ensure sufficient contact margin between the upper electrode and the plug.

In addition, the photodiode may be formed on the first substrate including the lower interconnection to achieve vertical integration of the image sensor.

In addition, a photodiode may be formed in the crystalline semiconductor layer to reduce the defect of the photodiode.

In addition, the upper electrode may be partially connected to the photodiode to secure a light receiving area of the photodiode.

In addition, a device isolation layer may be formed on the photodiode to separate the photodiode for each pixel unit.

The above-described embodiments are not limited to the above-described embodiments and drawings, and it is common in the technical field to which the present embodiments belong that various changes, modifications, and changes can be made without departing from the technical spirit of the present embodiments. It will be apparent to those who have

1 to 10 are cross-sectional views illustrating a manufacturing process of an image sensor according to an embodiment.

Claims (7)

A semiconductor substrate including a pixel region and a peripheral circuit region; An interlayer insulating film including a metal wiring formed on the semiconductor substrate; A photodiode pattern disposed on the interlayer insulating layer in the pixel area and formed to correspond to a unit pixel; An isolation layer formed over the photodiode pattern, between the photodiode pattern, which is a boundary of unit pixels, and on the interlayer insulating layer of the peripheral circuit region to separate the unit pixels; An upper electrode connected to the metal wiring and disposed on the device isolation layer; A first via hole formed through the device isolation layer in the pixel region; And A second via hole formed through the device isolation layer in the peripheral circuit region; The upper electrode is connected to the photodiode pattern by the first via hole, and is connected to the metal wiring of the peripheral circuit region by the second via hole. The metallization includes a metal layer pattern and a plug, and the widths of the plugs formed in the pixel area and the peripheral circuit area are all the same. And a width of the second via hole is wider than that of the plug. The method of claim 1, And a protective layer formed on the device isolation layer on which the upper electrode is formed, wherein the protective layer is formed of at least two layers. The method of claim 1, And the upper electrode is patterned to expose a portion of the device isolation layer. Forming a metal wiring and an interlayer insulating film including a metal film pattern and a plug on a first substrate including a pixel area and a peripheral circuit area; Forming a second substrate comprising a photodiode; Bonding a second substrate including the photodiode on the interlayer dielectric layer; Removing the second substrate so that the photodiode remains on the first substrate, and forming a photodiode pattern so that the photodiode corresponds to a unit pixel of the pixel area; Forming a device isolation layer including a first via hole and a second via hole between the photodiode pattern, which is a boundary of unit pixels, and on the interlayer insulating layer of the peripheral circuit area to separate the unit pixel and the upper portion of the photodiode pattern. ; And Forming an upper electrode on the device isolation layer; The upper electrode is connected to the photodiode pattern by the first via hole, and is connected to the metal wiring of the peripheral circuit region by the second via hole. The widths of the plugs formed in the pixel area and the peripheral circuit area are all the same, The width of the second via hole is wider than the width of the plug, and when the device isolation layer including the second via hole is formed, a portion of the interlayer insulating film is exposed to the second via hole. . The method of claim 4, wherein Forming the metallization and the interlayer dielectric layer including the metal layer pattern and the plug on the first substrate including the pixel region and the peripheral circuit region may include: Forming a metal film pattern on the first substrate including the pixel area and the peripheral circuit area; Forming an interlayer insulating film on the first substrate including the metal film pattern; Forming a third via hole exposing the metal film pattern on the interlayer insulating film; And Filling the third via hole with a metal material to form a plug electrically connected to the metal film pattern; And the widths of the third via holes formed in the pixel area and the peripheral circuit area are all the same. The method of claim 4, wherein And forming a protective layer on the device isolation layer in which the upper electrode is formed. The method of claim 4, wherein And the upper electrode is patterned to expose a portion of the device isolation layer.

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