KR100997299B1 - Image Sensor and Method for Manufacturing Thereof - Google Patents

Abstract

An image sensor according to an embodiment includes a first substrate including a pixel portion on which a readout circuit is formed and a peripheral portion on which a peripheral circuit is formed; A wiring and an interlayer insulating film formed on the first substrate so as to be connected to the readout circuit and the peripheral circuit; A crystalline semiconductor layer formed on the interlayer insulating film corresponding to the pixel portion; First and second photodiodes formed on the crystalline semiconductor layer and connected to wires by device isolation trenches, respectively; A device isolation layer formed on the crystalline semiconductor layer including the device isolation trench; An upper electrode layer partially connected to the first photodiode through the device isolation layer; An exposed portion formed in the upper electrode layer to selectively expose an upper region of the first photodiode; And a protective layer disposed on the first substrate including the exposed portion.

Image Sensor, Photodiode, Device Separation

Description

Image Sensor and Method for Manufacturing Thereof}

Embodiments relate to an image sensor and a manufacturing method thereof.

An image sensor is a semiconductor device that converts an optical image into an electrical signal, and is classified into a charge coupled device (CCD) image sensor and a complementary metal oxide silicon (CMOS) image sensor (CIS). do.

In the prior art, a photodiode is formed on a substrate by ion implantation. However, as the size of the photodiode gradually decreases for the purpose of increasing the number of pixels without increasing the chip size, the image quality decreases due to the reduction of the area of the light receiver.

In addition, since the stack height is not reduced as much as the area of the light receiving unit is reduced, the number of photons incident on the light receiving unit is also decreased due to diffraction of light called an airy disk.

One alternative to overcome this is to deposit photodiodes with amorphous Si, or read-out circuitry using wafer-to-wafer bonding such as silicon substrates. And photodiodes are formed on the lead-out circuit (hereinafter referred to as "three-dimensional image sensor"). The photodiode and lead-out circuit are connected via a metal line.

According to the prior art, there is a problem that perfect device separation between pixels is not possible.

In addition, in the conventional image sensor, leakage current is generated by peripheral elements such as wiring and temperature, which may cause dark current.

In addition, according to the related art, since both the source and the drain of the both ends of the transfer transistor are doped with a high concentration N-type, charge sharing occurs as shown in FIG. 19. When charge sharing occurs, the sensitivity of the output image is lowered and image errors may occur.

In addition, according to the related art, a dark current is generated between the photodiode and the lead-out circuit and the photocharge is not smoothly moved, and saturation and sensitivity are decreased.

Embodiments provide an image sensor and a method of manufacturing the same, in which element separation between pixels of a photodiode is effective while increasing a fill factor.

In addition, an embodiment is to provide an image sensor and a method of manufacturing the same that can protect the photodiode and peripheral devices while the device is separated from the photodiode.

In addition, an embodiment is to provide an image sensor and a method of manufacturing the dummy pixel is formed that can measure the leakage current (Leakage current).

In addition, the embodiment is to provide an image sensor and a method of manufacturing the same that can increase the charge factor (Charge Sharing) does not occur.

In addition, the embodiment of the present invention provides an image sensor capable of minimizing dark current sources and preventing saturation and degradation of sensitivity by creating a smooth movement path of photo charge between the photodiode and the lead-out circuit. To provide a manufacturing method.

An image sensor according to an embodiment includes a first substrate including a pixel portion on which a readout circuit is formed and a peripheral portion on which a peripheral circuit is formed; A wiring and an interlayer insulating film formed on the first substrate so as to be connected to the readout circuit and the peripheral circuit; A crystalline semiconductor layer formed on the interlayer insulating film corresponding to the pixel portion; First and second photodiodes formed on the crystalline semiconductor layer and connected to wires by device isolation trenches, respectively; A device isolation layer formed on the crystalline semiconductor layer including the device isolation trench; An upper electrode layer partially connected to the first photodiode through the device isolation layer; An exposed portion formed in the upper electrode layer to selectively expose an upper region of the first photodiode; And a protective layer disposed on the first substrate including the exposed portion.

In another embodiment, a method of manufacturing an image sensor includes: forming a pixel part including a readout circuit and a peripheral part including a peripheral circuit on a first substrate; Forming a wiring and an interlayer insulating film on the first substrate and connected to the readout circuit and the peripheral circuit; Forming a second substrate comprising a crystalline semiconductor layer; Forming a photodiode layer on the crystalline semiconductor layer; Bonding a second substrate including the first substrate and the photodiode layer; Removing a portion of the second substrate to expose the photodiode layer on the first substrate; Forming a device isolation trench in the crystalline semiconductor layer to form a first photodiode and a second photodiode respectively connected to a wiring; Forming an isolation layer on the crystalline semiconductor layer including the first and second photodiodes; Forming an upper electrode layer on the device isolation layer to be partially connected to the first photodiode; Forming an exposed portion by removing a portion of the upper electrode layer to selectively expose an upper region of the first photodiode; And forming a protective layer on the interlayer insulating layer including the exposed portion.

The embodiment is to provide an image sensor and a method of manufacturing the same that can improve the sensitivity of the photodiode while increasing the fill factor (fill factor).

In addition, the embodiment includes a main pixel electrically connected to the upper wiring to perform a substantial operation, and a dummy pixel not connected to the upper wiring. The dummy pixel may be used as a reference pixel to measure the leakage current of the main pixel, thereby improving performance of the device.

In addition, according to the embodiment, the device may be designed such that there is a potential difference between the source and the drain across the transfer transistor Tx, thereby enabling full dumping of the photo charge.

In addition, according to the embodiment, the charge connection region is formed between the photodiode and the lead-out circuit to create a smooth movement path of the photo charge, thereby minimizing the dark current source, and reducing saturation and sensitivity. You can prevent it.

An image sensor and a method of manufacturing the same according to an embodiment will be described in detail with reference to the accompanying drawings. In the description of the embodiments, where it is described as being formed "on / under" of each layer, it is understood that the phase is formed directly or indirectly through another layer. It includes everything.

The embodiment is not limited to the CMOS image sensor, and may be applied to all image sensors requiring a photodiode.

(First embodiment)

16 is a cross-sectional view illustrating an image sensor according to an embodiment.

The image sensor according to the embodiment includes a first substrate 100 including a pixel portion A on which the readout circuit 120 is formed and a peripheral portion B on which the peripheral circuit is formed; Wirings 150 and 150a and an interlayer insulating layer 160 formed on the first substrate 100 so as to be connected to the lead-out circuit 120 and the peripheral circuits; A crystalline semiconductor layer 200 formed on the interlayer insulating layer 160 corresponding to the pixel portion A; A first photodiode 205 and a second photodiode 205a formed in the crystalline semiconductor layer 200 and separated by unit pixels by device isolation trenches 235 and connected to the wirings 150 and 150a, respectively; A device isolation layer 250 formed on the crystalline semiconductor layer 200 including the device isolation trench 235; An upper electrode layer 260 penetrating through the device isolation layer 250 and partially connected to the first photodiode 205; An exposed portion 265 formed in the upper electrode layer 260 to selectively expose an upper region of the first photodiode 205; And a protective layer 270 formed on the interlayer insulating layer 160 including the exposed portion 265.

The first photodiode 205 is a main pixel electrically connected to the upper electrode layer 260 through a first via hole 255 to perform a substantial operation. The second photodiode 205a is a dummy pixel that is not electrically connected to the upper electrode layer 260. Since the second photodiode 205a used as the dummy pixel can exclude the leakage factor of the upper electrode layer 260, the second photodiode 205a can be used as a reference pixel for measuring an accurate liquid current. For example, the second photodiode 205a may be an edge region of the chip.

The first passivation layer 270 and the second passivation layer 280 are disposed on the first substrate 100 including the upper electrode layer 260. The first passivation layer 270 may be formed on an upper surface of the lower device isolation layer 250 through the first exposed portion 265 of the upper electrode layer 260.

An isolation layer 250 is formed on the crystalline semiconductor layer 200 to separate the photodiode 205 for each pixel.

In addition, a first passivation layer 270 and a second passivation layer 280 are formed on the interlayer insulating layer 160 including the crystalline semiconductor layer 200 to form the wirings of the photodiode 205 and the peripheral portion B. 150) can be protected.

Unexplained reference numerals among the reference numerals of FIG. 16 will be described below in the manufacturing method.

Hereinafter, a manufacturing method of an image sensor according to an embodiment will be described with reference to FIGS. 1 to 16.

Referring to FIG. 1, a readout circuit and wirings 150 and 150a are formed in the pixel portion A of the first substrate 100.

The first substrate 100 may be a single crystal or polycrystalline silicon substrate, and may be a substrate doped with p-type impurities or n-type impurities. An isolation region 110 is formed on the first substrate 100 to define an active region. A readout circuit 120 including transistors for each unit pixel is formed in the active region.

Referring to FIG. 2, the readout circuit 120 and the wiring 150 will be described in detail.

The readout circuit 120 may include a transfer transistor (Tx) 121, a reset transistor (Rx) 123, a drive transistor (Dx) 125, and a select transistor (Sx) 127. . Thereafter, an ion implantation region 130 including a floating diffusion region (FD) 131 and source / drain regions 133, 135, and 137 for each transistor may be formed. Meanwhile, the readout circuit 120 may be any one of 3Tr, 4Tr, or 5Tr.

The forming of the lead-out circuit 120 on the first substrate 100 may include forming an electrical junction region 140 on the first substrate 100 and forming an interconnection on the electrical junction region 140. And forming a first conductivity type connection region 147 connected to 150.

For example, the electrical junction region 140 may be a PN junction 140, but is not limited thereto. For example, the electrical junction region 140 may include a first conductive ion implantation layer 143 and a first conductive ion implantation layer (143) formed on the second conductive well 141 or the second conductive epitaxial layer. 143 may include a second conductivity type ion implantation layer 145. For example, the PN junction 140 may be a P0 145 / N- 143 / P-141 junction as shown in FIG. 2, but is not limited thereto. The first substrate 100 may be conductive in a second conductivity type, but is not limited thereto.

According to the embodiment, the device can be designed such that there is a voltage difference between the source / drain across the transfer transistor Tx, thereby enabling full dumping of the photo charge. Accordingly, as the photo charge generated in the photodiode is dumped into the floating diffusion region, the output image sensitivity may be increased.

That is, in the embodiment, as shown in FIG. 2, the voltage difference between the source / drain across the transfer transistor (Tx) 121 is formed by forming the electric junction region 140 on the first substrate 100 on which the readout circuit 120 is formed. This allows full dumping of the photocharge.

Hereinafter, the dumping structure of the photocharge of the embodiment will be described in detail with reference to FIG. 18.

Unlike the floating diffusion (FD) 131 node, which is an N + function in the embodiment, the P / N / P section 140, which is an electrical junction region 140, does not transmit all of the applied voltage and pinches at a constant voltage. It is off (Pinch-off). This voltage is called a pinning voltage and the pinning voltage depends on the P0 145 and N- (143) doping concentrations.

Specifically, the electrons generated by the photodiode 205 are moved to the PNP caption 140 and are transferred to the FD 131 node when the transfer transistor (Tx) 121 is turned on and converted into voltage.

Since the maximum voltage value of the P0 / N- / P- caption 140 becomes pinning voltage and the maximum voltage value of the node FD 131 becomes Vdd-Rx Vth, as shown in FIG. 18, the potential difference between both ends of the Tx 131 is shown. Due to this, electrons generated from the photodiode 205 on the chip without charge sharing may be fully dumped to the FD 131 node.

That is, in the embodiment, the reason why the P0 / N- / Pwell junction is formed instead of the N + / Pwell junction in the silicon sub, which is the first substrate 100, is P0 / N- / during the 4-Tr APS Reset operation. In Pwell junction, + voltage is applied to N- (143) and ground voltage is applied to P0 (145) and Pwell 141. Will occur. This is called pinning voltage. Therefore, a voltage difference is generated in the source / drain at both ends of the Tx 121, and thus the photocharge is completely dumped from the N-well to the FD through the Tx at the Tx On / Off operation to prevent the charge sharing phenomenon.

Therefore, unlike the case where the photodiode is simply connected by N + junction as in the prior art, the embodiment can avoid problems such as degradation of saturation and degradation of sensitivity.

Next, according to the embodiment, a first conductive connection region 147 is formed between the photodiode 205 and the lead-out circuit 120 to create a smooth moving path for the photo charge, thereby generating a dark current source. Minimize and prevent saturation and degradation.

To this end, the first embodiment may form an n + doped region as the first conductive connection region 147 for ohmic contact on the surface of the P0 / N− / P− junction 140. The N + region 147 may be formed to contact the N− 143 through the P0 145.

Meanwhile, in order to minimize the first conductive connection region 147 from becoming a leakage source, the width of the first conductive connection region 147 may be minimized. To this end, the embodiment may proceed with a plug implant after etching the first metal contact 151a, but is not limited thereto. For example, the first conductive connection region 147 may be formed by forming an ion implantation pattern (not shown) and using the ion implantation mask as an ion implantation mask.

That is, as in the first embodiment, the reason for locally N + doping only to the contact forming part is to facilitate the formation of ohmic contact while minimizing the dark signal. As in the prior art, when N + Doping the entire Tx Source part, the dark signal may increase due to the substrate surface dangling bond.

Next, the interlayer insulating layer 160 may be formed on the first substrate 100, and the wiring 150 may be formed. The wiring 150 may include a first metal contact 151a, a first metal 151, a second metal 152, a third metal 153, and a fourth metal contact 154a, but is not limited thereto. It is not.

The wiring 150 may be formed for each pixel to connect the photodiode 205 and the readout circuit 120 to transmit photocharges of the photodiode 205. When the wire 150 connected to the lead-out circuit 120 is formed, a wire 170 connected to the peripheral portion B may also be formed. The wires 150 and 170 may be formed of various conductive materials including metals, alloys, or silicides.

The wirings 150 and 150a formed in the pixel portion A may be formed for each pixel to transmit the photocharges of the photodiode to the readout circuit 120. For example, the first wiring 150 of the pixel portion A may be connected to a unit pixel performing a substantial operation, and the second wiring 150a may be connected to a dummy pixel. When the third metal 153 of the wiring 150 is formed, a pad 180 may be formed in the peripheral portion B.

Referring to FIG. 3, a second substrate 20 including a crystalline semiconductor layer 200 is prepared. The second substrate 20 may be a single crystal or polycrystalline silicon substrate, and may be a substrate doped with p-type impurities or n-type impurities. The crystalline semiconductor layer 200 may be formed by an epitaxial process on the second substrate 20.

Referring to FIG. 4, a photodiode layer 201 is formed inside the crystalline semiconductor layer 200. The photodiode layer 201 may be formed by ion implanting the N-type first impurity region 220 and the P-type second impurity region 230 into the crystalline semiconductor layer 200. Since the second impurity region 230 is formed on the first impurity region 220, a photodiode layer 201 having a PN junction is formed in the crystalline semiconductor layer 200.

In addition, an ohmic contact layer 210 may be formed by ion implanting a high concentration of N-type impurities under the first impurity region 220.

According to the embodiment, the thickness of the first impurity region 220 is formed to be thicker than the thickness of the second impurity region 230, thereby increasing the charge story capacity. That is, by forming the N-layer thicker to expand the area, it is possible to improve the capacity (capacity) that may contain the optoelectronic.

Although not shown, a hydrogen ion layer may be formed between the crystalline semiconductor layer 200 and the second substrate 20. Alternatively, an insulating layer may be embedded between the crystalline semiconductor layer 220 and the second substrate 20. The insulating layer may then be removed through a wet etching process after the second substrate 20 is removed. The hydrogen ion layer and the insulating layer are for separating the second substrate 20 and the crystalline semiconductor layer 200.

Referring to FIG. 5, a second substrate 20 including the first substrate 100 and the crystalline semiconductor layer 200 is bonded. The surface of the ohmic contact layer 210, which is a lower surface of the second substrate 20, is positioned on the interlayer insulating layer 160, which is a surface of the first substrate 100, and then bonding is performed. Then, the lower wiring 150 and the ohmic contact layer 210 are in an electrically connected state.

Referring to FIG. 6, the second substrate 20 is removed to expose the photodiode layer 201. That is, when the second substrate 20 is removed, the crystalline semiconductor layer 200 of the thin film remains on the first substrate 100. For example, the second substrate 20 may be removed by a blade or CMP process based on a hydrogen ion layer (not shown) or an insulating layer (not shown).

Referring to FIG. 7, an isolation pattern 240 is formed on the crystalline semiconductor layer 200. The device isolation pattern 240 may selectively expose the crystalline semiconductor layer 200 by forming an insulating layer such as an oxide layer on the photodiode layer 201 and patterning the same. In addition, the device isolation pattern 240 may expose the crystalline semiconductor layer 200 on the peripheral portion B.

Referring to FIG. 8, a device isolation trench 235 is formed in the crystalline semiconductor layer 200. The isolation trench 235 may be formed by etching the crystalline semiconductor layer 200 using the isolation pattern 240 as an etching mask. Then, the photodiode layer 201 on the pixel portion A may be connected to the wiring 150 separated by the device isolation trench 235 and separated by unit pixels.

That is, the first photodiode 205 connected to the wiring 150 may be a unit pixel that operates substantially, and the second photodiode 205 connected to the wiring 150a may be a dummy pixel. In addition, when the first and second photodiodes 205 and 205a are formed, the crystalline semiconductor layer 200 of the peripheral portion B is removed to remove the interlayer insulating layer 160 and the wiring 170 of the peripheral portion B. Is exposed.

Referring to FIG. 9, a device isolation layer 250 is formed on a first substrate 100 including the device isolation trench 235. The device isolation layer 250 may be formed of a transparent insulating layer such as an oxide film. Since the device isolation layer 250 fills the inside of the device isolation trench 235 and is formed on the interlayer insulating layer 100, the first and second photodiodes 205 and 205a may be separated from each other. . In addition, the device isolation layer 250 is formed on the entire upper surface of the interlayer insulating layer 160 to protect the first and second photodiodes 205 and 205a and the wiring 170 of the peripheral portion B. have.

Referring to FIG. 10, first and second via holes 255 and 257 are formed in the device isolation layer 250. The first and second via holes 255 and 257 may partially remove the device isolation layer 250 to expose the surface of the first photodiode 205 and the interconnection 170.

Referring to FIG. 11, an upper electrode layer 260 is formed on the device isolation layer 250 including the first and second via holes 255 and 257. The upper electrode layer 260 may be formed by depositing a conductive material on the device isolation layer 250 including the first and second via holes 255 and 257. For example, the upper electrode layer 260 may be formed of an opaque metal layer such as titanium, aluminum, copper, cobalt, and tungsten.

The upper electrode layer 260 may be electrically connected to the first photodiode 205 separated for each unit pixel through the first via hole 255. In addition, the upper electrode layer 260 may be electrically connected to the wiring 170 of the peripheral portion B through the second via hole 257. The upper electrode layer 260 is formed to extend from the first via hole 255 to the second via hole 257 to cover the upper region of the second photodiode 205a. Therefore, the light is blocked to the second photodiode 205a by the upper electrode layer 260.

The upper electrode layer 260 is connected only to the first photodiode 205 so that the first photodiode 205 performs a substantial operation. In addition, since the upper electrode layer 262 is not electrically connected to the second photodiode 205a, the second photodiode pattern 205a may serve as a dummy pixel. In general, the leakage factor in measuring the leakage current may be due to the lower wiring and the upper wiring. In the exemplary embodiment, when the leakage current of the wiring 150 does not occur, the dummy current is not connected to the upper electrode layer 260 which is the reset line, thereby eliminating the leakage current factor of the reset line. Measurement is possible. Since the liquid current directly affects a dark signal, the second photodiode 205a can be used as a reference pixel for the dark signal by using the second photodiode 205a as a dummy pixel.

In addition, since the upper electrode layer 260 acts as a blocking film of the second photodiode 205a, an output image due to a hot pixel may be improved by comparing signal differences due to internal or external temperature.

Referring to FIG. 12, a first exposed portion 265 is formed in the upper electrode layer 260 to expose a light receiving region of the first photodiode 205 formed for each unit pixel. The first exposure part 265 may secure the light receiving area of the first photodiode 205 by removing the upper electrode layer 260 on the first photodiode 205 formed for each unit pixel.

In addition, when the first exposed portion 265 is formed, a second exposed portion 267 exposing the device isolation layer 250 on the pad 180 may be formed.

Referring to FIG. 13, a first passivation layer 270 and a second passivation layer 280 are formed on the interlayer insulating layer 160 on which the first and second exposed portions 265 and 267 are formed. The first passivation layer 270 may be in contact with the device isolation layer 250 through the first exposed portion 265. For example, the first protective layer 280 may be formed of an oxide film or a nitride film. The second protective layer 280 may be formed of a nitride film or an oxide film.

Referring to FIG. 14, a pad hole 285 exposing the pad 180 on the peripheral portion B is formed. The pad hole 285 is formed by removing the interlayer insulating layer 160, the device isolation layer 250, the first passivation layer 270, and the second passivation layer 280 on the pad 180. Can be exposed.

Referring to FIG. 15, a pad protection layer 290 is formed on the interlayer insulating layer 160 on which the pad hole 285 is formed. The pad protective layer 290 is to prevent the pad 180 from being contaminated during the subsequent formation of the color filter 300 and the micro lens (not shown). For example, the pad protection layer 290 may have a TEOS layer having a thickness of about 10 to about 200 kPa.

Referring to FIG. 16, a color filter 300 and a micro lens (not shown) are formed on the pad protection layer 290 corresponding to the first and second photodiodes 205. The color filter 300 is formed one by one unit pixel to separate the color from the incident light.

Second Embodiment

17 is a partial detailed view of an image sensor according to a second embodiment.

The image sensor according to the second embodiment includes a first substrate 100 on which a readout circuitry 120 is formed; A wiring 150 formed on the first substrate 100 to be electrically connected to the readout circuit 120; And a photodiode (not shown) electrically connected to the wiring 150 and formed in the crystalline semiconductor layer on the upper side of the first substrate 100.

The second embodiment can employ the technical features of the first embodiment.

For example, the first photodiode 205 of the second embodiment may be separated by unit pixels by the device isolation trench 235 and the device isolation layer 250. In addition, a protective layer 270 may be formed on the interlayer insulating layer 160 including the first photodiode 205 to protect the photodiode 205 and other devices. In addition, a second photodiode 205a that is a dummy pixel that is not electrically connected to the upper electrode layer 260 may be formed to measure the liquid current.

Meanwhile, unlike the first embodiment, the second embodiment is an example in which the first conductive connection region 148 is formed on one side of the electrical bonding region 140. The first conductive connection region 148 may be formed between the electrical junction region 140 and the device isolation layer 110, and may be electrically connected to the electrical junction region while being in contact with the device isolation layer 110.

According to an embodiment, an N + connection region 148 for ohmic contacts may be formed in the P0 / N− / P− junction 140, in which the process of forming the N + connection region 148 and the M1C contact 151a may be performed. It can be a Leakage Source. This is because the electric field EF may be generated on the Si surface of the substrate because the reverse bias is applied to the P0 / N− / P− junction 140. The crystal defects generated during the contact forming process in the electric field become a liquid source.

In addition, when the N + connection region 148 is formed on the surface of the P0 / N- / P- junction 140, an E-Field by the N + / P0 junction 148/145 is added, which is also a leakage source. Can be

Accordingly, in the second embodiment, the first contact plug 151a is formed in an active region formed of the N + connection region 148 without being doped with a P0 layer, and a layout for connecting the first contact plug 151a with the N-junction 143 is provided. present.

According to the second embodiment, the E-Field of the Si surface does not occur, which may contribute to the reduction of dark current of the 3-D integrated CIS.

1 to 16 are cross-sectional views illustrating a manufacturing process of the image sensor according to the first embodiment.

17 is a partial detailed view of an image sensor according to a second embodiment.

FIG. 18 illustrates a photocharge dumping structure of the readout circuit according to the first embodiment.

19 is a view showing a photocharge dumping structure of a lead-out circuit according to the prior art.

Claims (19)

A first substrate including a pixel portion on which a readout circuit is formed and a peripheral portion on which a peripheral circuit is formed; A wiring and an interlayer insulating film formed on the first substrate so as to be connected to the readout circuit and the peripheral circuit; A crystalline semiconductor layer formed on the interlayer insulating film corresponding to the pixel portion; A first photodiode and a second photodiode formed on the crystalline semiconductor layer and separated by unit pixels by device isolation trenches and electrically connected to the wirings, respectively; A device isolation layer formed on the crystalline semiconductor layer including the device isolation trench; An upper electrode layer partially connected to the first photodiode through the device isolation layer; An exposed portion formed in the upper electrode layer to selectively expose an upper region of the first photodiode; And And a protective layer disposed on the first substrate including the exposed portion. The method of claim 1, The device isolation layer includes a first via hole exposing the first photodiode, and the upper electrode layer is electrically connected to the first photodiode through the first via hole. The method of claim 1, The first photodiode is a main pixel electrically connected to the upper electrode layer to perform a substantial operation, and the second photodiode is a dummy pixel not electrically connected to the upper electrode layer. The method of claim 1, The lead out circuit is An electrical junction region formed in the first substrate, The electrical junction region is A first conductivity type ion implantation region formed on the first substrate; And And a second conductivity type ion implantation region formed on the first conductivity type ion implantation region. The method of claim 4, wherein And a first conductivity type connection region formed on the electrical junction region and electrically connected to the wiring. The method of claim 4, wherein The electrical junction region is Image sensor characterized in that the PNP junction (junction). The method of claim 1, The readout circuit includes a transistor, And a potential difference between the source and the drain of both sides of the transistor. The method of claim 7, wherein The transistor is a transfer transistor, And an ion implantation concentration of a source region located on one side of the transfer transistor is lower than an ion implantation concentration of a floating diffusion region, which is a drain region located on the other side of the transfer transistor. The method of claim 4, wherein And a first conductivity type connection region formed on one side of the electrical junction region to be electrically connected to the wiring. 10. The method of claim 9, An isolation region is formed on the first substrate to define an active region. The first conductivity type connection region, An image sensor formed between the electrical junction region and the device isolation layer and electrically connected to the electrical junction region while being in contact with the device isolation layer. Forming a pixel portion including a readout circuit and a peripheral portion including a peripheral circuit on the first substrate; Forming a wiring and an interlayer insulating film on the first substrate and connected to the readout circuit and the peripheral circuit; Forming a second substrate comprising a crystalline semiconductor layer; Forming a photodiode layer on the crystalline semiconductor layer; Bonding a second substrate including the first substrate and the photodiode layer; Removing a portion of the second substrate to expose the photodiode layer; Forming a device isolation trench in the crystalline semiconductor layer to separate the pixel for each unit pixel, and forming a first photodiode and a second photodiode electrically connected to the wires; Forming an isolation layer on the crystalline semiconductor layer including the first and second photodiodes; Forming an upper electrode layer on the device isolation layer through the device isolation layer to be electrically connected to the first photodiode; Forming an exposed portion by removing a portion of the upper electrode layer to selectively expose an upper region of the first photodiode; And And forming a protective layer on the interlayer insulating film including the exposed portion. The method of claim 11, When the device isolation trench is formed, the crystalline semiconductor layer on the periphery is removed to expose the wiring of the periphery. The method of claim 11, Forming the upper electrode layer, Forming a first via hole in the device isolation layer to partially expose the surface of the first photodiode; And forming a metal layer on the device isolation layer including the first via hole. The method of claim 13, And forming a second via hole exposing the wiring of the peripheral part when the first via hole is formed. And the upper electrode layer is electrically connected to the wires of the peripheral portion through the second via hole. The method of claim 11, Forming a lead-out circuit on the first substrate comprises forming an electrical junction region on the first substrate, Forming an electrical junction region on the first substrate, Forming a first conductivity type ion implantation region in the first substrate; And And forming a second conductivity type ion implantation region on the first conductivity type ion implantation region. The method of claim 15, And forming a first conductive connection region electrically connected to the wiring on the electrical junction region. The method of claim 16, Forming the first conductivity type connection region, The method of manufacturing an image sensor, characterized in that proceeds after the contact etched on the wiring. The method of claim 15, And forming a first conductive connection region electrically connected to the wiring at one side of the electrical junction region. The method of claim 18, An isolation region is formed on the first substrate to define an active region. The first conductivity type connection region, A method formed between the electrical junction region and the device isolation layer and in electrical contact with the electrical junction region while being in contact with the device isolation layer.

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