JP3719947B2 - Solid-state imaging device and manufacturing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a solid-state imaging device and a manufacturing method thereof, and more particularly to a solid-state imaging device in which a light conversion element is integrated on a semiconductor substrate and a manufacturing method thereof.
[0002]
[Prior art and problems to be solved by the invention]
Conventionally, a MOS type solid-state imaging device composed of a light conversion element formed by a photodiode and a scanning element is known. For example, in Japanese Patent No. 2594992, a plurality of photodiodes as light conversion elements are provided on a plurality of photodiodes. A MOS-type solid-state imaging device is described in which a MOS-type transistor as a scanning element is formed and the area occupied on a silicon substrate per pixel is reduced to enable high resolution.
[0003]
FIG. 8A shows a cross-sectional view of such a MOS type solid-state imaging device, and FIG. 8B shows a circuit diagram thereof.
As shown in FIGS. 8A and 8B, a photodiode 3 is formed in a P well 2 on the silicon substrate 1, and a MOS transistor switch 60 for reading the signal charge of the photodiode 3 A pixel amplifier MOS transistor 61 for amplifying, a reset MOS transistor 62 for resetting signal charges, and the like are provided for each pixel.
[0004]
The photodiode 3 is separated by the thermal oxide film 4 and the P-type diffusion layer 5, and the MOS transistor switch 60 forms a gate 60G and a drain 60D.
The reset MOS transistor switch 62 is formed on the photodiode 3 with the insulating layer 6 interposed therebetween, and constitutes a source 62S, a gate 62G, and a drain 63. The source 62S also serves as the gate 61G of the pixel amplifier MOS transistor 61.
[0005]
An insulating film 7, an insulating film 8, and a drain line 64 are provided on the reset MOS transistor switch 62.
In such a MOS type solid-state imaging device, if the thickness in the depth direction in the silicon region on the photodiode 3 is set to 100 nm or less, the attenuation amount of light transmitted in the thickness direction becomes small. Therefore, a decrease in sensitivity of the photodiode due to the presence of the silicon region can be suppressed to an amount that can be ignored by human vision.
[0006]
In such a MOS type solid-state imaging device, as shown in the circuit diagram shown in FIG. 8B, the vertical signal line 48 for transferring the signal charge amplified by the pixel amplifier MOS transistor 61 has been transferred. The storage capacitors 51 and 52 for storing the signal charges via the switches 49 and 50 are provided for each column in the vertical direction.
Further, switches 49 and 50 are respectively connected in the horizontal direction, and an output amplifier 57 having a feedback resistor 58, horizontal signal lines 55 and 65 connected to an output terminal 59, and the like are provided.
[0007]
The MOS transistor switch 60 is scanned through the photogate line 47 by a photogate selection circuit (not shown).
The drain of the pixel amplifier MOS transistor 61 and the drain of the reset MOS transistor 62 are scanned through the drain line 46 by a pixel amplifier selection circuit (not shown).
[0008]
The vertical signal line 48 connected to the gate of the reset MOS transistor 62 is connected to the reset gate line 54 via the switch 53.
In such a MOS type solid-state imaging device, since the light conversion element and the reading element are formed only on the surface side of the semiconductor substrate, the optical information input from above is partially reflected by the metal wiring, There is a problem that the signal-to-noise ratio (S / N ratio) becomes small and the optical signal is lowered.
[0009]
In order to obtain a predetermined S / N ratio with respect to such a problem, a method of increasing the occupation area of the impurity region constituting the light conversion element is known. Due to the dimensional arrangement, there is a problem that the occupied area per pixel becomes large and a limit occurs at a certain point.
[0010]
For example, Japanese Patent No. 2594992 discloses a light conversion element in which a plurality of photodiodes that accumulate signal charges are provided two-dimensionally on the surface of a semiconductor substrate in accordance with optical information, and the light conversion element includes And a semiconductor element (hereinafter referred to as “read element”) for reading the accumulated signal charge, and at least one of the read elements is provided on the light conversion element region of the semiconductor substrate via an insulating film. A solid-state imaging device is disclosed.
[0011]
However, even in such a method, there is a problem that the optical information is reflected in the metal wiring region portion for wiring the reading element, and the S / N ratio is lowered.
[0012]
An object of the present invention is to reduce the noise (which can increase the S / N ratio) generated by reflecting light incident on the light conversion element region even if the area occupied by the light conversion element is increased to some extent. An object of the present invention is to provide a MOS type solid-state imaging device capable of increasing the resolution and reducing the chip area.
[0013]
[Means for Solving the Problems]
In view of the above problems, as a result of intensive research, the present inventor has provided a light conversion element two-dimensionally on the surface of the first semiconductor substrate according to optical information, and light conversion is performed on the light conversion element via a light shielding film. A solid-state imaging device provided with a second semiconductor substrate having an element for reading out signal charges accumulated in the element has been found to solve the above problem by capturing optical information from the back surface of the first semiconductor substrate. The invention has been completed.
[0014]
Thus, according to the present invention, the light conversion element is formed on the surface of the first semiconductor substrate, the second semiconductor substrate, and the second semiconductor substrate each having a light conversion element that takes in optical information and converts it into a signal charge. A semiconductor element for reading out the signal charge accumulated in the first semiconductor substrate, and a metal layer for bonding the first semiconductor substrate and the back surface opposite to the front surface of the second semiconductor substrate through an insulating film, and There is provided a solid-state imaging device characterized in that a contact reaching the first semiconductor substrate from the surface of the second semiconductor substrate is formed.
[0015]
Further, according to the present invention, the steps of forming a light conversion element for converting into an internal uptake signal charge optical information of the first semiconductor board, the first semiconductor substrate, the oxide film and the first metal layer laminating formed in this order, the second semiconductor substrate, an oxide film and a second metal layer laminating formed in this order, and fusing said first metal layer and the second metal layer, wherein Bonding the first semiconductor substrate and the second semiconductor substrate, forming a contact reaching the first semiconductor substrate from the surface facing the second metal layer of the second semiconductor substrate, and a second of the second semiconductor substrate. A solid-state imaging device comprising: a step of forming a semiconductor element for reading signal charges accumulated in the light conversion element on a surface facing the metal layer; and a step of polishing the first semiconductor substrate to a desired thickness A manufacturing method is provided.
[0016]
DETAILED DESCRIPTION OF THE INVENTION
One solid-state imaging device that uses a photodiode is a CMOS image sensor. There are generally two circuit configurations for each pixel of the CMOS image sensor: a three-transistor type composed of a photodiode and three readout transistors, and a four-transistor type composed of a photodiode and four readout transistors. Are known.
[0017]
FIG. 5A shows a cell plan view of a 3-transistor type CMOS image sensor, and FIG. 6 shows a circuit diagram thereof.
Hereinafter, an operation method of the three-transistor type CMOS image sensor will be described.
[0018]
First, the charge remaining on the wiring is discharged to the drain line 18 by turning on the reset transistor 12, and then the reset transistor 12 is turned off. Next, charges are accumulated in the gate of the amplification transistor 13 by the carriers generated by photoelectric conversion of the photodiode 11, and the amplification transistor 13 is turned on. At the same time, when the selection transistor 14 is turned on, a signal is read out to the signal line 15.
[0019]
Next, a cell plan view of a 4-transistor type CMOS image sensor is shown in FIG. 5B, and a circuit diagram thereof is shown in FIG.
Hereinafter, an operation method of the 4-transistor type CMOS image sensor will be described.
[0020]
First, the charge remaining on the wiring is discharged to the drain line 27 by turning on the reset transistor 23, and then the reset transistor 23 is turned off. Next, when the read transistor 20 is turned on, carriers generated by photoelectric conversion of the photodiode 19 flow into the amplification transistor 21 side. At this time, when the read transistor 20 is turned off, charges are accumulated in the gate of the amplification transistor 21 and the amplification transistor is turned on. At the same time, when the selection transistor 22 is turned on, a signal is read out to the signal line 24 .
[0021]
Hereinafter, although the present invention is explained in detail based on an embodiment, the present invention is not limited by these embodiments.
[0022]
Embodiment 1
[Manufacturing method of 3-transistor type CMOS image sensor]
A manufacturing method of the 3-transistor type CMOS image sensor will be described with reference to manufacturing process diagrams (FIGS. 1 to 3) taken along a line AB in FIG.
As shown in FIG. 2A, impurities are implanted into a silicon single crystal substrate 31 serving as a first semiconductor substrate to form a photodiode serving as a light conversion element, and the light conversion element of each pixel is electrically connected. Implantation for forming an impurity region to be separated is performed using a resist mask.
[0023]
Examples of the first semiconductor substrate include elemental semiconductors such as silicon and germanium, and compound semiconductors such as GaAs, InGaAs, and ZnSe. Of these, a silicon substrate is preferable.
Impurities for forming the light conversion element are implanted into a region from the surface of the silicon single crystal substrate 31 to a depth of about 2 to 48 μm with an implantation energy of several hundreds KeV to several tens MeV and a dose of 10 ¹³ to 10 ^16. Ion implantation is performed a plurality of times at ions / cm ² to form an N-type impurity layer 28 having a concentration of about 10 ¹⁷ to 10 ¹⁹ ions / cm ³ . Next, an N-type impurity layer 29 having a concentration of about 10 ¹⁶ to 10 ¹⁷ ions / cm ³ is implanted into a region having a depth of about 48 to 50 μm from the surface of the silicon single crystal substrate 31 with an implantation energy of several hundred keV to several tens MeV and a dose of 10 ^12. It is formed by ion implantation under the condition of -10 ¹⁴ ions / cm ² . Next, a P-type impurity layer 30 having a concentration of about 10 ¹⁷ to 10 ¹⁸ ions / cm ³ is implanted into a region having a depth of about 50 to 51 μm from the surface of the silicon single crystal substrate 31 with an implantation energy of several hundred keV to several tens MeV and a dose of 10 ^13. It is formed by ion implantation under the condition of -10 ¹⁵ ions / cm ² .
[0024]
The N-type impurity layer 29 and the P-type impurity layer 30 may be formed by implanting ions into the polished surface after polishing the silicon single crystal substrate 31 shown in FIG.
The P-type impurity layer 30 prevents the charge formed in the photodiode (the N-type impurity layer 28) from decreasing due to surface leakage, so that the N-type impurity layer 28 in which a depletion layer is generated is removed from the substrate surface. Keep away.
[0025]
In addition, implantation is performed to form a P-type impurity region 32 that electrically isolates the light conversion element of each pixel. The implantation is not particularly limited as long as it functions as electrical isolation of the light conversion element, and is performed under conditions of implantation energy of several hundred keV to several tens of MeV and a dose of 10 ¹³ to 10 ¹⁵ ions / cm ² . A P-type impurity region 32 having a concentration of about 10 ¹⁸ to 10 ²⁰ ions / cm ³ is formed.
[0026]
For example, boron can be used as the P-type impurity used for the impurity implantation, and antimony, arsenic, phosphorus, or the like can be used as the N-type impurity.
Next, as shown in FIG. 2B, a SiO ₂ layer 34 is formed on the surface of the silicon single crystal substrate 31 to a thickness of about 1000 to 4000 mm.
Next, Al, which is a low melting point metal as the first metal layer , is sputtered on the SiO ₂ layer 34 to form the Al layer 33.
[0027]
Next, as shown in FIG. 2C, a silicon substrate 37 as a second semiconductor substrate is prepared separately from the silicon single crystal substrate 31, and a SiO ₂ layer 36 is formed on this surface with a thickness of about 1000 to 4000 mm. Then, an Al layer as a second metal layer is formed on the SiO ₂ layer 36 by sputtering.
As the second semiconductor substrate, the substrate mentioned in the first semiconductor substrate can be used other than the silicon substrate.
The first metal layer and the second metal layer are made of a material such as gold, silver, aluminum, copper, nickel, titanium, indium tin oxide (ITO), zinc oxide (ZnO), tin oxide (SnO), or the like. Things can be used. Of these, aluminum is preferably used.
[0028]
By superimposing the Al layer 33 of the silicon single crystal substrate 31 and the Al layer of the silicon substrate 37 and annealing in a nitrogen atmosphere at 500 to 600 ° C., both Al layers become an adhesive metal and strongly adhere to each other. An Al single layer film 35 is formed. At this time, since the SiO ₂ layers 34 and 36 exist, Al impurities do not diffuse into the silicon single crystal substrate 31 and the silicon substrate 37, respectively.
[0029]
Next, as shown in FIG. 2 (d), the silicon substrate 37 is mechanically or chemically polished by a known method to a thickness of about 1000 to 5000 mm to form a silicon active layer.
As described above, an SOI substrate having a light shielding film (Al single layer film 35) in the SiO ₂ layer is obtained.
[0030]
Next, as shown in FIG. 3A, element isolations 38 are formed at predetermined positions on the silicon substrate 37. The insulating film of the element isolation 38 can be formed using an STI method that is a known element isolation formation method. In this case, the thickness of the element isolation is usually about 2000 to 4000 mm.
[0031]
Next, as shown in FIG. 3B, a contact hole 40 for reading a signal accumulated in the light conversion element is opened on the silicon substrate 37 side, and the silicon substrate 37 is formed by a known method such as CVD. An insulating film of about 100 to 2000 mm, for example, an SiO ₂ film is formed on the surface and the side surface of the contact hole 40, and the entire surface is etched back to form the insulating film 39 only on the side wall of the hole.
[0032]
The contact hole 40 connects a wiring formed in the contact hole only to the gate of the read transistor. Accordingly, overetching is performed so that the entire region of the contact hole side wall (the surface of the silicon substrate 37) is covered with the insulating film 39.
[0033]
Next, as shown in FIG. 3C, the wiring 42 is formed only in the contact hole 40. As the formation method, there is a method in which polysilicon containing N-type impurities is deposited by a known method such as a CVD method or the like to deposit a film having a thickness larger than that in which holes are completely buried, and then the entire surface is etched back.
[0034]
Next, the amplification transistor 13, the reset transistor 12 (not shown), and the selection transistor 14 (not shown) are formed on the silicon substrate 37 by a known method. At this time, a wiring (not shown) for connecting the contact wiring 41 and the gate portion of the reading transistor is also formed.
[0035]
Next, as shown in FIG. 3D, an oxide film 43 is deposited on the surface of the silicon substrate 37 to a film thickness of about 5000 to 10000 mm and planarized by the CVD method. Next, the contact hole 44 is opened, tungsten or the like is deposited by the CVD method, the entire surface is etched back, and a tungsten wiring is formed in the contact hole 44. Next, a metal layer such as Al is formed on the oxide film 43 and the tungsten wiring, and a metal wiring 45 is formed at a predetermined position including the contact hole 44 by photo and etching.
[0036]
Next, as shown in FIG. 1A, the silicon single crystal substrate 31 is mechanically or chemically polished by a known method. At that time, the film thickness from the interface between the SiO ₂ layer 34 and the N-type impurity layer 28 to the back surface of the silicon single crystal substrate 31 is set to the back surface of the silicon single crystal substrate 31 when an operating voltage is applied to the light conversion element. The thickness of the depletion generated in the direction is made less than the thickness of 1000 mm. This is because only the light incident on the solid-state imaging device that actually generates a signal charge is absorbed in the depletion layer of the photodiode, and the silicon film thickness under the depletion layer of the photodiode is increased. This is because the thicker the film, the more the incident signal is absorbed in the silicon single crystal substrate. In other words, the incident light is attenuated before being incident on the depletion layer of the photodiode, and the S / N ratio is prevented from decreasing. In general, human visibility is highest near a wavelength of 555 nm, and rapidly decreases at wavelengths around that. In addition, since the light with a wavelength of 555 nm has a property of almost transmitting if the silicon film is 1000 mm or less, it is also intended to suppress the deterioration of incident light by the silicon film to an amount that can be ignored by human vision.
[0037]
Embodiment 2
[Method for Manufacturing 4-Transistor CMOS Image Sensor]
Next, the manufacturing method of the 4-transistor type CMOS image sensor of the present invention will be described in detail with reference to process cross-sectional views (FIGS. 1 to 4) taken along the line AB of FIG.
[0038]
After carrying out in the same manner as the embodiment of the three-transistor type CMOS image sensor [FIGS. 2A to 2D], as shown in FIG. 4A, after forming the element isolation 38, the contact hole 57 is formed. An insulating film (for example, SiO ₂ film) of about 100 to 2000 mm is formed on the surface of the silicon substrate 37 and the side surface of the contact hole by a well-known technique such as CVD, and the entire surface is etched back so that only the hole side wall is formed. An insulating film side wall spacer 56 is formed. In order to connect the contact hole 57 to the source region of the signal reading transistor, over-etching is performed so that the side wall spacer is eliminated on the side wall above the contact hole (about 50 to 100 mm). Next, contact wiring is formed only in the contact hole 57. This method is performed by forming a film having a thickness larger than that in which a hole is completely buried by polysilicon or the like containing N-type impurities and etching back the entire surface.
[0039]
Next, as shown in FIG. 4B, a read transistor 20, an amplification transistor 21, a reset transistor 23 (not shown), and a selection transistor 22 (not shown) are formed on the substrate by a known method.
At this time, the contact wiring and the source part of the reading transistor 20 are arranged to be connected.
Thereafter, as shown in FIGS. 4C and 1B, a 4-transistor CMOS image sensor is manufactured in the same manner as in the first embodiment.
[0040]
【The invention's effect】
According to the present invention, the occupied area per pixel can be reduced and high resolution can be achieved. In addition, since there is no film that blocks or refracts optical information from the back surface of the silicon substrate to the light conversion element, and is a single layer of silicon, the S / N ratio, optical Signal degradation is improved. In addition, with the above structure, the light conversion element can secure a light receiving area having a cell pitch size substantially on the back surface of the semiconductor substrate, so that an on-chip microlens for increasing the light collection rate as in the prior art is unnecessary. Therefore, cost reduction can be realized at the same time.
[Brief description of the drawings]
FIG. 1 is an element cross-sectional view of a 3-transistor type and a 4-transistor type CMOS image sensor of the present invention.
FIG. 2 is a cross-sectional view of an element manufacturing process of a three-transistor type CMOS image sensor of the present invention.
FIG. 3 is a cross-sectional view of an element manufacturing process of a three-transistor type CMOS image sensor of the present invention.
FIG. 4 is a cross-sectional view of an element manufacturing process of a four-transistor type CMOS image sensor of the present invention.
FIG. 5 is a plan view showing a configuration of a unit cell of the 3-transistor type and 4-transistor type CMOS image sensor of the present invention.
FIG. 6 is a circuit diagram of a three-transistor CMOS image sensor of the present invention.
FIG. 7 is a circuit diagram of a four-transistor CMOS image sensor of the present invention.
FIG. 8 is a cross-sectional view and a circuit diagram of a conventional MOS type solid-state imaging device.
[Explanation of symbols]
1, 31, 37 Silicon substrate (silicon single crystal substrate)
2 P-well 3, 11, 19 Photodiode 4 Thermal oxide film 5 P-type diffusion layer 6, 7, 8, 39 Insulating film 12, 23 Reset transistor 13, 21 Amplifying transistor 14, 22 Select transistor 15 Signal line 16, 25 Address Lines 17, 26 Reset lines 18, 27, 46, 64 Drain line 20 Read transistors 55, 65 Horizontal signal lines 28, 29 N-type impurity layer 30 P-type impurity layer 32 P-type impurity region 33 Al layers 34, 36 SiO ₂ layer 35 Al single layer film 38 element isolation 40, 44, 57 contact hole 41 contact wiring 42 wiring 43 oxide film 45 metal wiring 47 photogate line 48 vertical signal line 49, 50 switch 51, 52 storage capacitor 54 reset gate line 56 side Wall spacer 57 Output amplifier 58 Feedback resistor 59 Output terminal 60 MOS transistor switch 61 Pixel amplifier MOS transistor 62 Reset MOS transistor switch 63 Drain

Claims (7)

A first semiconductor substrate having a light conversion element that takes in optical information and converts it into a signal charge, a second semiconductor substrate, and a signal charge formed on the surface of the second semiconductor substrate and accumulated in the light conversion element are read out. And a metal layer for bonding the first semiconductor substrate and the back surface opposite to the front surface of the second semiconductor substrate through an insulating film, and further, the surface of the second semiconductor substrate A solid-state imaging device, wherein a contact reaching the first semiconductor substrate is formed. The solid-state imaging device according to claim 1, wherein the metal layer is aluminum. The semiconductor element for reading the signal charge accumulated in the light conversion element is a three-transistor type composed of a photodiode and three readout transistors, or a four-transistor type composed of a photodiode and four readout transistors. The solid-state imaging device according to claim 1 or 2.   4. The optical conversion element comprises an N-type layer having a thickness equal to or less than a depth obtained by adding 1000 to the depth of depletion generated when an operating voltage is applied to the optical conversion element. The solid-state imaging device described in 1. Forming a light conversion element for converting the capture signal charges of light information into the first semiconductor board,
A step of forming an oxide film and a first metal layer in this order on the first semiconductor substrate;
A step of forming an oxide film and a second metal layer in this order on the second semiconductor substrate;
A step of fusing said first metal layer and the second metal layer, bonding the first semiconductor substrate and the second semiconductor substrate,
Forming a contact reaching the first semiconductor substrate from a surface facing the second metal layer of the second semiconductor substrate ;
Forming a semiconductor element for reading signal charges accumulated in the light conversion element on a surface of the second semiconductor substrate facing the second metal layer ;
And a step of polishing the first semiconductor substrate to a desired thickness. The method for manufacturing a solid-state imaging device according to claim 5, wherein aluminum is used for the first metal layer and the second metal layer . As a semiconductor element for reading signal charges accumulated in the light conversion element, a three-transistor type constituted by a photodiode and three readout transistors or a four-transistor type constituted by a photodiode and four readout transistors The manufacturing method of the solid-state imaging device according to claim 5 or 6.

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