JP5836581B2 - Manufacturing method of solid-state imaging device - Google Patents

Description

The present invention relates to a method of manufacturing a solid-state imaging device.

  In recent years, in order to improve the sensitivity of a solid-state imaging device, transistors and wiring patterns are arranged on the first surface (front surface) side of a semiconductor substrate, and light is incident on the second surface (back surface) side opposite to the front surface side. Back-illuminated solid-state imaging devices have been proposed. In the back-illuminated solid-state imaging device, the photoelectric conversion unit formed by the processing on the first main side and the members (for example, a light shielding film, a color filter, and a micro lens) formed by the processing on the second main side are positioned. It is necessary to match.

  In Patent Document 1, an insulating film having a region having a different film thickness is formed on the surface opposite to the light incident side of the semiconductor layer, and ions are formed so as to reach the incident side of the semiconductor layer through the insulating film. It is disclosed that an alignment mark 31 is formed on the incident side by injecting. The alignment mark 31 is configured by a region having a refractive index difference due to a difference in ion concentration corresponding to a region having a different thickness of the insulating film. Patent Document 1 also discloses that a second alignment mark 32 having a step is formed on the insulating film 23 covering the alignment mark 31 with the alignment mark 31 as a reference. The alignment of the metal layer formed on the insulating film 23 can be performed using the second alignment mark 32.

JP 2008-147332 A

  In the technique described in Patent Document 1, since the second alignment mark 32 having a step is formed on the insulating film 23 after forming the alignment mark 31 composed of a region having a refractive index difference, the second alignment mark 32 is formed. A lithography process is indispensable.

  The present invention has been made against the background of the above-mentioned problem recognition, and provides an advantageous technique for simplifying the manufacturing process of a back-illuminated solid-state imaging device.

A method of manufacturing a solid-state imaging device according to one aspect of the present invention includes a step of preparing a semiconductor substrate having a first surface and a second surface, which are surfaces opposite to each other, and including a first impurity semiconductor region; A first implantation step of forming a charge storage portion in the semiconductor substrate by implanting ions from the first surface to the semiconductor substrate; and implanting ions from the first surface to the semiconductor substrate. Forming a second impurity semiconductor region to form a mixed region including the first and second impurity semiconductor regions in the semiconductor substrate; and thinning the semiconductor substrate from the second surface side. And reducing the thickness of the mixed region by using an etchant having different etching rates for the first impurity semiconductor region and the second impurity semiconductor region. And a etching process for forming the mark having a step on the mixed region by etching.

  According to the present invention, an advantageous technique is provided to simplify the manufacturing process of a back-illuminated solid-state imaging device.

The figure explaining the manufacturing method of the solid-state image sensor of 1st Embodiment of this invention. The figure which illustrates the positional relationship of a mark and a chip | tip. The figure explaining the manufacturing method of the solid-state image sensor of 2nd Embodiment of this invention.

  A solid-state imaging device according to an embodiment of the present invention includes a semiconductor substrate having a first surface and a second surface that are surfaces opposite to each other. A pixel including a photoelectric conversion portion that also serves as a charge storage portion and a readout circuit is formed on the semiconductor substrate. In the charge storage unit, electrons or holes generated by photoelectric conversion are stored. The charge accumulated in the charge accumulation unit is read out by the readout circuit. The read circuit can include, for example, a transfer transistor, an amplification transistor, and a reset transistor. The transfer transistor transfers the charge accumulated in the charge accumulation unit to the floating diffusion. The voltage of the floating diffusion changes according to the amount of charge transferred to the floating diffusion. The amplification transistor outputs a signal corresponding to the voltage of the floating diffusion to the vertical signal line. The reset transistor resets the potential of the floating diffusion. The readout circuit may further include a selection transistor that selects a row. If the selection transistor is not provided, the row can be selected by controlling the voltage of the floating diffusion by the reset transistor. Transistors such as the transfer transistor, the amplification transistor, the reset transistor, and the selection transistor may be formed on the first surface of the semiconductor substrate. The solid-state imaging device according to the embodiment of the present invention photoelectrically converts light incident on the photoelectric conversion unit from the second surface side, and reads out charges generated by the photoelectric conversion.

  For example, a light shielding film and a color filter may be disposed on the second surface side of the semiconductor substrate. A microlens can be further disposed on the second surface side of the semiconductor substrate. Etching a mixed region including a first impurity region and a second impurity semiconductor region formed by implanting ions into the semiconductor substrate from the first surface side of the semiconductor substrate on the second surface of the semiconductor substrate. A mark is formed by. Since this mark is formed through a process of implanting ions from the first surface side of the semiconductor substrate into the semiconductor substrate, the positional relationship with the circuit elements formed on the first surface side is guaranteed. .

  A method for manufacturing a solid-state imaging device according to the first embodiment of the present invention will be described with reference to FIGS. In the step shown in FIG. 1A, a plurality of circuit elements are formed on the first surface 3 of the semiconductor substrate 1 having the first surface 3 and the second surface 4 that are opposite to each other, thereby forming an integrated circuit. Form. Here, the circuit element may include, for example, the photoelectric conversion unit 20, a transistor, and a capacitor element. The integrated circuit includes, for example, a pixel array in which a plurality of pixels are arranged, a row selection circuit that selects a row of the pixel array, a column selection circuit that selects a column of the pixel array, and the row selection circuit and the column. An output circuit that outputs a signal of a pixel selected by the selection circuit can be included. The semiconductor substrate 1 can include, for example, a silicon single crystal layer 30 formed by epitaxial growth on a bulk silicon substrate. FIG. 1A schematically shows a photoelectric conversion unit 20 that also serves as a charge storage unit, and a transfer transistor 21 that transfers charges accumulated in the photoelectric conversion unit 20 to a floating diffusion 22. In one example, the semiconductor substrate 1 is a P-type semiconductor substrate, the photoelectric conversion unit 20 that also serves as a charge storage unit is an N-type semiconductor region, and electrons are stored in the photoelectric conversion unit 20. In another example, the semiconductor substrate 1 is an N-type semiconductor substrate, the photoelectric conversion unit 20 that also serves as a charge storage unit is a P-type semiconductor region, and holes are stored in the photoelectric conversion unit 20. The photoelectric conversion unit 20 can be formed in an arbitrary range within a depth range of 1 to 10 μm from the first surface of the semiconductor substrate 1. Here, the step of forming the circuit element shown in FIG. 1A is a first step of forming the photoelectric conversion unit 20 in the semiconductor substrate 1 by implanting ions from the first surface 3 side into the semiconductor substrate 1. An injection step may be included. The step of forming the circuit element shown in FIG. 1A can also include a step of forming a transistor such as the transfer transistor 21.

  Next, the step shown in FIG. In the process shown in FIG. 1B, a photoresist film is formed so as to cover the first surface 3 side of the semiconductor substrate 1, and is patterned by a photolithography process to form a resist pattern 120 having an opening 400. Process. In the step shown in FIG. 1B, the first impurity semiconductor region 102 and the second impurity semiconductor region are also implanted into the semiconductor substrate 1 by implanting ions from the first surface 3 side through the opening 400 of the resist pattern 120. A second implantation step for forming the mixed region 103 including 101 is included. Here, typically, in the first implantation step, the photoelectric conversion unit 20 is formed by implanting ions into the semiconductor substrate 1 including the first impurity semiconductor region 102, and in the second implantation step, the second impurity semiconductor is formed. Ions for forming the region 101 are implanted into the first impurity semiconductor region 102. As a result, a mixed region 103 including the first impurity semiconductor region 102 and the second impurity semiconductor region 101 is formed. However, the second implantation step includes a step of implanting ions for forming the first impurity semiconductor region 102 into the semiconductor substrate 1 and a step of implanting ions for forming the second impurity semiconductor region 101 into the semiconductor substrate 1. And may be included. In the second implantation step, the mixed region 103 is formed such that the end of the mixed region 103 on the second surface 4 side is closer to the second surface 4 than the end of the photoelectric conversion unit 20 on the second surface 4 side. It is preferable to do. After completion of the second implantation step, the resist pattern 120 is removed by a treatment such as ashing (ashing) or sulfuric acid immersion.

In one example, the first impurity semiconductor region 102 is a silicon single crystal layer 30 formed by epitaxial growth, and may contain, for example, boron at a concentration of 1 × 10 ¹⁷ cm ⁻³ or less. In addition, the second implantation step can be performed with the ion species being boron or boron difluoride, the dose amount being 1 × 10 ^{14 to} 1 × 10 ¹⁷ cm ⁻² and the acceleration energy being 1 to 5 MeV. The second impurity semiconductor region 101 may contain boron or boron difluoride at a concentration of 1 × 10 ^{17 to} 1 × 10 ²⁰ cm ⁻³ .

FIG. 2 is a schematic plan view of the first surface 3 of the semiconductor substrate 1 as viewed from above. FIG. 2 shows an example of the opening 400 that the resist pattern 120 has. A second impurity semiconductor region 101 is formed in a portion corresponding to the opening 400, and a mark for alignment is formed by etching the mixed region 103 including the second impurity semiconductor region 101 and the first impurity semiconductor region 102 as described later. It is formed. The opening 400 is preferably disposed in a dicing area between the chip area 71 and the chip area 71. The dimension of the mark 23 may be in the range of 1 μm ^{2 to} 1 mm ² , for example. The shape of the second impurity semiconductor region 101 can be determined to be, for example, a cross shape or a quadrangle according to a mark to be formed.

The step of forming the second impurity semiconductor region 101 may be performed, for example, before the formation of the element isolation portion such as STI or LOCOS, or may be performed at an arbitrary stage after the formation of the element isolation portion. However, the impurity concentration distribution in the semiconductor substrate formed by ion implantation changes due to diffusion depending on the heat treatment conditions. Therefore, it is desirable that the heat treatment after the formation of the second impurity semiconductor region 101 employs heat treatment conditions that suppress impurity diffusion, such as a heat treatment method that suppresses impurity diffusion (for example, RTA (Rapid Thermal Annealing)). In the step shown in FIG. 1C, the interlayer insulating layer 220 and the wiring structure 210 are formed. The wiring structure 210 includes a wiring pattern made of at least one material selected from the group consisting of aluminum, copper, tungsten, and titanium nitride, for example. In the step illustrated in FIG. 1C, the support substrate 230 is further bonded to the surface of the interlayer insulating layer 220.

  Next, the step shown in FIG. The process shown in FIG. 1D includes a thinning process in which the semiconductor substrate 1 is thinned from the second surface 4 side to expose the mixed region 103. In the second injection step, the mixed region 103 is formed so that the end of the mixed region 103 on the second surface 4 side is closer to the second surface 4 than the end of the photoelectric conversion unit 20 on the second surface 4 side. When formed, a structure in which the photoelectric conversion unit 20 is embedded in the semiconductor substrate 1 can be obtained. This is advantageous for reducing noise due to dark current. The thinning step can include a step of polishing the second surface 4 of the semiconductor substrate 1 by a mechanical polishing method, a chemical mechanical polishing method (CMP), or the like. Alternatively, when a substrate having a porous layer therein is prepared as the semiconductor substrate 1 and the steps shown in FIGS. 1A, 1B, and 1C are performed on the substrate, the thinning step includes This may be a step of dividing the substrate using the porous layer. The substrate having the porous layer is formed by anodizing the surface of the silicon substrate in a solution containing hydrogen fluoride to form a porous layer on the surface, and then a single crystal silicon layer on the porous layer. Can be obtained by growing.

  Next, the step shown in FIG. In the step shown in FIG. 1E, a step is formed in the mixed region 103 by etching the mixed region 103 using an etchant having different etching rates of the first impurity semiconductor region 102 and the second impurity semiconductor region 101. Forming a mark 23 having the same. Such an etchant is an etchant that generates different etching rates depending on the difference in impurity concentration, the type of impurity, and the conductivity type of the impurity semiconductor region. In the example shown in FIG. 1E, etching is performed using an etchant whose etching rate of the first impurity semiconductor region 102 is smaller than that of the second impurity semiconductor region 101. Therefore, the second impurity semiconductor region 101 is etched more than the first impurity semiconductor region 102. As a result, the second impurity semiconductor region 101 is recessed from the first impurity semiconductor region 102, thereby forming a step constituting the mark 23. The mark 23 is formed by etching a mixed region including the first impurity region and the second impurity semiconductor region formed by implanting ions into the semiconductor substrate 1 from the first surface 3 side of the semiconductor substrate 1. . The resist pattern 120 for implanting ions from the first surface 3 side with respect to the semiconductor substrate 1 is aligned with a circuit element such as the photoelectric conversion unit 20. Therefore, the mark 23 can be formed by being aligned with the circuit element on the first surface 3 side with the same positional accuracy as the alignment mark formed on the first surface 3 side. Therefore, the positions of the light shielding film, the color filter, and the microlens can be determined in the subsequent process using the mark 23.

As the etchant, for example, hydrogen fluoride (HF), nitric acid _(HNO 3), acetic acid _{(CH 3 COOH) 1: 3} : 8 may be used a mixed solution obtained by mixing with a volume ratio. When the semiconductor substrate 1 is immersed in the mixed solution, the boron concentration is 1 × 10 ^{18 to} 1 × 10 ²⁰ cm ⁻³ in the first impurity semiconductor region 102 having a boron concentration of 1 × 10 ¹⁷ cm ⁻³ or less. The etching rate of the two impurity semiconductor region 101 can be increased 100 times or more. Therefore, by immersing the semiconductor substrate 1 in the above mixed solution, the second impurity semiconductor region 101 is etched without substantially etching the first impurity semiconductor region 102, and a step is formed. Alternatively, as the etchant, a mixed solution of potassium hydroxide (KOH), isopropyl alcohol (IPA) and water, or a mixed solution of ethylenediamine, pyrocatechol and water called EPW system can be used. In this case, a silicon crystal having a lower impurity concentration of boron has a higher etching rate, so that a step in which the second impurity semiconductor region 101 is convex can be formed. The height of the step for forming the mark 23 is preferably about 0.1 μm to 1 μm, but it is sufficient that a step capable of obtaining a contrast capable of recognizing the step in the semiconductor manufacturing apparatus can be formed.

  Next, in the step shown in FIG. 1F, the light shielding film 302, the planarizing film 301, the color filter 300, and the microlens 310 are formed using the mark 23 having a step as an alignment mark. Thereby, a back-illuminated solid-state imaging device is manufactured. The light shielding film 302 is made of a material having a low transmittance with respect to visible light, such as aluminum, tungsten, polycrystalline silicon, or the like in order to prevent light from entering the adjacent photoelectric conversion unit 20. It forms so that the photoelectric conversion part 20 which fits may be partitioned off. For the light shielding film 302, a light shielding material is formed over the entire surface of the second surface 4 of the semiconductor substrate 1, and then a photoresist is applied thereon, a resist pattern is formed by photolithography, and the resist pattern is used as a light shielding material. Formed by etching material. Even if the light shielding material is formed over the entire surface of the second surface 4 of the semiconductor substrate 1, the mark 23 can be detected by the level difference, so that a resist pattern can be formed with high accuracy by photolithography.

  In addition to the above, as an antireflection film for preventing loss due to reflection of incident light, a thin film of hafnium oxide, titanium oxide, silicon nitride or the like is formed on the second surface 4 side of the semiconductor substrate 1 and the planarizing film 301. You may provide between.

  As described above, according to the first embodiment, it is not necessary to form the second alignment mark as in Patent Document 1, so the number of processes is reduced. In the solid-state imaging device manufactured according to the first embodiment, a part of the second surface of the semiconductor substrate 1 is formed by the mixed region 103 including the first impurity semiconductor region 102 and the second impurity semiconductor region 101. The mark 23 is formed by a step between the first impurity semiconductor region 102 and the second impurity semiconductor region 101 in the mixed region 103.

  Hereinafter, a method for manufacturing a solid-state imaging device according to the second embodiment of the present invention will be described with reference to FIG. Note that matters not mentioned in the second embodiment can follow the first embodiment. In the second embodiment, an SOI (Silicon On Insulator) substrate is used as the semiconductor substrate 1. The semiconductor substrate 1 of the second embodiment has an insulating layer 2 inside thereof, has a first semiconductor layer 1 a on the first surface 3 side of the semiconductor substrate 1 when viewed from the insulating layer 2, and extends from the insulating layer 2. As seen, the second semiconductor layer 1 b is provided on the second surface 4 side of the semiconductor substrate 1.

  In the step shown in FIG. 3A, a plurality of circuit elements are formed on the first surface 3 of the SOI substrate as the semiconductor substrate 1 as in the first embodiment, thereby forming an integrated circuit. Here, the circuit element may include, for example, the photoelectric conversion unit 20, a transistor, and a capacitor element. The step of forming the circuit element may include a first implantation step of forming the photoelectric conversion unit 20 in the semiconductor substrate 1 by implanting ions from the first surface 3 side into the semiconductor substrate 1. In the step shown in FIG. 3A, as in the first embodiment, a second implantation step is performed in which ions are implanted into the semiconductor substrate 1 from the first surface 3 side through the opening 400 of the resist pattern 120. To do. Thereby, the mixed region 103 including the first impurity semiconductor region 102 and the second impurity semiconductor region 101 is formed. Here, the second implantation step may be performed so that the mixed region 103 is in contact with the insulating layer 2.

  Next, in the step shown in FIG. 3B, the interlayer insulating layer 220 and the wiring structure 210 are formed as in the step shown in FIG. The wiring structure 210 includes a wiring pattern made of at least one material selected from the group consisting of aluminum, copper, tungsten, and titanium nitride, for example. In the step shown in FIG. 3B, as in the step shown in FIG. 1C, the support substrate 230 is further bonded to the surface of the interlayer insulating layer 220.

  Next, the thinning process shown in FIG. The step shown in FIG. 3C includes a step of polishing the second semiconductor layer 1b of the semiconductor substrate 1 to expose the insulating layer 2 and a step of removing the insulating layer 2 by etching. The step of polishing the second semiconductor layer 1b can be performed by, for example, a mechanical polishing method (MP) or a chemical mechanical polishing method (CMP). The step of removing the insulating layer 2 by etching can be performed, for example, by immersing the semiconductor substrate 1 from which the second semiconductor layer 1b has been removed in a diluted hydrofluoric acid solution (DHF). The insulating layer 2 functions as a polishing stop layer in the step of polishing the second semiconductor layer 1b, which is advantageous in order not to expose the photoelectric conversion unit 20 in the step of polishing the second semiconductor layer 1b. When the mixed region 103 is in contact with the insulating layer 2, the mixed region 103 is exposed by removing the insulating layer 2. When the mixed region 103 is not in contact with the insulating layer 2, the first semiconductor layer 1 a can be etched so that the mixed region 103 is exposed.

  Through the above steps, a structure similar to the structure shown in FIG. In the following, steps similar to those shown in FIGS. 1E and 1F of the first embodiment can be performed.

  In the above-described embodiment, the example in which the first impurity semiconductor region 102 and the second impurity semiconductor region 101 in the mixed region are formed of boron is shown. However, a sufficient difference in etching rate is sufficient in the etching process, and the ion species for forming the first impurity semiconductor region 102 and the second impurity semiconductor region 101 can be arbitrarily set. For example, the first impurity semiconductor region 102 may be formed of arsenic, and the second impurity semiconductor region 101 may be formed of boron.

Claims (8)

Preparing a semiconductor substrate having a first surface and a second surface that are opposite to each other and having a first impurity semiconductor region;
A first implantation step of forming a charge storage portion in the semiconductor substrate by implanting ions from the first surface side into the semiconductor substrate;
Ions are implanted into the semiconductor substrate from the first surface side to form a second impurity semiconductor region, thereby forming a mixed region including the first and second impurity semiconductor regions in the semiconductor substrate. An injection process;
A thinning step of thinning the semiconductor substrate from the second surface side to expose the mixed region;
An etching step of forming a mark having a step in the mixed region by etching the mixed region using an etchant having an etching rate of the first impurity semiconductor region and an etching rate of the second impurity semiconductor region different from each other;
The manufacturing method of the solid-state image sensor characterized by including. In the first implantation step, the charge storage part is formed by implanting ions into the semiconductor substrate including the first impurity semiconductor region, and in the second implantation step, the second impurity semiconductor region is formed. The ions are implanted into the first impurity semiconductor region to form the mixed region including the first impurity semiconductor region and the second impurity semiconductor region.
The manufacturing method of the solid-state image sensor of Claim 1 characterized by the above-mentioned. In the second implantation step, the mixed region is formed so that an end of the mixed region on the second surface side is closer to the second surface than an end of the charge storage unit on the second surface side. Form,
The method for manufacturing a solid-state imaging device according to claim 1 or 2. The semiconductor substrate has an insulating layer therein, has a first semiconductor layer on the first surface side of the insulating layer, and has a second semiconductor layer on the second surface side,
The thinning step includes a step of polishing the second semiconductor layer to expose the insulating layer, and a step of removing the insulating layer by etching.
The method for manufacturing a solid-state imaging device according to any one of claims 1 to 3. In the second implantation step, the mixed region is formed in the first semiconductor layer so that the mixed region is in contact with the insulating layer.
The manufacturing method of the solid-state image sensor of Claim 4 characterized by the above-mentioned. The second implantation step is performed with the ion species being boron or boron difluoride, the dose amount being 1 × 10 ¹⁴ or more and 1 × 10 ¹⁷ cm ⁻² or less, and the acceleration energy being 1 or more and 5 MeV or less.
The method for manufacturing a solid-state imaging device according to claim 1, wherein: In the etching step, as the etchant, (a) a mixture of hydrogen fluoride (HF), nitric acid (HNO ₃ ) and acetic acid (CH ₃ COOH), (b) potassium hydroxide (KOH), isopropyl alcohol (IPA) And a mixture of water and (c) a mixture of ethylenediamine, pyrocatechol and water,
The method for manufacturing a solid-state imaging device according to claim 1, wherein The second injection step is performed after the first injection step.
The method for manufacturing a solid-state imaging device according to claim 1, wherein:

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