JP2005150521A - Imaging apparatus and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent mixing of free electrons between adjacent pixels in a back face irradiation type imaging apparatus of high resolution and high sensitivity. <P>SOLUTION: The imaging apparatus is provided with a semiconductor substrate 114 having at least 2 main surfaces, a photodiode provided on the first main surface (light incident side) of the semiconductor substrate 114, and a reading means (a transfer MOS transistor and a floating diffusion area 110) provided on the second main surface of the semiconductor substrate for reading an electric signal from the photodiode. The photodiode has at least a first semiconductor area 101 of a first conductive type provided on the first main surface, and a second semiconductor area 102 of a second conductive type arranged inside of the semiconductor substrate more than the first semiconductor area. The photodiode and the reading means are surrounded by a third conductor area 112 of the first conductive type arranged inside of the semiconductor substrate extending from the first main surface side of the semiconductor substrate to the second main surface side. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to an imaging device and a method of manufacturing the same, and more specifically, receives an electric signal received on one side (second side) of a semiconductor and photoelectrically converted an electric signal by a photoelectric conversion unit provided on the second side. The present invention relates to a back-illuminated imaging device that is transferred to and read out by a reading means provided on the surface side (first surface side), and a manufacturing method thereof.

  FIG. 52 shows a conventional example disclosed in Patent Document 1, for example, of a back-illuminated imaging device that is one of imaging devices that achieve both high sensitivity and high resolution. In FIG. 52, the P-type semiconductor substrate 12 is set to a thickness of about 10 μm. An N-type CCD (charge transfer device) diffusion layer 13 is provided on the first surface side of the semiconductor substrate 12 for signal charge transfer. In the vicinity of the CCD diffusion layer 13, a multilayer transfer electrode 15 is disposed via a gate oxide film 14. Further, an antireflection film 19 is formed on the side of the semiconductor substrate 12 on which the energy rays are incident (second surface side). Further, a support substrate 21 for obtaining the mechanical strength of the imaging device is provided.

The imaging apparatus having such a configuration is irradiated with energy rays from the second surface side. Electron-hole pairs are generated on the second surface side of the semiconductor substrate 12 by the energy rays. The free electrons move through the semiconductor substrate 12, reach the potential well of the CCD diffusion layer 13, and are accumulated as signal charges. The signal charges in the CCD diffusion layer 13 are transferred by the voltage applied to the transfer electrode 15 and sequentially read out. Reference numeral 17 denotes a charge storage unit, 18 denotes a depletion prevention layer, and 20 denotes an AL pad.
JP 2002-151676 A

  In the conventional back-illuminated imaging device, before free electrons generated on the second surface side in FIG. 52 move through the semiconductor substrate 12 and reach the CCD diffusion layer 13, they are mixed between adjacent pixels, As a result, there is a problem that smear is likely to occur. Such smearing is a serious adverse effect on reducing the pixel pitch and increasing the number of pixels in the imaging apparatus to improve the resolution. In particular, short wavelength energy rays such as blue generate electron-hole pairs in a very shallow region on the second surface side. Therefore, in the case of an energy beam with a short wavelength, the moving distance of free electrons is particularly long, and the above problem is more likely to occur. In the conventional example described in Patent Document 1, a P-type buried channel stop layer 17a having a concentration higher than that of the semiconductor substrate 12 is introduced as a countermeasure. However, between the channel stop layer 17a and the CCD diffusion layer 13 is introduced. Therefore, it is difficult to completely prevent free electrons from being mixed between adjacent pixels during charge transfer in the vertical direction from the charge transfer unit 17 to the CCD diffusion layer 13. Also, if the channel stop layer 17a and the CCD diffusion layer 13 are brought into contact with each other and the adjacent pixels are electrically isolated from each other, the image quality can be improved by increasing the reverse current between the two during CCD charge transfer. There is a problem of deterioration.

  In view of the above problems, an object of the present invention is to provide a high-resolution, high-sensitivity back-illuminated imaging device that generates less smear.

An imaging device according to the present invention comprises a semiconductor substrate having at least two main surfaces;
Photoelectric conversion means provided on the first main surface of the semiconductor substrate;
A reading means for reading an electrical signal from the photoelectric conversion means provided on the second main surface of the semiconductor substrate;
Wiring means connected to the readout means and provided on the semiconductor substrate,
The photoelectric conversion means includes at least a first-conductivity-type first semiconductor region provided on the first main surface, and a second-conductivity-type first semiconductor region disposed inside the semiconductor substrate with respect to the first semiconductor region. In an imaging device having two semiconductor regions,
The photoelectric conversion means and the reading means are surrounded by a third semiconductor region of the first conductivity type disposed inside the semiconductor substrate from the first main surface side to the second main surface side of the semiconductor substrate. It is characterized by.

An imaging device of the present invention includes a semiconductor substrate having at least two main surfaces,
Photoelectric conversion means provided on the first main surface of the semiconductor substrate;
A reading means for reading an electrical signal from the photoelectric conversion means provided on the second main surface of the semiconductor substrate;
Wiring means connected to the readout means and provided on the semiconductor substrate,
The photoelectric conversion means includes at least a first-conductivity-type first semiconductor region provided on the first main surface, and a second-conductivity-type first semiconductor region disposed inside the semiconductor substrate with respect to the first semiconductor region. In an imaging device having two semiconductor regions,
The photoelectric conversion means and the readout means are surrounded by an insulating material region disposed inside the semiconductor substrate from the first main surface side to the second main surface side of the semiconductor substrate. And

In the method of manufacturing an imaging device according to the present invention, a first conductive type first semiconductor region to be a photoelectric conversion unit and a second conductive type second semiconductor region in contact with the first semiconductor region are formed on a semiconductor substrate. A first step of
A second step of forming a third semiconductor region of a first conductivity type in contact with the second semiconductor region;
A reading means for reading an electrical signal from the photoelectric conversion means is formed in the third semiconductor region, surrounds the periphery of the reading means and the photoelectric conversion means, and extends from the surface of the third semiconductor region to the second semiconductor region. Forming a fourth semiconductor region of the first conductivity type over one semiconductor region, and the first semiconductor region and the second semiconductor region on the semiconductor substrate by the first to third steps. Forming a semiconductor substrate including a third semiconductor region and a fourth semiconductor region;
A fourth step of forming a wiring connected to the reading means on the third semiconductor region;
A fifth step of bonding the semiconductor substrate on which the wiring is formed to a support substrate;
A sixth step of separating or removing the semiconductor substrate;
It is characterized by having.

  As described above, according to the present invention, it is possible to effectively prevent mixing of free electrons between adjacent pixels, and a high-resolution and high-sensitivity back-illuminated imaging device with less smear is realized.

  In the imaging apparatus according to the present invention, photoelectric conversion means such as a photodiode is formed on the second main surface side of the semiconductor substrate, and readout means such as an insulated gate transistor for reading the signal charge generated there is provided as the first main signal of the semiconductor substrate. A pixel separation region that is formed on the surface side so that signal charges do not leak to adjacent pixels is disposed between the pixels so as to surround the photoelectric conversion unit and the readout unit, and an electrical signal read from the readout unit is The pixel is output to the outside through a wiring different from the semiconductor layer, and the readout means and the photoelectric conversion means are arranged separately on the first main surface side and the second surface side of the semiconductor layer. The aperture ratio of the photodiode can be increased and high sensitivity can be obtained.

  Furthermore, since the pixel pitch can be reduced without reducing the size of the semiconductor element, high resolution can be realized at low cost and high yield. Further, this configuration relaxes the restrictions on the dimensions of the wiring and reduces the probability of occurrence of wiring disconnection or short-circuiting between wirings, which also enables high yield.

  Further, by arranging the reading means and the photodiode separately on the first main surface side and the second main surface side of the semiconductor layer, the area of the capacitive element constituting the reading means is not restricted by the opening of the photodiode. Can be bigger. This increases the signal capacity and increases the dynamic range. Further, since the ratio of the peripheral length to the area of the capacitive element can be reduced, the S / N ratio against noise due to dark current generated in the peripheral area of the capacitive element is improved, and the S / N of the sensor can be improved. In addition, since the signal charge in the capacitive element is less deteriorated, the electronic shutter function of simultaneously transferring the signal charge of all the photodiodes to the capacitive element and then sequentially reading out the signal charge of each capacitive element is achieved with a high S / N can be realized while securing N.

  Furthermore, the pixel separation region disposed between adjacent pixels can prevent mixing of signal charges generated by the photoelectric conversion means between the pixels, and even when the pixel pitch is narrowed to achieve high resolution, smearing is extremely high. A small high-quality image can be obtained.

  In addition, the high concentration layer provided on the second main surface side surface functions as an etching stop and a photo diode depletion prevention layer when etching the silicon substrate. The latter contributes to improvement, and the latter can obtain a low-noise and high-quality image by preventing the dark current generated on the semiconductor surface from being mixed into the signal charge. The surface protective film provided on the second main surface side of the semiconductor layer also has a function as an antireflection film for incident light by adjusting the optical film thickness.

  Further, according to the present invention, it is possible to reduce the width of the pixel isolation region by forming the pixel isolation region by a plurality of ion implantation processes. Thereby, the aperture ratio of the pixel is further expanded, and the sensitivity of the imaging device can be further improved. Furthermore, the pixel pitch can be reduced and the resolution can be improved.

  According to the third embodiment of the present invention, the process margin of the etching process in the silicon substrate etching can be increased, and the process can be stabilized and the process yield can be improved. Moreover, since the uniformity of the film thickness of the semiconductor layer can be improved, a high-quality image can be obtained.

  Further, according to the present invention, by using a high-quality silicon oxide film as a protective film for the light receiving surface, it is possible to suppress the generation of dark current generated on the surface of the light receiving surface and to obtain a high-quality image with low noise. it can. Further, the reliability is improved by the excellent durability of the surface protective film.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a cross-sectional structure diagram of one pixel of an imaging apparatus that best represents the features of the present invention. In FIG. 1, a photodiode n-layer 102 serving as a photoelectric conversion means, a photodiode p-layer 101, a p-layer 105 having a thickened surface of the photodiode p-layer 101, a p-layer for forming the photodiode p-layer, and an element well. A well 103 of a type, a gate region 107 of a transfer MOS transistor serving as a reading means formed on the well 103 via an insulating layer 109, and a source region of the transfer MOS transistor formed on one side of the gate region 107. In addition, an n-type signal charge transfer path 111 connected to the n-layer 102 of the photodiode, and an n-type diffusion floating region formed as a drain region of the transfer MOS transistor under the other side surface of the gate region 107 of the transfer MOS transistor 110 and an n-type electric field relaxation region 108. Note that adjacent pixels are partitioned by a p-type pixel isolation region 112.

  The diffusion floating region 110 is connected to the gate of the amplification MOS transistor 122 of the output circuit. The drain of the row selection switch MOS transistor 123 is connected to the source of the amplification MOS transistor 122. A current source 124 serving as a load of the amplifying MOS transistor is connected to the source to constitute a source follower amplifier circuit, and an electric signal from the pixel is output from the output terminal 125.

  The diffusion floating region 110 is connected to the reset MOS transistor 120 for resetting the diffusion floating region 110, and the drain is connected to the reset power source 121.

  Further, 106 is a surface protective film of the photodiode, 104 is a field oxide film for element isolation, and 113 is a support substrate for obtaining the mechanical strength of the imaging apparatus. Although not shown in FIG. 1, wirings for connecting semiconductor elements and transmitting signals are provided on the side where the field oxide film 104 is formed (the first main layer of the semiconductor layer 114 serving as a semiconductor substrate). Surface side) and the support substrate 113.

  FIG. 2 is a plan view of the semiconductor layer 114 on the first main surface side. One pixel is composed of a signal charge transfer path 111 as a reading means, a gate region 107 of a transfer MOS transistor, a diffusion floating region 110, a reset MOS transistor 120, an amplification MOS transistor 122, and a row selection switch MOS transistor 123. Each of the plurality of pixels is electrically separated by the pixel separation region 112. This plan view is a drawing in which semiconductor elements are connected and wiring for transmitting signals is omitted.

  FIG. 3 is a plan view of the second main surface, which is the surface on which the semiconductor layer 114 photodiode is formed. This figure shows a plan view of a surface where the n-layer 102 and the pixel isolation region 112 of the photodiode are on the same plane. A photodiode is formed for each pixel, and each pixel is electrically isolated by a pixel isolation region 112.

  Next, the reading operation of the imaging apparatus will be described. Light enters from the surface protective film 106 side of the photodiode (the second main surface side of the semiconductor layer 114), and electrons generated by photoelectric conversion accumulate in the n layer 102 of the photodiode. In addition, holes formed by photoelectric conversion are discharged through the p-type pixel isolation region 112 fixed to the ground potential 126, the p-layer 101 of the photodiode, and the high-concentration p-layer 105. At this time, the transfer MOS transistor is in an OFF state. After a predetermined accumulation time has elapsed, a positive voltage is applied to the control electrode (gate region) 107 of the transfer MOS transistor to turn on the transfer MOS transistor, and the accumulated charge in the n-layer 102 of the photodiode is transferred to the diffusion floating region 110. Forward. Before the transfer MOS transistor is turned on, the reset MOS transistor 120 is turned on in advance to reset the diffusion floating region 110 to a predetermined voltage. When the accumulated charge is transferred to the diffusion floating region 110, the transfer charge Qsig and the diffusion floating capacitance CFD are used as the voltage of the diffusion floating region 110. Since the transfer charge is an electron, the voltage corresponding to Qsig / CFD becomes the reset voltage. Decrease from If the storage layer of the photodiode is p-type, since the transfer charge is a hole, the voltage rises conversely.

In such a photoelectric conversion device, it is important to read out the signal charge accumulated in the n-layer 102 of the photodiode at a higher rate in order to achieve a high noise removal rate.
More specifically, if the voltage of the diffusion floating region 110 that is lowered by the voltage of Qsig / CFD from the reset voltage after reading the signal is VFDsig1, and the transfer MOS transistor is in a sufficiently ON state, the n-layer 102 of the photodiode is applied. The reverse bias of VFDsig1 is applied to the GND potential of the p-type well 103 and the deep p-layer 105 on the surface. At this time, a depletion layer extends from the p-type well 103 and the deep p-layer 105 to the n-layer 102, and the entire n-layer 102 of the photodiode is depleted, thereby diffusing and floating with almost no signal charge remaining in the photodiode. The signal charge can be read out to the region 110.

  In this case, the photodiode is reset at the same time as the signal charge is read out to the diffusion floating region 110. If the number of electrons remaining in the n layer is zero after reading, that is, when the reverse bias of VFDsig1 is applied to the n layer 102 of the photodiode, it is superimposed on the output signal Vr1 and the reset signal immediately after reset by Qsig / CFD. By taking the difference from the output signal Vsig1, the reset noise can be completely removed, and an output signal of Vsig1−Vr1 = Qsig / CFD × A (A is the gain of the output circuit for each pixel) can be obtained. it can.

A feature of the present embodiment is that a photodiode is formed on the second main surface side of the semiconductor layer 114, and reading means (here, a transfer MOS transistor) for reading the signal charge generated there is provided on the first main surface of the semiconductor layer 114. The pixel separation region 112 is formed between the pixels so as to surround the photodiode and the reading unit, and an electric signal read from the reading unit is transmitted from each pixel to the semiconductor layer. 114 is configured to output to the outside via a different wiring.
By arranging the reading means and the photodiode separately on the first main surface side and the second main surface side of the semiconductor layer 114, the aperture ratio of the photodiode can be increased, and high sensitivity can be obtained. Furthermore, since the pixel pitch can be reduced without reducing the size of the semiconductor element, high resolution can be realized at low cost and high yield. Further, this configuration relaxes the restrictions on the dimensions of the wiring and reduces the probability of occurrence of wiring disconnection or short-circuiting between wirings, which also enables high yield.

  Further, by arranging the reading means and the photodiode separately on the first main surface side and the second main surface side of the semiconductor layer 114, the area of the diffusion floating region 110 constituting the reading means can be limited by the opening of the photodiode. Can be enlarged without receiving. Thereby, the signal capacity of the diffusion floating region 110 is increased, and the dynamic range can be increased. Further, since the ratio of the peripheral length to the area of the diffusion floating region 110 is reduced, the S / N ratio against noise due to dark current generated in the peripheral region of the diffusion floating region 110 is improved, and the S / N of the sensor can be improved. . Furthermore, since there is little deterioration of the signal charge in the diffusion floating region 110, the function of the electronic shutter is such that the signal charges of all the photodiodes are transferred to the diffusion floating region 110 at the same time, and then the signals of each diffusion floating region 110 are sequentially read out. Can be realized while ensuring high S / N.

  Furthermore, the pixel separation region 112 disposed between adjacent pixels can prevent signal charges generated by the photodiode from being mixed between pixels, and the smear is extremely small even when the pixel pitch is narrowed to achieve high resolution. A high-quality image can be obtained.

  In addition, the p-type high concentration layer 105 provided on the second main surface side functions as an etching stop and a photo diode depletion prevention layer during the etching of the silicon substrate, and the former makes the thickness of the semiconductor layer 114 uniform. The latter contributes to the improvement of image quality, and the latter can obtain a low-noise and high-quality image by preventing the dark current generated on the semiconductor surface from being mixed into the signal charge. The surface protective film 106 provided on the second main surface side of the semiconductor layer 114 also has a function as an antireflection film for incident light by adjusting the optical film thickness.

  In the above, the case where electrons are accumulated has been described as an example. However, the present invention can also be applied to the case where holes are accumulated, and the types of accumulated charges and transfer MOS transistors are also applicable. It is not limited. Furthermore, semiconductor switching elements used for reading means such as stored charge transfer switches are not limited to MOS transistors, and semiconductor switching elements such as bipolar transistors can also be applied.

A first embodiment of the present invention will be described with reference to FIGS. A step used as an alignment mark in a later step is formed on a part of the surface of the p-type silicon substrate 201 having a concentration of 1 × 10 ¹⁸ cm ⁻³ or less using a difference in etching and oxidation rate (not shown). ). This alignment mark is used not only for the subsequent semiconductor process, but also as an alignment mark for forming a color filter and a microlens on the light receiving surface. Boron is introduced into the surface of the p-type substrate 201 where the step is formed by ion implantation (ion implantation) or boron diffusion from boron-containing glass, and heat treatment is performed, so that the concentration is about 5 × 10 ¹⁹ cm ⁻³ or more. A p-type high concentration layer 202 is formed (FIG. 4).

Further, a p-type epitaxial layer 203 of about 2 × 10 ¹⁶ cm ⁻³ and an n-type epitaxial layer 204 of about 1 × 10 ¹⁷ cm ⁻³ are formed. The thicknesses of the p-type high-concentration layer 202 and the p-type epitaxial layer 203 are adjusted to a thickness that allows the light having a wavelength to be detected by the imaging device to be sufficiently transmitted. Further, the thickness of the n-type epitaxial layer 204 is adjusted to a film thickness that sufficiently attenuates light having a wavelength to be detected by the imaging apparatus. When the wavelength to be detected is in the visible light region, a film thickness of about several thousand angstroms to about 15 μm is appropriate (FIG. 5).

Next, boron is introduced using ion implantation, heat treatment is performed, and a p-type well layer 205 having a concentration of about 1 × 10 ¹⁶ cm ⁻³ is formed. Subsequently, a photoresist process, an ion implantation (ion implantation) process, repeating an oxidation process to form a concentration of about 1 × ¹⁰ 18 ^{cm -3} of p-type channel stop layer 206, field oxide film 207, the concentration about 1 × ¹⁰ 18 ^{cm -3} of p-type channel stop layer 208. Since the p-type channel stop layer 208 is necessary until its impurity profile reaches the p-type epitaxial layer 203, depending on the film thickness of the epitaxial layer, a corresponding high energy implantation is required for the ion implantation process. In some cases, the injection energy is changed and injection is performed a plurality of times (FIG. 6).

  Further, in accordance with a normal semiconductor manufacturing process, the gate oxide film 209, the gate electrode 210, the n-type electric field relaxation region 211, the signal charge transfer path 212, the p-type depletion prevention layer 213, the n-type source / drain region 214, the n-type A diffusion floating region 230 is formed. Here, the photodiode is formed by an n-type epitaxial layer 204, a p-type semiconductor layer 203 in contact therewith, a p-type well layer 205, a p-type channel stop layer 208, and a depletion blocking layer 213. The signal charge transfer path 212 is formed so that the signal charge can be completely transferred by providing an n-type concentration profile under the gate electrode by oblique implantation of ion implantation using the gate electrode 210 as a mask (FIG. 7).

  Thereafter, in accordance with a normal semiconductor manufacturing process, the first interlayer insulating film 215, the contact 216, the first metal wiring 217, the second interlayer insulating film 218, and the via that connects the first metal wiring 217 and the second metal wiring 220. 219, a second metal wiring 220, a third interlayer insulating film 221, a via 222 connecting the second metal wiring 220 and the third metal wiring 223, a third metal wiring 223, and a passivation film 224 are sequentially formed (FIG. 8). .

  Next, the support substrate 225 and the surface side (first main surface side) on which the wiring layer of the semiconductor substrate is formed are bonded using a resin. The material of the support substrate 225 is insulative, and the thermal expansion coefficient up to about 500 ° C. is the same as that of the Si substrate 201. The support substrate 225 can withstand an etchant during subsequent Si substrate etching, and further mounting processes such as dicing later. It is required to have mechanical strength that can withstand. Furthermore, it is more desirable that the imaging apparatus has a light shielding property with respect to a target wavelength. On the other hand, the resin used for bonding is insulative, similar to that required for the support substrate 225, and has a thermal expansion coefficient up to about 500 ° C., which is the same as that of the Si substrate. It is required to have endurance, to have an adhesive strength that can withstand a subsequent mounting process, to have no problem in reliability of the adhesive strength, and more desirably to have a light-shielding property with respect to a target wavelength. In addition, as long as it has this characteristic, it is not limited to resin (FIG. 9).

  Next, the semiconductor substrate 201 is selectively removed by alkali wet etching. Examples of the etchant include TMAH (tetramethylammonium hydroxide), a mixed solution of KOH (potassium hydroxide), water and IPA (isopropyl alcohol), or EPW (ethylenediamine / pyrocatechol / water). Each etchant has a selection ratio between low-concentration p-type Si and high-concentration p-type Si. In etching of the silicon substrate 201, the p-type high-concentration layer 202 serves as an etching stop, and the semiconductor layer 227 serving as a semiconductor substrate is formed. The thickness is controlled with high accuracy. The etch rate ratio (p− / p +) between p− and p + of each etchant at 80 ° C. is about 10 for TMAH, about 200 for a KOH / water / IPA mixture, and about 1000 for EPW. When used, the semiconductor layer 227 has the best film thickness controllability. Note that the alignment step on the silicon substrate formed in the description of FIG. 4 is maintained as it is on the second main surface side because the concentration profile of high-concentration boron traces the step shape. It can be used in the filter and microlens formation process (FIG. 10).

  After the etching of the silicon substrate, the light receiving surface is oxidized at a temperature of 500 ° C. or lower in a wet atmosphere to form a silicon oxide protective film 226 (FIG. 11).

  Further, although not shown, an infrared cut filter, a color filter, or a microlens can be formed on the surface of the protective film 226. When forming a color filter or a micro lens, high-precision alignment is required for the photodiode. Here, by using the alignment mark carved on the second main surface side described above, high-accuracy alignment is possible.

  The feature of this embodiment is that a photodiode is formed on the second main surface side of the semiconductor layer 227, and a means for reading the signal charge generated there is formed on the first main surface side of the semiconductor layer 227, so that the signal charge is adjacent. A pixel isolation region 208 is disposed between the pixels so as not to leak into the pixels to surround the photodiode and the reading unit, and an electric signal read from the reading unit is externally transmitted from each pixel through a wiring different from that of the semiconductor layer 227. This is a configuration that outputs.

  By arranging the reading means and the photodiode separately on the first main surface side and the second main surface side of the semiconductor layer 227, the aperture ratio of the photodiode can be increased and high sensitivity can be obtained. Furthermore, since the pixel pitch can be reduced without reducing the size of the semiconductor element, high resolution can be realized at low cost and high yield. Further, this configuration relaxes the restrictions on the dimensions of the wiring and reduces the probability of occurrence of wiring disconnection or short-circuiting between wirings, which also enables high yield.

  Furthermore, the pixel separation region 208 arranged between adjacent pixels can prevent mixing of signal charges generated by the photodiodes between the pixels, and the smear is extremely small even when the pixel pitch is narrowed to achieve high resolution. A high-quality image can be obtained.

  In addition, the p-type high concentration layer 202 provided on the second main surface side functions as an etching stop and a photo diode depletion prevention layer during the etching of the silicon substrate, and the former makes the thickness of the semiconductor layer 227 uniform. The latter contributes to the improvement of image quality, and the latter can obtain a low-noise and high-quality image by preventing the dark current generated on the semiconductor surface from being mixed into the signal charge. The surface protective film 226 provided on the second main surface side of the semiconductor layer 227 also has an optical function such as antireflection of incident light by adjusting its refractive index and film thickness.

  In the above, the case where electrons are accumulated has been described as an example, but this embodiment can also be applied to the case where holes are accumulated. It is not limited. Furthermore, semiconductor switching elements used for reading means such as stored charge transfer switches are not limited to MOS transistors, and semiconductor switching elements such as bipolar transistors can also be applied.

A second embodiment of the present invention will be described with reference to FIGS. A step used as an alignment mark in a later step is formed on a part of the surface of the p-type silicon substrate 201 having a concentration of 1 × 10 ¹⁸ cm ⁻³ or less using a difference in etching and oxidation rate (not shown). ). This alignment mark is used not only for the subsequent semiconductor process, but also as an alignment mark for forming a color filter and a microlens on the light receiving surface. Boron is introduced into the surface of the p-type substrate 201 where the step is formed by ion implantation or boron diffusion from boron-containing glass and heat treatment is performed, and a p-type high concentration having a concentration of about 5 × 10 ¹⁹ cm ⁻³ or more. Layer 202 is formed (FIG. 12).

Further, a p-type epitaxial layer 203 of about 2 × 10 ¹⁶ cm ⁻³ and an n-type epitaxial layer 204 of about 1 × 10 ¹⁷ cm ⁻³ are formed. The thicknesses of the p-type high-concentration layer 202 and the p-type epitaxial layer 203 are adjusted to a thickness that allows the light having a wavelength to be detected by the imaging device to be sufficiently transmitted. The n-type epitaxial layer 204 is formed to be thinner than the finally required n-type epitaxial layer. Subsequently, a pixel isolation region 208 is formed by using resist patterning and ion implantation (FIG. 13).

  Further, an n-type epitaxial layer 204 is additionally formed. The film thickness is made thinner than the finally required n-type epitaxial layer (FIG. 14).

  Subsequently, a pixel isolation region 208 is additionally formed using resist patterning and ion implantation (FIG. 15).

  Furthermore, the film thickness of the n-type epitaxial layer 204 finally requires an additional film-forming process of the n-type epitaxial layer 204 and an additional formation process of the pixel isolation region 208 using resist patterning and ion implantation. Repeat several times until the film thickness is reached (FIG. 16).

  Thereafter, the final structure of the imaging device is obtained by the same process as in the first embodiment (FIGS. 17 to 22).

  The feature of this embodiment is that the formation process of the n-type epitaxial layer 204 and the pixel isolation region 208 is repeated a plurality of times. By reducing the film thickness of the n-type epitaxial layer 204 in forming the pixel isolation region 208, the acceleration energy of ion implantation can be lowered. This means that the photoresist film thickness of the masking material at the time of ion implantation can be reduced, which facilitates fine patterning of the photoresist, that is, the width of the pixel isolation region 208 can be reduced. . Thereby, the aperture ratio of the pixel is further expanded, and the sensitivity of the imaging device can be further improved. Furthermore, the pixel pitch can be reduced and the resolution can be improved.

  Note that the reading means and the photodiode are arranged separately on the first main surface side and the second main surface side of the semiconductor layer 227, whereby the aperture ratio of the photodiode can be increased and high sensitivity can be obtained. . Furthermore, since the pixel pitch can be reduced without reducing the size of the semiconductor element, high resolution can be realized at low cost and high yield. Further, this configuration relaxes the restrictions on the dimensions of the wiring and reduces the probability of occurrence of wiring disconnection or short-circuiting between wirings, which also enables high yield.

  In addition, the p-type high concentration layer 202 provided on the second main surface side functions as an etching stop and a photo diode depletion prevention layer during the etching of the silicon substrate, and the former makes the thickness of the semiconductor layer 227 uniform. The latter contributes to the improvement of image quality, and the latter can obtain a low-noise and high-quality image by preventing the dark current generated on the semiconductor surface from being mixed into the signal charge. The surface protective film 226 provided on the second main surface side of the semiconductor layer 227 also has an optical function such as antireflection of incident light by adjusting its refractive index and film thickness.

  In the above, the case where electrons are accumulated has been described as an example, but this embodiment can also be applied to the case where holes are accumulated. It is not limited. Furthermore, semiconductor switching elements used for reading means such as stored charge transfer switches are not limited to MOS transistors, and semiconductor switching elements such as bipolar transistors can also be applied.

A third embodiment of the present invention will be described with reference to FIGS. A step used as an alignment mark in a later step is formed on a part of the surface of the p-type silicon substrate 201 having a concentration of 1 × 10 ¹⁶ cm ⁻³ or more using a difference in etching and oxidation rate (not shown). ). This alignment mark is used not only for the subsequent semiconductor process, but also as an alignment mark for forming a color filter and a microlens on the light receiving surface. A porous layer 240 is formed on the surface of the p-type substrate 201 where the step is formed by anodizing in a hydrofluoric acid solution. Here, it is preferable that the concentration of hydrofluoric acid is 10% or more from the viewpoint of making porous. As the amount of current flowing at the time of anodization is appropriately determined by the state or the like of the thickness or porous layer surface of the porous layer to be hydrofluoric acid concentration and the desired, preferably in the range of 1mA ^/ cm ² ~100mA / cm 2 It is. Also, by adding alcohol such as ethyl alcohol to the solution, reaction product gas bubbles generated during anodization can be removed from the reaction surface without instantaneous stirring, and a porous silicon layer can be formed uniformly and efficiently. Can do. The amount of alcohol to be added is appropriately determined depending on the concentration of hydrofluoric acid, the desired thickness of the porous layer, or the surface state of the porous layer. In addition, when the porous layer is made porous, the formation current level is changed from a low level to a high level in the middle, for example, so that the porous layer 240 has a change in density (change in the proportion of pores in the layer). Thus, it can be controlled so that the porous layer is easily separated in a later step (FIG. 23). Porous silicon was discovered by Uhlir et al. In 1956 in the research process of electrolytic polishing of semiconductors (A. Uhlir, Bell Syst. Tech. J., vol. 35, 333 (1956)).

Subsequently, a p-type high concentration layer 202 having a concentration of 2 × 10 ¹⁷ cm ⁻³ or more is formed on the surface of the porous layer 240 by epitaxial growth. Further, a p-type epitaxial layer 203 of about 2 × 10 ¹⁶ cm ⁻³ and an n-type epitaxial layer 204 of about 1 × 10 ¹⁷ cm ⁻³ are formed. The thicknesses of the p-type high-concentration layer 202 and the p-type epitaxial layer 203 are adjusted to a thickness that allows the light having a wavelength to be detected by the imaging device to be sufficiently transmitted. Further, the thickness of the n-type epitaxial layer 204 is adjusted to a film thickness that sufficiently attenuates light having a wavelength to be detected by the imaging apparatus. When the wavelength to be detected is in the visible light region, a film thickness of about several thousand angstroms to about 15 μm is appropriate (FIG. 24).

Next, boron is introduced using ion implantation, heat treatment is performed, and a p-type well layer 205 having a concentration of about 1 × 10 ¹⁶ cm ⁻³ is formed. Subsequently, a photoresist process, an ion implantation process, and an oxidation process are repeated. to form a concentration of about 1 × ¹⁰ 18 ^{cm -3} of p-type channel stop layer 206, field oxide film 207, the concentration about 1 × ¹⁰ 18 ^{cm -3} of p-type channel stop layer 208. Since the p-type channel stop layer 208 is necessary until its impurity profile reaches the p-type epitaxial layer 203, depending on the film thickness of the epitaxial layer, a corresponding high energy implantation is required for the ion implantation process. In some cases, multiple injections are required with different injection energies. Alternatively, the p-type channel stop layer 208 can be formed by the method described in the second embodiment (FIG. 25).

  Further, in accordance with a normal semiconductor manufacturing process, the gate oxide film 209, the gate electrode 210, the n-type electric field relaxation region 211, the signal charge transfer path 212, the p-type depletion prevention layer 213, the n-type source / drain region 214, the n-type A diffusion floating region 230 is formed. Here, the photodiode is formed of an n-type epitaxial layer 204, a p-type semiconductor layer 203 in contact therewith, a p-type well layer 205, a p-type channel stop layer 208, and a p-type depletion blocking layer 213. The signal charge transfer path 212 is formed so that the signal charge can be completely transferred by providing an n-type concentration profile under the gate electrode by oblique implantation of ion implantation using the gate electrode 210 as a mask (FIG. 26).

  Thereafter, in accordance with a normal semiconductor manufacturing process, the first interlayer insulating film 215, the contact 216, the first metal wiring 217, the second interlayer insulating film 218, and the via that connects the first metal wiring 217 and the second metal wiring 220. 219, a second metal wiring 220, a third interlayer insulating film 221, a via 222 connecting the second metal wiring 220 and the third metal wiring 223, a third metal wiring 223, and a passivation film 224 are sequentially formed (FIG. 27). .

  Next, the support substrate 225 and the surface side (first main surface side) on which the wiring layer of the semiconductor substrate is formed are bonded using a resin. The material of the support substrate 225 is insulative, and the thermal expansion coefficient up to about 500 ° C. is the same as that of the Si substrate 201. The support substrate 225 can withstand an etchant during subsequent Si substrate etching, and further mounting processes such as dicing later. It is required to have mechanical strength that can withstand. Furthermore, it is more desirable that the imaging apparatus has a light shielding property with respect to a target wavelength. On the other hand, the resin used for bonding is insulative, similar to that required for the support substrate, has a thermal expansion coefficient up to about 500 ° C., and is resistant to an etchant during subsequent etching of the Si substrate. In addition, it is required to have an adhesive strength that can withstand a subsequent mounting process, to have no problem in reliability of the adhesive strength, and more desirably to have a light-shielding property with respect to a target wavelength. In addition, if it has this characteristic, it will not be limited to resin (FIG. 28).

  Next, by applying a force to the support substrate 225 or the silicon substrate 201, the porous layer 240 is separated at a fragile portion in the porous layer 240. Alternatively, the silicon substrate 201 is removed until the porous layer 240 is exposed by grinding, polishing, or wet etching of the silicon substrate 201 (FIG. 29).

  Subsequently, the porous layer 240 exposed on the surface is selectively removed by etching. For etching, hydrofluoric acid, which is a selective etching solution for porous silicon, or a mixed solution in which at least one of alcohol and hydrogen peroxide is added to hydrofluoric acid, or alcohol and buffered hydrofluoric acid are added to buffered hydrofluoric acid. At least one kind of mixed solution to which at least one of hydrogen peroxide water is added is used. For example, when etching is performed with stirring in a mixed solution of 49% hydrofluoric acid and 30% hydrogen peroxide (1: 5), the etching rate with respect to single crystal silicon is extremely low, and the selectivity with respect to the etching rate of the porous layer Reaches a power of ten or more, and the etching amount (about several tens of angstroms) in the p-type high-concentration layer 202 grown as a single crystal by epitaxial growth is practically negligible (FIG. 30).

  After removing the porous layer 240 by etching, the light-receiving surface is oxidized at a temperature of 500 ° C. or lower in a wet atmosphere to form a silicon oxide protective film 226 (FIG. 31).

Further, although not shown, an infrared cut filter, a color filter, or a microlens can be formed on the surface of the protective film 226. When forming a color filter or a micro lens, high-precision alignment is required for the photodiode. Here, since the alignment step on the silicon substrate formed in the description of FIG. 23 is transferred as it is to the p-type high concentration layer 202 formed by epitaxial growth, a color filter and microlens formation step is used by using this. High-precision alignment is possible.
The feature of this embodiment is that selective etching of porous silicon and single crystal silicon is used when the silicon substrate 201 is removed and the thin film semiconductor layer 227 is formed. Since single crystal silicon works very effectively as an etching stopper, the porous silicon etching process becomes very easy. In other words, since the overetching of the porous silicon etching can be increased, the etching residue of the porous silicon can be prevented, and the margin of the temperature management, time management, etc. of the etching process can be increased, the process can be stabilized, Yield improvement can be realized. In addition, since the uniformity of the film thickness of the semiconductor layer 227 can be improved, a high-quality image can be obtained.

  Note that the reading means and the photodiode are arranged separately on the first main surface side and the second main surface side of the semiconductor layer 227, whereby the aperture ratio of the photodiode can be increased and high sensitivity can be obtained. . Furthermore, since the pixel pitch can be reduced without reducing the size of the semiconductor element, high resolution can be realized at low cost and high yield. Further, this configuration relaxes the restrictions on the dimensions of the wiring and reduces the probability of occurrence of wiring disconnection or short-circuiting between wirings, which also enables high yield.

  The p-type high concentration layer 202 provided on the second main surface side functions as a depletion prevention layer of the photodiode, and prevents dark current generated on the semiconductor surface from being mixed into the signal charge. It is possible to obtain a low-noise high-quality image. The surface protective film 226 provided on the second main surface side of the semiconductor layer 227 also has an optical function such as antireflection of incident light by adjusting its refractive index and film thickness.

  In the above, the case where electrons are accumulated has been described as an example, but this embodiment can also be applied to the case where holes are accumulated. It is not limited. Furthermore, semiconductor switching elements used for reading means such as stored charge transfer switches are not limited to MOS transistors, and semiconductor switching elements such as bipolar transistors can also be applied.

  A fourth embodiment of the present invention will be described with reference to FIGS. In this embodiment, an SOI substrate (in this application, SOI means Semiconductor On Insulator, and a semiconductor material other than silicon can be used, but in this embodiment, a silicon on insulator is used) is used as a silicon substrate. . There are SIMOX, ELTRAN, and the like depending on the manufacturing method of the SOI substrate, but the type is not particularly limited as long as it is an SOI structure substrate. SIMOX is a method first reported by K. Izumi. After oxygen ions are implanted into the Si wafer, high temperature annealing is performed in an argon / oxygen atmosphere, so that the oxygen ions are combined with Si and oxidized in the Si wafer. A Si layer is formed. In ELTRAN, a silicon substrate is made porous, a non-porous layer is formed on the formed porous layer, bonded to another substrate through an insulating layer, and then separated by the porous layer. This is a method disclosed in Japanese Patent Laid-Open No. 7-302889 and the like, in which a non-porous layer is transferred to the side.

Here, 250 is a silicon substrate, 251 is a buried oxide film, and 252 is an SOI layer. The buried oxide film layer 251 later functions as a protective film for the light receiving portion and is also expected to function as an antireflection film for incident light. Therefore, the thickness of the buried oxide film layer 251 reflects the wavelength of light that is to be detected by the imaging device. It is desirable to set the film thickness to satisfy the prevention condition. A part of the SOI layer 252 is removed by etching until the buried oxide film 251 is exposed, and a step used as an alignment mark in a later process is formed (not shown). This alignment mark is used not only for the subsequent semiconductor process, but also as an alignment mark for forming a color filter and a microlens on the light receiving surface. Boron is introduced into the SOI layer 252 by ion implantation or boron diffusion from a boron-containing glass and heat treatment is performed to form a p-type high concentration layer having a concentration of about 2 × 10 ¹⁷ cm ⁻³ or more (FIG. 32).

Subsequently, a p-type epitaxial layer 203 of about 2 × 10 ¹⁶ cm ⁻³ and an n-type epitaxial layer 204 of about 1 × 10 ¹⁷ cm ⁻³ are formed on the SOI layer 252. The thicknesses of the p-type high-concentration SOI layer 252 and the p-type epitaxial layer 203 are adjusted to a thickness that allows the light having a wavelength to be detected by the imaging device to be sufficiently transmitted. Further, the thickness of the n-type epitaxial layer 204 is adjusted to a film thickness that sufficiently attenuates light having a wavelength to be detected by the imaging apparatus. When the wavelength to be detected is in the visible light region, a film thickness of about several thousand angstroms to about 15 μm is appropriate (FIG. 33).

Next, boron is introduced using ion implantation, heat treatment is performed, and a p-type well layer 205 having a concentration of about 1 × 10 ¹⁶ cm ⁻³ is formed. Subsequently, a photoresist process, an ion implantation process, and an oxidation process are repeated. to form a concentration of about 1 × ¹⁰ 18 ^{cm -3} of p-type channel stop layer 206, field oxide film 207, the concentration about 1 × ¹⁰ 18 ^{cm -3} of p-type channel stop layer 208. Since the p-type channel stop layer 208 is necessary until its impurity profile reaches the p-type epitaxial layer 203, depending on the film thickness of the epitaxial layer, a corresponding high energy implantation is required for the ion implantation process. In some cases, multiple injections are required with different injection energies. Alternatively, the p-type channel stop layer 208 can be formed by the method described in the second embodiment (FIG. 34).

  Further, in accordance with a normal semiconductor manufacturing process, the gate oxide film 209, the gate electrode 210, the n-type electric field relaxation region 211, the signal charge transfer path 212, the p-type depletion prevention layer 213, the n-type source / drain region 214, the n-type A diffusion floating region 230 is formed. Here, the photodiode is formed by an n-type epitaxial layer 204, a p-type semiconductor layer 203 in contact therewith, a p-type well layer 205, a p-type channel stop layer 208, and a depletion blocking layer 213. The signal charge transfer path 212 is formed so that the signal charge can be completely transferred by providing an n-type concentration profile under the gate electrode by oblique implantation of ion implantation using the gate electrode 210 as a mask (FIG. 35).

  Thereafter, in accordance with a normal semiconductor manufacturing process, the first interlayer insulating film 215, the contact 216, the first metal wiring 217, the second interlayer insulating film 218, and the via that connects the first metal wiring 217 and the second metal wiring 220. 219, the second metal wiring 220, the third interlayer insulating film 221, the via 222 connecting the second metal wiring 220 and the third metal wiring 223, the third metal wiring 223, and the passivation film 224 are sequentially formed (FIG. 36). .

  Next, the surface side (first main surface side) on which the wiring layer of the support substrate 225 and the SOI substrate is formed is bonded using a resin. The material of the support substrate 225 is insulative, and the thermal expansion coefficient up to about 500 ° C. is the same as that of the Si substrate 201. The support substrate 225 can withstand an etchant during subsequent Si substrate etching, and further mounting processes such as dicing later. It is required to have mechanical strength that can withstand. Furthermore, it is more desirable that the imaging apparatus has a light shielding property with respect to a target wavelength. On the other hand, the resin used for bonding is insulative, similar to that required for the support substrate 225, and has a thermal expansion coefficient up to about 500 ° C., which is the same as that of the Si substrate. It is required to have endurance, to have an adhesive strength that can withstand a subsequent mounting process, to have no problem in reliability of the adhesive strength, and more desirably to have a light-shielding property with respect to a target wavelength. In addition, if it has this characteristic, it will not be limited to resin (FIG. 37).

Subsequently, the silicon substrate 250 is selectively removed by etching using the buried oxide film 251 as an etching stopper. As the etchant, an alkaline etchant having a high etch rate selectivity between silicon and a silicon oxide film is suitable. For example, TMAH (tetramethylammonium hydroxide) or a mixed solution of KOH (potassium hydroxide), water and IPA (isopropyl alcohol), or EPW (ethylenediamine / pyrocatechol / water) is an etching selectivity ratio between silicon and a silicon oxide film. (Si / SiO ₂ ) is about 100, and the etching of the silicon substrate 250 can be effectively stopped by the buried oxide film 251. Thereafter, although not shown, a color filter and a microlens can be formed on the surface of the buried oxide film 251 serving as a light receiving surface by using the alignment mark described in FIG. 32 (FIG. 38).

  The feature of this embodiment is that SOI is used for the silicon substrate, the buried oxide film 251 is used as an etching stopper when the silicon substrate 250 is removed by etching, and the buried oxide film 251 is used for the surface protection film on the light receiving surface. Is a point. According to the former, the film thickness of the semiconductor layer 227 which is a light receiving element is not affected by etching, and a very uniform and highly accurate film thickness can be obtained, whereby a high quality image can be obtained. On the other hand, since the buried oxide film 251 can be formed by high-temperature silicon oxidation, the use of a high-quality silicon oxide film as a protective film reduces the generation of dark current generated on the light-receiving surface. Therefore, a high-quality image with low noise can be obtained. Further, the reliability is improved by the excellent durability of the surface protective film.

  Note that by arranging the reading means and the photodiode separately on the first main surface side and the second main surface side of the semiconductor layer 227, the aperture ratio of the photodiode can be increased, and high sensitivity can be obtained. Furthermore, since the pixel pitch can be reduced without reducing the size of the semiconductor element, high resolution can be realized at low cost and high yield. Further, this configuration relaxes the restrictions on the dimensions of the wiring and reduces the probability of occurrence of wiring disconnection or short-circuiting between wirings, which also enables high yield.

  The p-type high-concentration SOI layer 252 provided on the second main surface side functions as a depletion prevention layer of the photodiode, and prevents dark current generated on the semiconductor surface from being mixed into the signal charge. This makes it possible to obtain a low-noise high-quality image. The surface protective film 251 provided on the second main surface side of the semiconductor layer 227 also has an optical function such as antireflection of incident light by adjusting its refractive index and film thickness.

  In the above, the case where electrons are accumulated has been described as an example, but this embodiment can also be applied to the case where holes are accumulated. It is not limited. Furthermore, semiconductor switching elements used for reading means such as stored charge transfer switches are not limited to MOS transistors, and semiconductor switching elements such as bipolar transistors can also be applied.

A fifth embodiment of the present invention will be described with reference to FIGS. A step used as an alignment mark in a later step is formed on a part of the surface of the p-type silicon substrate 201 having a concentration of 1 × 10 ¹⁸ cm ⁻³ or less using a difference in etching and oxidation rate (not shown). ). This alignment mark is used not only for the subsequent semiconductor process, but also as an alignment mark for forming a color filter and a microlens on the light receiving surface. Boron is introduced into the surface of the p-type substrate 201 where the step is formed by ion implantation or boron diffusion from boron-containing glass and heat treatment is performed, and a p-type high concentration having a concentration of about 5 × 10 ¹⁹ cm ⁻³ or more Layer 202 is formed (FIG. 39).

Further, a p-type epitaxial layer 203 of about 2 × 10 ¹⁶ cm ⁻³ and an n-type epitaxial layer 204 of about 1 × 10 ¹⁷ cm ⁻³ are formed. The thicknesses of the p-type high-concentration layer 202 and the p-type epitaxial layer 203 are adjusted to a thickness that allows the light having a wavelength to be detected by the imaging device to be sufficiently transmitted. Further, the thickness of the n-type epitaxial layer 204 is adjusted to a film thickness that sufficiently attenuates light having a wavelength to be detected by the imaging apparatus. When the wavelength to be detected is in the visible light region, a film thickness of about several thousand angstroms to about 15 μm is appropriate (FIG. 40).

  Next, part of the n-type epitaxial layer 204 is removed by dry etching. The etching depth at this time reaches at least the p-type epitaxial layer 203, and preferably reaches the p-type high concentration layer 202. Subsequently, an insulating material 260 is embedded in the etched portion. For example, a chemically stable insulating material such as a silicon oxide film or a silicon nitride film is desirable, and further, it is more desirable to be an insulating material having sufficient light-shielding property or reflectivity with respect to the wavelength of light to be detected. . In this example, a silicon oxide film containing boron was used (FIG. 41).

Further, in accordance with a normal semiconductor manufacturing process, the gate oxide film 209, the gate electrode 210, the n-type electric field relaxation region 211, the signal charge transfer path 212, the p-type depletion prevention layer 213, the n-type source / drain region 214, the n-type A diffusion floating region 230 is formed. Here, the photodiode is formed by an n-type epitaxial layer 204, a p-type semiconductor layer 203 in contact therewith, a p-type well layer 205, a p-type channel stop layer 208, and a depletion blocking layer 213. The signal charge transfer path 212 is formed so that the signal charge can be completely transferred by providing an n-type concentration profile under the gate electrode by oblique implantation of ion implantation using the gate electrode 210 as a mask. Note that in the heat treatment process in the manufacturing process up to here, boron contained in the insulating material 260 is diffused into the n-type epitaxial layer 204 by thermal diffusion, and the p-type diffusion layer 261 is formed. The impurity concentration of the p-type diffusion layer 261 is such that a depletion layer formed between the p-type diffusion layer 261 and the n-type epitaxial layer 204 reaches the insulating material 260 within a voltage range applied during sensor operation. It is adjusted to the concentration necessary to avoid it. For example, 5 × 10 ¹⁷ cm ⁻³ is used here. Although not shown here, the p-type diffusion layer 261 is fixed to an arbitrary potential together with the p-type epitaxial layer 203 and the p-type high concentration layer 202, functions as a path for discharging unnecessary charges, and is p-type. This also functions effectively to stably fix the potential of the well 204 (FIG. 42).

  The subsequent steps are the same as the steps from FIG. 8 to FIG. 11 of the first embodiment (FIGS. 43 to 47).

  FIG. 48 is a plan view of the semiconductor layer 227 on the first main surface side. One pixel includes a signal charge transfer path 212 as a reading means, a gate region 210 of a transfer MOS transistor, a diffusion floating region 230, a reset MOS transistor 120, an amplification MOS transistor 122, and a row selection switch MOS transistor 123. Each of the plurality of pixels is electrically separated by the pixel separation region 260. This plan view is a drawing in which semiconductor elements are connected and wiring for transmitting signals is omitted.

  FIG. 49 is a plan view of the second main surface side, which is the surface on which the semiconductor layer 227 photodiode is formed. This figure shows a plan view of a surface where the n-layer 204 of the photodiode and the pixel isolation region 260 are on the same plane. A photodiode is formed for each pixel, and each pixel is electrically isolated by a pixel isolation region 260.

  A feature of this embodiment is that an insulating material 260 is used in a separation region between adjacent pixels. Thereby, mixing of signal charges between adjacent pixels is completely prevented. Further, when a light-shielding material is used for the insulating material 260, it is possible to prevent light leaking from adjacent pixels due to light obliquely incident on the light receiving portion, and it is possible to prevent smear. Furthermore, as described in this embodiment, when a depletion prevention region is formed at the interface between the insulating material 260 and the semiconductor layer, it becomes possible to prevent the dark current generated at this interface from mixing with the signal charge, Effective for noise suppression.

  Note that the structure described in this embodiment can also be applied to the manufacturing methods in the third and fourth embodiments.

  Thereby, the reading means and the photodiode are separately arranged on the first main surface side and the second main surface side of the semiconductor layer 227, whereby the aperture ratio of the photodiode can be increased and high sensitivity can be obtained. . Furthermore, since the pixel pitch can be reduced without reducing the size of the semiconductor element, high resolution can be realized at low cost and high yield. Further, this configuration relaxes the restrictions on the dimensions of the wiring and reduces the probability of occurrence of wiring disconnection or short-circuiting between wirings, which also enables high yield.

  Furthermore, the pixel separation region 260 disposed between adjacent pixels can prevent the signal charge generated by the photodiode from being mixed between pixels, and the smear is extremely small even when the pixel pitch is narrowed to achieve high resolution. A high-quality image can be obtained.

  In addition, the p-type high concentration layer 202 provided on the second main surface side functions as an etching stop and a photo diode depletion prevention layer during the etching of the silicon substrate, and the former makes the thickness of the semiconductor layer 227 uniform. The latter contributes to the improvement of image quality, and the latter can obtain a low-noise and high-quality image by preventing the dark current generated on the semiconductor surface from being mixed into the signal charge. The surface protective film 226 provided on the second main surface side of the semiconductor layer 227 also has an optical function such as antireflection of incident light by adjusting its refractive index and film thickness.

  In the above, the case where electrons are accumulated has been described as an example, but this embodiment can also be applied to the case where holes are accumulated. It is not limited. Furthermore, semiconductor switching elements used for reading means such as stored charge transfer switches are not limited to MOS transistors, and semiconductor switching elements such as bipolar transistors can also be applied.

  In this example, an imaging device including a pixel having the photodiode and transfer MOS transistor of the first to fifth examples and a readout circuit for reading a signal from the pixel was manufactured. FIG. 50 is a diagram illustrating a configuration of one pixel, and FIG. 51 is a diagram illustrating a configuration of an imaging apparatus that illustrates pixels arranged in 3 rows and 3 columns and a readout circuit.

  In FIG. 50, reference numeral 705 denotes one pixel, PD denotes a photodiode, Q1 denotes a transfer switch Q1 of a transfer MOS transistor for transferring an electric signal from the photodiode PD to a diffusion floating region, and Q2 denotes a reset MOS transistor for resetting the diffusion floating region. The reset switch Q3 has a diffusion floating region connected to the gate and an input MOS transistor of a source follower amplifier circuit composed of a constant current source 812 (shown in FIG. 51) connected as a source side load, and Q4 selects a readout pixel. This is a selection switch.

The basic operation of FIGS. 50 and 51 will be described below.
1) A reset operation for inputting a reset voltage to the input gate of the source follower by the reset switch Q2 and row selection by the selection switch Q4 are performed.
2) The gate of the floating diffusion region of the input node of the source follower is floated, and noise components including fixed pattern noise such as reset noise and variation in threshold voltage of the source follower MOS are read out, and the information is stored in the signal storage unit 805. Hold once.
3) Thereafter, the transfer switch Q1 is opened and closed, the accumulated charge of the photodiode generated by the optical signal is transferred to the input node of the source follower, the sum of the noise component and the optical signal component described above is read, and held in the signal storage unit 805 To do.
4) The common signal lines 809 and 809 ′ are connected to the common signal line 1 (the sum of the noise component and the sum of the noise component and the optical signal component) via the transfer switches 808 and 808 ′ to the common signal line. 808), the transfer switch of the common signal line 2 (808 ′) is turned on, read out, and output as outputs 811 and 811 ′ through the output amplifiers 810, respectively.

  Thereafter, by taking the difference between the output 811 and the output 811 ′, the reset noise and the fixed pattern noise are removed, the optical signal component is extracted, and an image signal having a high S / N can be obtained.

  Reading was performed by the above method, and signal and noise were evaluated. As a result, a high S / N of dynamic range (S / N) = 75 to 85 dB for each bit was obtained.

  The present invention receives light on one surface side (second main surface side) of a semiconductor, and outputs an electric signal photoelectrically converted by a photoelectric conversion means provided on the second surface side to the other surface side (first surface side). The present invention can be applied to a back-illuminated imaging device that is transferred to a reading means provided and read.

1 is a cross-sectional structure diagram that best represents the features of the present invention. 3 is a plan view of a first main surface side of a semiconductor layer 114. FIG. It is a top view of the 2nd main surface side which is a surface by which the semiconductor layer 114 photodiode is formed. It is sectional structure drawing which showed the manufacturing process of 1st Example by this invention. It is sectional structure drawing which showed the manufacturing process of 1st Example by this invention. It is sectional structure drawing which showed the manufacturing process of 1st Example by this invention. It is sectional structure drawing which showed the manufacturing process of 1st Example by this invention. It is sectional structure drawing which showed the manufacturing process of 1st Example by this invention. It is sectional structure drawing which showed the manufacturing process of 1st Example by this invention. It is sectional structure drawing which showed the manufacturing process of 1st Example by this invention. It is sectional structure drawing which showed the manufacturing process of 1st Example by this invention. It is sectional structure drawing which showed the manufacturing process of 2nd Example by this invention. It is sectional structure drawing which showed the manufacturing process of 2nd Example by this invention. It is sectional structure drawing which showed the manufacturing process of 2nd Example by this invention. It is sectional structure drawing which showed the manufacturing process of 2nd Example by this invention. It is sectional structure drawing which showed the manufacturing process of 2nd Example by this invention. It is sectional structure drawing which showed the manufacturing process of 2nd Example by this invention. It is sectional structure drawing which showed the manufacturing process of 2nd Example by this invention. It is sectional structure drawing which showed the manufacturing process of 2nd Example by this invention. It is sectional structure drawing which showed the manufacturing process of 2nd Example by this invention. It is sectional structure drawing which showed the manufacturing process of 2nd Example by this invention. It is sectional structure drawing which showed the manufacturing process of 2nd Example by this invention. It is sectional structure drawing which showed the manufacturing process of the 3rd Example by this invention. It is sectional structure drawing which showed the manufacturing process of the 3rd Example by this invention. It is sectional structure drawing which showed the manufacturing process of the 3rd Example by this invention. It is sectional structure drawing which showed the manufacturing process of the 3rd Example by this invention. It is sectional structure drawing which showed the manufacturing process of the 3rd Example by this invention. It is sectional structure drawing which showed the manufacturing process of the 3rd Example by this invention. It is sectional structure drawing which showed the manufacturing process of the 3rd Example by this invention. It is sectional structure drawing which showed the manufacturing process of the 3rd Example by this invention. It is sectional structure drawing which showed the manufacturing process of the 3rd Example by this invention. It is sectional drawing which showed the manufacturing process of the 4th Example by this invention. It is sectional drawing which showed the manufacturing process of the 4th Example by this invention. It is sectional drawing which showed the manufacturing process of the 4th Example by this invention. It is sectional drawing which showed the manufacturing process of the 4th Example by this invention. It is sectional drawing which showed the manufacturing process of the 4th Example by this invention. It is sectional drawing which showed the manufacturing process of the 4th Example by this invention. It is sectional drawing which showed the manufacturing process of the 4th Example by this invention. It is sectional drawing which showed the manufacturing process of the 5th Example by this invention. It is sectional drawing which showed the manufacturing process of the 5th Example by this invention. It is sectional drawing which showed the manufacturing process of the 5th Example by this invention. It is sectional drawing which showed the manufacturing process of the 5th Example by this invention. It is sectional drawing which showed the manufacturing process of the 5th Example by this invention. It is sectional drawing which showed the manufacturing process of the 5th Example by this invention. It is sectional drawing which showed the manufacturing process of the 5th Example by this invention. It is sectional drawing which showed the manufacturing process of the 5th Example by this invention. It is sectional drawing which showed the manufacturing process of the 5th Example by this invention. 3 is a plan view of a first main surface side of a semiconductor layer 227. FIG. It is a top view of the 2nd main surface side which is a surface by which the semiconductor layer 227 photodiode is formed. It is an equivalent circuit diagram of a pixel using the present invention. It is an equivalent circuit diagram including the readout circuit of the area sensor using the present invention. It is a cross-section figure of the conventional example of a back irradiation type imaging device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 101 Photodiode p layer 102 Photodiode n layer 103 p-type well 104 Element isolation field oxide film 105 High-concentration p layer 106 Photodiode surface protection film 107 Gate region 108 n-type electric field relaxation region 109 Insulating layer 110 n-type Diffusion floating region 111 n-type signal charge transfer path 112 p-type pixel isolation region 113 support substrate 114 semiconductor layer 120 reset MOS transistor 121 reset power source 122 output circuit amplification MOS transistor 123 output circuit row selection switch MOS transistor 124 current source of output circuit 125 output terminal 201 p-type silicon substrate 201
202 p-type high concentration layer 203 p-type epitaxial layer 204 n-type epitaxial layer 205 p-type well layer 206 p-type channel stop layer 207 field oxide film 208 p-type channel stop layer 209 gate oxide film 210 gate electrode 211 n-type Electric field relaxation region 212 signal charge transfer path 213 p-type depletion blocking layer 214 n-type source / drain region 215 first interlayer insulating film 216 contact 217 first metal wiring 218 second interlayer insulating film 219 first metal wiring 220 connecting the second metal wiring to the second metal wiring 222 via connecting the second metal wiring to the third metal wiring 223 third metal wiring 224 passivation film 225 support substrate 226 protective film 227 semiconductor layer 230 n-type diffusion floating Region 240 Porous layer 250 Silicon substrate 25 Embedded oxide film 252 SOI layer 260 Insulating material 261 P-type diffusion layer 701 Power supply 702 Reset switch line 703 Selection switch line 704 Signal output line 705 Photodiode 706 Transfer switch line Q1 Transfer switch Q2 Reset switch Q3 Input MOS transistor Q4 selection switch 801 Power supply 802 Reset switch line 803 Selection switch line 804 Signal output line 805 Signal storage unit 806 Horizontal shift register 808 Transfer switch to common signal line 1 808 ′ Transfer switch to common signal line 2 809 Common signal line 1
809 'common signal line 2
810 Output amplifier 811 Output 811 'Output 812 Constant current source 813 Transfer switch line

Claims (14)

A semiconductor substrate having at least two major surfaces;
Photoelectric conversion means provided on the first main surface of the semiconductor substrate;
A reading means for reading an electrical signal from the photoelectric conversion means provided on the second main surface of the semiconductor substrate;
Wiring means connected to the readout means and provided on the semiconductor substrate,
The photoelectric conversion means includes at least a first-conductivity-type first semiconductor region provided on the first main surface, and a second-conductivity-type first semiconductor region disposed inside the semiconductor substrate with respect to the first semiconductor region. In an imaging device having two semiconductor regions,
The photoelectric conversion means and the reading means are surrounded by a third semiconductor region of the first conductivity type disposed inside the semiconductor substrate from the first main surface side to the second main surface side of the semiconductor substrate. An imaging device characterized by comprising: A semiconductor substrate having at least two major surfaces;
Photoelectric conversion means provided on the first main surface of the semiconductor substrate;
A reading means for reading an electrical signal from the photoelectric conversion means provided on the second main surface of the semiconductor substrate;
Wiring means connected to the readout means and provided on the semiconductor substrate,
The photoelectric conversion means includes at least a first-conductivity-type first semiconductor region provided on the first main surface, and a second-conductivity-type first semiconductor region disposed inside the semiconductor substrate with respect to the first semiconductor region. In an imaging device having two semiconductor regions,
The photoelectric conversion means and the readout means are surrounded by an insulating material region disposed inside the semiconductor substrate from the first main surface side to the second main surface side of the semiconductor substrate. An imaging device. The imaging apparatus according to claim 2, wherein the insulating material region is made of an insulating material containing silicon atoms. A semiconductor region of the first conductivity type is formed at the boundary between the insulating material region and the semiconductor substrate, and the impurity concentration of the semiconductor region is higher than 1 × 10 ¹⁸ cm ⁻³ , The impurity concentration of the first semiconductor region is 9 × 10 ¹⁶ cm ^{−3 to} 9 × 10 ¹⁷ cm ⁻³ , and the impurity concentration of the second semiconductor region is lower than 8 × 10 ¹⁶ cm ^−3. The imaging apparatus according to claim 2 or 3, wherein The imaging apparatus according to claim 1, wherein a chemically stable protective film is formed on the first main surface of the photoelectric conversion unit. The readout means includes an insulated gate transistor for signal transfer,
A fourth semiconductor region of a second conductivity type connected to the second semiconductor region of the photoelectric conversion means and serving as a signal transmission path for transferring a signal from the photoelectric conversion means; a part of the fourth semiconductor region The imaging device according to claim 1, which becomes a main electrode region of the insulated gate transistor. Forming a first conductive type first semiconductor region serving as a photoelectric conversion unit and a second conductive type second semiconductor region in contact with the first semiconductor region on a semiconductor substrate;
A second step of forming a third semiconductor region of a first conductivity type in contact with the second semiconductor region;
A reading means for reading an electrical signal from the photoelectric conversion means is formed in the third semiconductor region, surrounds the periphery of the reading means and the photoelectric conversion means, and extends from the surface of the third semiconductor region to the second semiconductor region. Forming a fourth semiconductor region of the first conductivity type over one semiconductor region, and the first semiconductor region and the second semiconductor region on the semiconductor substrate by the first to third steps. Forming a semiconductor substrate including a third semiconductor region and a fourth semiconductor region;
A fourth step of forming a wiring connected to the reading means on the third semiconductor region;
A fifth step of bonding the semiconductor substrate on which the wiring is formed to a support substrate;
A sixth step of separating or removing the semiconductor substrate;
A method for manufacturing an imaging apparatus, comprising: The method of manufacturing an imaging device according to claim 7, further comprising a step of forming a protective film on a light receiving surface of the photoelectric conversion unit of the semiconductor substrate after the sixth step. The method of manufacturing an imaging device according to claim 7, wherein the fourth semiconductor region is formed by a plurality of ion implantation processes. The fourth semiconductor region is formed by etching away a part of the semiconductor substrate, embedding an insulating material containing an impurity of the first conductivity type in the etching removal portion, and diffusing the impurity. The manufacturing method of the imaging device of Claim 7. Forming a high-concentration impurity layer on the semiconductor substrate, and performing the first to third steps after the step to form the semiconductor substrate on the high-concentration impurity layer; Perform 4 steps and 5th step,
8. The method of manufacturing an imaging device according to claim 7, wherein, in the sixth step, the semiconductor substrate is removed by etching using the high-concentration impurity layer as an etching stopper. Forming a porous layer on the semiconductor substrate, and performing the first to third steps after the step to form the semiconductor substrate on the porous layer; Perform 5 steps,
The method of manufacturing an imaging device according to claim 7, wherein in the sixth step, the porous layer is separated to separate the semiconductor substrate, or the semiconductor substrate is removed up to the porous layer. The method of manufacturing an imaging apparatus according to claim 12, further comprising a step of removing the porous layer remaining on the semiconductor substrate after the sixth step. An SOI (Semiconductor On Insulator) substrate in which a semiconductor layer is formed on a supporting substrate via an insulating layer is used as the semiconductor substrate, and the first to third steps are performed on the thin film semiconductor layer of the SOI substrate. The imaging device according to claim 7, wherein after forming the semiconductor substrate and performing the fourth and fifth steps, the support substrate of the SOI substrate is removed in the sixth step. Production method.

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