JP4270105B2 - Solid-state image sensor - Google Patents

Description

The present invention relates to a solid-state imaging device .

  Typical examples of the solid-state imaging device include a CMOS solid-state imaging device that reads by specifying an XY address, and a CCD solid-state imaging device that is a charge transfer type. Any of these solid-state imaging devices photoelectrically converts light incident on a photodiode that is a two-dimensionally arranged photoelectric conversion device, and one of the charges (for example, electrons) is used as a signal charge.

  A typical CCD solid-state image sensor is an interline transfer type CCD solid-state image sensor having a vertical overflow structure in which charges overflowed in the light receiving section are swept away to the substrate side. This CCD solid-state imaging device has a light receiving portion that becomes a pixel, a vertical transfer register, a horizontal transfer register, and an output portion connected to the horizontal transfer register, and serves as an overflow control gate region in an n-type semiconductor substrate, for example. A p-type semiconductor well region is formed, a photodiode serving as a light receiving portion is formed in the p-type semiconductor well region, and the charge overflowed in the light receiving portion is transferred to the n-type semiconductor substrate through the overflow control gate region formed of the p-type semiconductor well region. It is configured to sweep away (see p36, 103 of Non-Patent Document 1).

The CMOS solid-state imaging device, as shown in FIG. 10 A, B, for example, a p-type semiconductor well region 112 is formed in the n-type semiconductor substrate 111, a p-type semiconductor well of each region partitioned by the pixel isolation region 113 A unit pixel 114 composed of a photodiode PD and a plurality of MOS transistors Tr is formed in the region 112, and a surface irradiation type is formed in which a color filter 116 and an on-chip lens 117 are formed on the substrate surface via a multilayer wiring layer 115. . The photodiode PD is formed to include an n-type semiconductor region 121 and a p + semiconductor region 122 that serves as an accumulation layer on the surface. As the MOS transistor Tr constituting the pixel, for example, when it is constituted by four MOS transistors, it has a read transistor Tr1, a reset transistor Tr2, a vertical selection transistor (not shown), and an amplification transistor (not shown). The read transistor Tr1 is formed by an n-type source / drain region 124 serving as a floating diffusion (FD), a photodiode PD, and a gate electrode 125 formed therebetween via a gate insulating film. The reset transistor Tr2 is formed by a pair of n-type source / drain regions 124 and 126 and a gate electrode 127 formed between them via a gate insulating film. The multilayer wiring layer 115 is formed by the multilayer wiring 129 formed through the interlayer insulating film 128. A color filter 116 and an on-chip lens 117 are formed on the multilayer wiring layer 115 via a passivation film 130 (see FIG. 9 of Patent Document 1). As shown in FIG. 10A, the CMOS solid-state imaging device 110 includes an imaging region in which a plurality of pixels 114 are arranged in a matrix on the surface side of one semiconductor chip 141, that is, a photodiode PD and a sensor circuit using MOS transistors. A so-called photodiode PD / sensor circuit region 142 is formed. The CMOS solid-state imaging device 110 is configured as a surface irradiation type in which light is incident from the substrate surface side.

  On the other hand, as a CMOS solid-state image sensor, a so-called back-illuminated CMOS solid-state image sensor in which light is incident from the back side of the substrate has also been proposed (see Patent Document 1).

JP 2003-31785 A CQ Publishing Co., Ltd. August 10, 2003 "Basics and Applications of CCD / CMOS Image Sensor" by Kazuya Yonemoto

  By the way, the CMOS solid-state imaging device has a focal plane shutter due to its structure, and it has been difficult to realize a complete simultaneous shutter. That is, even if the shutter is released, the shutter is released in the order of reading from the pixels in sequence (see p179 of Non-Patent Document 1). In the case of a CCD solid-state imaging device, the charge (electrons) is swept away and reset on the semiconductor substrate side, and the charge of each light receiving unit is transferred to the vertical transfer register at the same time, and the charge is held through the vertical transfer register. Simultaneous electronic shuttering is possible (see p139, 179 of Non-Patent Document 1). However, in the case of a CMOS solid-state imaging device, the charge of the floating diffusion (FD) is reset by the reset transistor, the charge of the photodiode of the pixel is then read out to the floating diffusion (PD) of the transistor, and this operation is performed for each pixel array. I do it in order. In a CMOS solid-state imaging device, when a video charge is held in a floating diffusion (FD) for 1/30 seconds, for example, much noise (leakage current or the like) is generated compared to a photodiode PD that performs photoelectric conversion. As a result, in a CMOS solid-state imaging device, there is currently no method for realizing a complete simultaneous shutter with fine pixels and high image quality.

  On the other hand, in the CMOS solid-state imaging device, a configuration shown in the comparative example of FIGS. 8 and 9 is conceivable as a method for realizing a complete simultaneous shutter. This CMOS solid-state imaging device 151 is equipped with analog / digital conversion means and memory means corresponding to each fine pixel, and after the photoelectric conversion, all pixels are simultaneously converted to analog / digital, and held in the memory means as data, and thereafter This is a method of sequentially reading out the signals of each pixel from the memory means. That is, as shown in FIG. 8, this type of CMOS solid-state imaging device 151 is a pixel comprising a photodiode PD and a plurality of MOS transistors (sensor transistors) in a part of the surface side of one semiconductor chip 152, that is, in an imaging region. A so-called photodiode PD / sensor circuit region 154 is formed, and an analog / digital conversion means (ADC) and a memory means corresponding to each pixel are formed on the other part of the surface side. 155 is formed.

  FIG. 9 shows a schematic cross-sectional structure of the CMOS solid-state imaging device 151 of the comparative example. In the photodiode PD / sensor circuit region 154, a plurality of front-illuminated pixels 114 similar to those shown in FIG. 10B are arranged, and in the ADC / memory region 155, a pair of n + source / drain regions 131 and gate insulation are provided therebetween. An analog / digital conversion means and a memory means formed by having a MOS transistor Tr11 composed of a gate electrode 132 formed through a film are formed. In the figure, parts corresponding to those in FIG.

  8 and 9, the all-pixel simultaneous shutter can be realized. However, there is a disadvantage that the chip area is increased and the cost is increased.

In view of the above points, by using a back-illuminated solid-state imaging device, while suppressing an increase in chip area, there is provided a solid-state imaging device that enables realization of full simultaneous electronic shutter .

Solid-state imaging device according to the present invention, the semiconductor substrate, a plurality of pixels composed of a photoelectric conversion element which faces the back surface side of the semiconductor substrate and the sensor transistor formed on the surface side of the semiconductor substrate, is connected to each pixel The analog / digital conversion means and the memory means are formed on the surface side of the semiconductor substrate, and a multilayer wiring layer is formed on the surface of the semiconductor substrate with an interlayer insulating film interposed therebetween. These signals are simultaneously subjected to analog / digital conversion by the analog / digital conversion means, and then stored as data in the memory means.

As a preferred form of the solid-state imaging device according to the present invention, a photoelectric conversion element region is formed facing the back side of the semiconductor substrate, a sensor transistor region is formed on the front side of the semiconductor substrate, and analog / digital connected for each pixel. A conversion circuit region and a memory circuit region including a memory element or a capacitor element are formed, and incident light is incident on the photoelectric conversion element from the back surface side of the semiconductor substrate.

As a preferred embodiment of the solid-state imaging device according to the present invention, the photoelectric conversion element region is formed so as to extend below the sensor transistor region.
As a preferred embodiment of the solid-state imaging device according to the present invention, the photoelectric conversion element region is formed to extend to the sensor transistor region, the analog / digital conversion circuit region, and the memory circuit.
Furthermore, the preferable form of the solid-state imaging device according to the present invention is configured such that an electrode pad is formed on the back surface of the semiconductor substrate.

According to the solid-state imaging device according to the present invention, the analog / digital conversion means and the memory means are connected to each pixel, and the analog / digital conversion is performed simultaneously on the signals of all the pixels by the analog / digital conversion means. 6, it is possible to perform complete simultaneous electronic chatter of all pixels. In addition, since a back-illuminated solid-state image sensor is used, a photoelectric conversion element is formed so as to face the back side of the substrate, and a sensor transistor, an analog / digital conversion unit, and a memory unit that read the charge of the photoelectric conversion device on the front side of the substrate Thus, a complete simultaneous electronic shutter can be performed while suppressing an increase in the area of the semiconductor chip. A completely simultaneous electronic shutter can be realized with fine pixels and high image quality. Further, the aperture ratio of the photoelectric conversion element is increased and sensitivity can be improved as compared with the surface irradiation type.

By forming the photoelectric conversion element to extend below the region of the sensor transistor, the aperture ratio of the photoelectric conversion element can be increased and the sensitivity can be improved.
By forming the photoelectric conversion element extending below the sensor transistor area, the analog / digital conversion circuit area, and the memory circuit area, the aperture ratio of the photoelectric conversion element can be further improved, and the hand can be greatly improved. Out.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

1 and 2 show an example of an embodiment of a solid-state imaging device according to the present invention. The solid-state imaging device 1 according to the present embodiment is configured using a back-illuminated CMOS solid-state imaging device. As shown in FIG. 1, a photodiode PD and a plurality of MOS transistors 2 serving as photoelectric conversion devices. Unit pixels 3 composed of [21, 22, 23, 24] are two-dimensionally arranged in a matrix, and an analog / digital conversion means, that is, an analog / digital conversion circuit 5 is connected to the output line 4 of each pixel 3, A memory means 6 is connected to each analog / digital conversion circuit 5 so as to correspond to each pixel.

  The pixel 3 of this example is configured by one photodiode PD, four MOS transistors including a charge readout transistor 21, a reset transistor 22, an amplification transistor 23, and a load transistor. That is, the photodiode PD is connected to the source of the charge readout transistor 21 and the gate thereof is connected to the readout wiring 7 that supplies the readout pulse. The drain of the charge readout transistor is connected to the source of the reset transistor 22, and a so-called floating diffusion (FD) between the drain of the charge readout transistor 21 and the source of the reset transistor 22 is connected to the gate of the amplification transistor 23. The drain of the reset transistor 22 is connected to the power supply wiring 8 to which the power supply voltage Vdd is supplied, and the reset wiring 9 to which the reset pulse φR is supplied is connected to the gate of the reset transistor 22. The drain of the amplification transistor 23 is connected to the power supply wiring 8. A load transistor 24 is connected to the source of the amplification transistor 23. The source of the load transistor 24 is connected to the ground (GND), and its gate is connected to the load wiring 10. The midpoint of connection between the amplification transistor 23 and the load transistor 24 is connected to the output line 4.

  In the above example, the MOS transistor of the pixel is composed of four transistors, that is, a charge readout transistor, a reset transistor, an amplifying transistor, and a load transistor, but may be composed of other plural transistors. The number of MOS transistors constituting the pixel can be appropriately selected according to the purpose.

  The memory means 6 can be constituted by, for example, a digital memory such as a DRAM, SRAM, flash memory, or an analog memory formed by a capacitive element.

  In this back-illuminated type CMOS solid-state imaging device 1, the signal charge photoelectrically converted and accumulated by the photodiode PD of each pixel 3 is read out to the floating diffusion (FD) through the respective charge read-out transistors 21, and the signal charge depends on the signal charge. Each signal output is supplied to the analog / digital conversion circuit 5 corresponding to all the pixels simultaneously through the output line 4, and the analog / digital converted signal is temporarily held as data in the memory means 6. This operation is executed in the same period for all pixels. Thereafter, the image data held from each memory means 6 is sequentially read out.

  In this CMOS solid-state imaging device 1, the light receiving period in which the photodiode PD receives light is the same for all pixels. When the electronic shutter is operated, the photoelectrically converted charges from the start of light reception to the required time are simultaneously swept away from each pixel through the reset transistor 22, and only the signal charges obtained by photoelectric conversion during the remaining light receiving period are read out.

  FIG. 2 shows an example of a schematic cross-sectional structure of the CMOS solid-state imaging device 1 of the present embodiment. This cross-sectional structure is such that a pixel separation region 32 is formed in an imaging region 26 of a thinned semiconductor substrate, for example, an n-type silicon substrate 31, and a p-type semiconductor well region of each pixel region partitioned by the pixel separation region 32. A plurality of the MOS transistors 2 [21 to 24] are formed in 33, which include the n-type source / drain regions 34, the gate insulating film 35, and the gate electrode 36. A so-called sensor transistor including the plurality of MOS transistors 2 [21 to 24] is formed on the substrate surface side. Further, the photodiode PD is formed so as to extend from the back surface side of the substrate to the front surface and to extend under the p-type semiconductor well region 33 in which the sensor transistors 2 [21 to 24] are formed. The photodiode PD is formed by an n + charge storage region 31a and an n semiconductor region 31b, and a p + semiconductor region 38 serving as an accumulation layer for suppressing dark current formed on both the front and back surfaces of the substrate. A color filter 41 is formed on the back side of the substrate through a passivation film 39, and an on-chip lens 42 corresponding to each pixel is formed on the color filter 41. The imaging area 26 is a so-called photodiode PD / sensor circuit area.

  A p-type semiconductor well region 43 is formed on the substrate surface side of a region 27 adjacent to the photodiode PD / sensor circuit region 26 of the n-type semiconductor substrate 31, and analog / corresponding to each pixel is formed in the p-type semiconductor well region 43. A digital conversion circuit 5 and memory means 6 are formed. That is, the analog / digital conversion circuit 5 formed in the p-type semiconductor well region 43 with the n + source / drain region 44, the gate insulating film 45, the MOS transistor 27 including the gate electrode 46, etc., and the digital memory or analog memory And the memory means 6 are formed. This area 27 is a so-called ADC / memory area.

  On the substrate surface side, a multilayer wiring layer 50 in which a multilayer wiring 49 is formed via an interlayer insulating film 48 corresponding to the respective regions 26 and 27 is formed. Further, a reinforcing support substrate 51 such as a silicon substrate is bonded on the multilayer wiring layer 50.

  According to the above-described CMOS solid-state imaging device 1 of the present embodiment, the analog / digital conversion circuit 5 and the memory means 6 are connected to each pixel 3, respectively, and the signals of all the pixels are simultaneously read out and temporarily stored after analog / digital conversion. Since the structure is held in the means 6, complete simultaneous electronic chatter of all pixels becomes possible. Further, since a backside illuminated CMOS solid-state imaging device is used, a photodiode PD is formed so as to face the back side of the substrate, and the sensor transistor 2 [21 to 24] for reading out the charge of the photodiode PD on the front side of the substrate, an analog / Digital conversion circuit 5 and memory means 6 can be formed, and an increase in the area of the semiconductor chip can be suppressed and a complete simultaneous electronic shutter can be performed. A completely simultaneous electronic shutter can be realized with fine pixels and high image quality. Further, the aperture ratio of the photodiode PD is increased and sensitivity can be improved as compared with the surface irradiation type.

3 and 4 each show an example of an embodiment in which the CMOS solid-state imaging device of the present invention is configured on one semiconductor chip. In the embodiment of FIG. 3, a so-called photodiode PD region 62 in which photodiodes of a plurality of pixels are arranged is formed on a part (corresponding to an imaging region) on the back side of the substrate of one semiconductor chip 61. In a region corresponding to the photodiode PD region 62, a so-called sensor circuit region 63 is formed, in which sensor transistors using MOS transistors constituting a plurality of pixels are formed, and a plurality of pixels connected to each pixel are adjacent to the sensor circuit region 63. An ADC / memory area 64 in which the analog / digital conversion circuit 5 and the memory means 6 are arranged is formed .
According to this embodiment, since the backside illumination type and the photodiode PD are formed up to the region corresponding to the sensor transistor, the aperture ratio of the photodiode PD which is a photoelectric conversion element is increased, and the sensitivity can be improved.

In the embodiment of FIG. 4, a sensor circuit region 63 and an ADC / memory region 64 are formed on the substrate surface side of one semiconductor chip 61 as in FIG. 3, and the sensor circuit region 63 and the ADC / memory region are formed on the back surface side of the substrate. The photodiode PD region 62 is formed over the entire region corresponding to 64. In this case, wirings are stretched around the sensor circuit and the ADC / memory circuit on the front surface side to contact the expanded photodiode PD on the back surface side. As shown in FIG. 4, it is preferable that the sensor circuit area 63 is arranged at the center of the chip and the ADC / memory area 64 is arranged at the periphery as shown in FIG. It is also conceivable that the sensor circuit area 63 and the ADC / memory area 64 are arranged so that the chip is divided into upper and lower parts as shown in FIG.
In this embodiment, the back-illuminated photoresist PD region 62 is formed over the sensor circuit region 63 and the region corresponding to the ADC / memory region, so that the aperture ratio of the photodiode PD is further improved and the sensitivity is greatly increased. Can be improved.

Next, an example of a method for manufacturing the CMOS solid-state imaging device 1 shown in FIG. 2 will be described with reference to FIGS.
First, as shown in FIG. 5A, an SOI (Silicon On) in which a thin n-type silicon layer (corresponding to the semiconductor substrate of FIG. 2) 31 is formed on a silicon substrate 66 via a silicon oxide film (SiO2 film) 67. An Insulator board 68 is prepared. An alignment mark 69 is formed at a required position of the silicon layer 31 of the SOI substrate 68.

  Next, as shown in FIG. 5B, the pixel separation region 32 of the imaging region is defined on the photodiode PD / sensor circuit region (corresponding to the imaging region) 26 of the n-type silicon layer 31 from the surface side with the alignment mark 69 as a reference. Form. P-type semiconductor well regions 33 and 43 are formed in the photodiode PD / sensor circuit region 26 and the ADC / memory region 27 of the n-type silicon layer 31. Next, a plurality of MOS transistors 2 [21 to 24] constituting a pixel are formed in the p-type semiconductor well region 33, and an analog / digital conversion circuit including a MOS transistor and the like and memory means are formed in the p-type semiconductor well region 43. To do. Since these MOS transistors 2 [21 to 24] and the MOS transistors constituting the analog / digital conversion circuit are the same as those in FIG. 2, the same reference numerals are given and redundant description is omitted. Further, a multilayer wiring layer 50 in which a multilayer wiring 49 is laminated on the surface of the n-type silicon layer 31 through an interlayer insulating film 48 is formed.

Next, as shown in FIG. 6C, a support substrate 51 such as a silicon substrate is bonded to the multilayer wiring layer 50, for example.
Next, as shown in FIG. 6D, the SOI substrate 68 is inverted, and the silicon substrate 66 is polished and removed by back grinding (mechanical roughing) and wet etching using the silicon oxide film 67 as a stopper film. Further, the silicon oxide film 67 is removed by wet etching.

  Next, as shown in FIG. 7E, for example, a silicon nitride film 71 serving as a passivation film is formed on the back surface of the silicon layer 31, and an electrode is derived from a part of the silicon layer 31, that is, the wiring layer 49a together with the silicon nitride film 71. An opening 72 reaching the wiring layer 49a is formed by selective etching in the portion to be formed. Further, an insulating film 73 such as a silicon oxide film is formed so as to cover the surface of the silicon nitride film 71 from the inner wall of the opening 72. A conductor layer 75 connected to the wiring layer 49a is formed in the opening 72, and an electrode pad 76 connected to the conductor layer 75 and facing the back surface is formed to form a so-called back electrode 77.

  Next, as shown in FIG. 7F, the color filter 41 and the on-chip lens 42 are formed at positions corresponding to the photoresist PD of each pixel on the back surface of the substrate to obtain the target CMOS solid-state imaging device 1.

It is a schematic circuit block diagram of the principal part which shows embodiment of the CMOS solid-state image sensor concerning this invention. It is a schematic sectional drawing of the principal part which shows an example of embodiment of the CMOS solid-state image sensor concerning this invention. It is a top view which shows typically the front and back of the semiconductor chip of one Embodiment of the CMOS solid-state image sensor which concerns on this invention. It is a top view which shows typically the front and back of the semiconductor chip of other embodiment of the CMOS solid-state image sensor concerning this invention. 1A to 1B are manufacturing process diagrams (part 1) showing an embodiment of a method for manufacturing a CMOS solid-state imaging device according to the present invention. C to D are manufacturing process diagrams (part 2) illustrating an embodiment of a method for manufacturing a CMOS solid-state imaging device according to the present invention. FIGS. 3A to 3F are manufacturing process diagrams (part 3) illustrating an embodiment of a method for manufacturing a CMOS solid-state imaging device according to the present invention. FIGS. It is a top view which shows typically the surface of the semiconductor chip of the CMOS solid-state image sensor concerning a comparative example. It is a schematic sectional drawing of the principal part of the CMOS solid-state image sensor concerning a comparative example. A and B are a plan view schematically showing the surface of a semiconductor chip of a conventional CMOS solid-state imaging device and a schematic cross-sectional view of the main part thereof.

Explanation of symbols

1..Back-illuminated CMOS solid-state imaging device, PD..Photodiode, 2 [21, 22, 23, 24] .. MOS transistor, 21..Charge read transistor, 22..Reset transistor, 23..Amplification Transistor, 24 ... Load transistor, 3 ... Unit pixel, 4 ... Output line, 5 ... Analog / digital conversion circuit, 6 ... Memory means, 26 ... Photodiode PD, Sensor area, 27 ... ADC Memory region, 28 ... MOS transistor, 31 ... n-type semiconductor substrate, 32 ... Pixel isolation region, 33, 43 ... p-type semiconductor well region, 34 ... n + source / drain region, 35 ... gate insulation film 36..Gate electrode, 44..n + source / drain region, 45..Gate insulation film, 46..Gate electrode, 48..Interlayer insulation film, 9 .. multilayer wiring, 50 ... wiring layer, 51 ... supporting substrate, 61 ... semiconductor chip, 62 ... photodiode PD region 63 ... sensor circuit area, 64 ... ADC · memory area

Claims (5)

A semiconductor substrate is provided with a plurality of pixels composed of photoelectric conversion elements facing the back side of the semiconductor substrate and sensor transistors formed on the front side of the semiconductor substrate ,
An analog / digital conversion means and a memory means connected to each pixel are formed on the surface side of the semiconductor substrate,
On the surface of the semiconductor substrate is formed a multilayer wiring layer in which a multilayer wiring is formed via an interlayer insulating film,
A solid-state imaging device, wherein signals of photoelectric conversion elements of all the pixels are simultaneously subjected to analog / digital conversion by the analog / digital conversion means and then held as data in the memory means. A photoelectric conversion element region is formed facing the back side of the semiconductor substrate,
A sensor transistor region, an analog / digital conversion circuit region connected to each pixel, and a memory circuit region including a memory element or a capacitor element are formed on the surface side of the semiconductor substrate.
2. The solid-state imaging device according to claim 1, wherein incident light is incident on the photoelectric conversion element from the back side of the semiconductor substrate. The solid-state imaging device according to claim 2, wherein the photoelectric conversion element region is formed to extend below the sensor transistor region. 3. The solid-state imaging device according to claim 2, wherein the photoelectric conversion element region is formed to extend below the sensor transistor region, the analog / digital conversion circuit region, and the memory circuit region. Electrode pads are formed on the back surface of the semiconductor substrate
The solid-state imaging device according to claim 1, 2, 3, or 4.

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