KR100904815B1 - Image Sensor and Method for Manufacturing Thereof - Google Patents

Abstract

An image sensor according to an embodiment includes a semiconductor substrate including a CMOS circuit arranged for each unit pixel; A metal wiring and an interlayer insulating film disposed on the semiconductor substrate; A first conductivity type conductive layer disposed on the interlayer insulating film; An intrinsic layer disposed on the first conductivity type conductive layer and including an ion implantation layer; A second conductivity type conductive layer disposed on the intrinsic layer; An upper electrode disposed on the second conductivity type conductive layer; And a color filter having a gap region on the upper electrode to be spaced apart from each other.

Image Sensor, CMOS Circuit, Photodiode

Description

Image Sensor and Method for Manufacturing Thereof}

In an embodiment, an image sensor and a method of manufacturing the same are disclosed.

The image sensor is a semiconductor device that converts an optical image into an electrical signal, and includes a charge coupled device (CCD) image sensor and a complementary metal oxide silicon (CMOS) image sensor (CIS). do.

The CMOS image sensor implements an image by sequentially detecting an electrical signal of each unit pixel by a switching method by forming a photodiode and a MOS transistor in the unit pixel.

The CMOS image sensor is a structure in which a photo diode area for receiving a light signal and converting it into an electric signal and a transistor for processing the electric signal are horizontally disposed on a semiconductor substrate.

According to the horizontal CMOS image sensor, a photodiode and a transistor are formed adjacent to each other horizontally on a substrate. Accordingly, an additional area for photodiode formation is required.

Embodiments provide an image sensor capable of providing vertical integration of a CMOS circuit and a photodiode and a method of manufacturing the same.

In addition, the embodiment provides an image sensor and a method of manufacturing the same that can be improved together with the resolution (Resolution) and sensor sensitivity (sensitivity).

In addition, the embodiment provides an image sensor and a method of manufacturing the same that can prevent crosstalk and noise phenomenon while employing a vertical photodiode.

An image sensor according to an embodiment includes a semiconductor substrate including a CMOS circuit arranged for each unit pixel; A metal wiring and an interlayer insulating film disposed on the semiconductor substrate; A first conductivity type conductive layer disposed on the interlayer insulating film; An intrinsic layer disposed on the first conductivity type conductive layer and including an ion implantation layer; A second conductivity type conductive layer disposed on the intrinsic layer; An upper electrode disposed on the second conductivity type conductive layer; And a color filter having a gap region on the upper electrode to be spaced apart from each other.

In addition, the manufacturing method of the image sensor according to the embodiment, forming a CMOS circuit for each unit pixel on the semiconductor substrate; Forming an interlayer insulating film including metal wiring on the semiconductor substrate; Forming a first conductivity type conductive layer on the interlayer insulating film; Forming an intrinsic layer including an ion implantation layer on the first conductivity type conductive layer; Forming a second conductivity type conductive layer on the intrinsic layer; Forming an upper electrode on the second conductivity type conductive layer; And forming a color filter having a gap region on the upper electrode so as to be spaced apart from each other.

According to the image sensor and the manufacturing method thereof according to the embodiment, it is possible to provide a vertical integration of the transistor circuit and the photodiode.

In addition, a light absorbing part may be formed between the color filters to block the light incident to the color filter from being incident to areas other than the pixel. Accordingly, since light passing through the color filter is incident on the corresponding photodiode, crosstalk and noise generation of the image sensor can be prevented.

In addition, the fill factor can be approached to 100% by vertical integration of the CMOS circuit and the photodiode.

In addition, the vertical integration can provide higher sensitivity at the same pixel size than the prior art.

In addition, each unit pixel can implement a more complex circuit without reducing the sensitivity.

In addition, in implementing the unit pixel of the photodiode, the light sensing ratio may be improved by increasing the surface area of the photodiode in the unit pixel.

An image sensor and a method of manufacturing the same according to an embodiment will be described in detail with reference to the accompanying drawings.

In the description of the embodiments, where described as being formed "on / over" of each layer, the on / over may be directly or through another layer ( indirectly) includes everything formed.

In the drawings, the thickness or size of each layer is exaggerated, omitted, or schematically illustrated for convenience and clarity of description. In addition, the size of each component does not necessarily reflect the actual size.

5 is a cross-sectional view of an image sensor according to an embodiment.

Referring to FIG. 5, the semiconductor substrate 10 includes a CMOS circuit 15.

The CMOS circuit 15 may be formed of a transfer transistor, a reset transistor, a drive transistor, a select transistor, and the like, arranged for each unit pixel and connected to an upper photodiode 70 to convert an received photocharge.

The interlayer insulating layer 20 including the metal wires 21 is disposed on the semiconductor substrate 10. The interlayer insulating layer 20 may be disposed in a plurality of layers, and the metal wiring 21 may be disposed in a plurality.

The lower electrode 30 is disposed on the metal line 21. For example, the lower electrode 30 may be formed of metal such as Cr, Ti, TiW, and Ta.

The lower electrode 30 is disposed on the metal line 21 and the interlayer insulating layer 20 so that the metal line 21 is not exposed. In addition, the lower electrode 30 is disposed above the metal wiring 21 arranged for each unit pixel and spaced apart for each unit pixel. The lower electrode 30 is spaced apart from a neighboring lower electrode to have a gap region D1.

The photodiode 70 is disposed on the interlayer insulating layer 20 including the lower electrode 30.

The photodiode 70 includes a first conductivity type conductive layer 40, an intrinsic layer 50, and a second conductivity type conductive layer 60. For example, the first conductivity type conductive layer 40 is an n-type amorphous silicon layer, the intrinsic layer 50 is an intrinsic amorphous silicon layer, and the second conductive layer 40 is an intrinsic amorphous silicon layer. The type conductive layer 60 may be a p-type amorphous silicon.

An ion implantation layer 65 is disposed on the intrinsic layer 50. The ion implantation layer 65 may be formed at a position corresponding to the gap region D1 of the lower electrode 30 and may have a width D3 corresponding to the gap region. For example, the ion implantation layer 65 may be formed of p-type impurities.

The intrinsic layer 50 of the photodiode 70 is separated for each unit pixel by the ion implantation layer 65, and light having an inclination angle is transferred to the photodiode 70 of an adjacent pixel through the color filter 90. By preventing the incident, it is possible to prevent crosstalk.

An upper electrode 80 is disposed on the photodiode 70.

The upper electrode 80 may be formed of a transparent electrode having good light transmittance and high conductivity. For example, the upper electrode 80 may be formed of any one of indium tin oxide (ITO), cardium tin oxide (CTO), and ZnO ₂ .

The color filter 90 is disposed for each unit pixel on the upper electrode 80.

The color filter 90 uses dyed photoresist, and one color filter 90 is formed for each unit pixel to separate colors from incident light. Each of the color filters 90 may represent a different color, and may be formed of three colors of red, green, and blue.

A gap region D2 is formed between the color filters 90 to separate the color filters 90 for each pixel. The gap region D2 of the color filter 90 may have a width corresponding to the gap region D1 of the lower electrode 30.

The light absorption filter 100 is disposed in the gap region D2 of the color filter 90. For example, the light absorption filter 100 may be a black filter.

Since the light absorption filter 100 is disposed in the gap region D1 of the color filter 90, the light having the inclination angle with respect to the color filter 90 is absorbed by the light absorption filter 100 and thus the lower photo. It is possible to prevent incident to the diode 70 to prevent the occurrence of crosstalk. In addition, since the ion implantation layer 65 is formed for each unit pixel between the photodiodes 70, light incident on the color filter 90 having an inclination angle does not enter the ion implantation layer 65 and is not electronicized. Can be prevented.

Therefore, light incident at an angle of inclination with respect to the color filter 90 may be prevented by the light absorption filter 100 and the ion implantation layer 65 to prevent the occurrence of crosstalk, thereby improving the reliability of the image sensor. have.

Hereinafter, a method of manufacturing an image sensor according to an embodiment will be described with reference to FIGS. 1 to 6.

Referring to FIG. 1, an interlayer insulating film 20 including a metal wiring 21 is formed on a semiconductor substrate 10 on which a CMOS circuit 15 is formed.

On the semiconductor substrate 10, a CMOS circuit 15 including a transfer transistor, a reset transistor, a drive transistor, a select transistor, and the like, which is connected to a photodiode 70 to be described later and converts received photoelectric charges into an electrical signal, has a unit pixel. Stars may be formed.

An interlayer insulating film 20 and a metal wiring 21 are formed on the semiconductor substrate 10 on which the CMOS circuit 15 is formed to be connected to a power line or a signal line.

The interlayer insulating film 20 may be formed of a plurality of layers. For example, the interlayer insulating film 20 may be formed of a nitride film or an oxide film.

The metal wiring 21 may be formed in plural through the interlayer insulating film 20. For example, the metal wire 21 may be formed of various conductive materials including metal, alloy, or salicide, that is, aluminum, copper, cobalt, or tungsten.

The metal line 21 transfers electrons generated from the photodiode 70 to the CMOS circuit 15 below. Although not shown, the metal wiring 21 may be connected to a region doped with impurities formed under the semiconductor substrate 10.

The lower electrode 30 is formed on the interlayer insulating layer 20 including the metal wiring 21. For example, the lower electrode 30 may be formed of metals such as Cr, Ti, TiW, and Ta.

The lower electrodes 30 are formed on the metal wires 21 arranged for each unit pixel. The lower electrode 30 is patterned for each unit pixel so that a gap region D1 is formed between the lower electrodes. In addition, the lower electrode 30 may be formed to have a wide area so that a large amount of electrons are transferred to the metal wire 21.

The photodiode 70 is formed on the interlayer insulating layer 20 including the lower electrode 30 so as to be connected to the metal wiring 21.

In the embodiment, the photodiode 70 uses a NIP diode. The NIP diode is formed of a structure in which a metal, an n-type amorphous silicon layer, an intrinsic amorphous silicon layer, and a p-type amorphous silicon layer are bonded to each other.

The NIP diode is a photodiode in which an intrinsic amorphous silicon layer, which is a pure semiconductor, is bonded between a p-type silicon layer and a metal, and the intrinsic amorphous silicon layer formed between the p-type metal and the metal becomes a depletion region to generate charge. And storage.

In an embodiment, a NIP diode is used as the photodiode, and the diode may have a structure such as P-I-N, N-I-P, or I-P.

In this embodiment, a photodiode having a NIP structure is used as an example. The n-type amorphous silicon layer is the first conductive conductive layer 40, the intrinsic amorphous silicon layer is the intrinsic layer 50, and the p-type amorphous silicon layer is The second conductive conductive layer 60 will be referred to as.

A method of forming the photodiode will be described below.

The first conductivity type conductive layer 40 is formed on the semiconductor substrate 10. In some cases, the first conductivity type conductive layer 40 may not be formed and subsequent processes may be performed.

The first conductivity type conductive layer 40 may serve as the N layer of the N-I-P diode employed in the embodiment. That is, the first conductivity type conductive layer 40 may be an N type conductivity type conductive layer, but is not limited thereto.

For example, the first conductivity type conductive layer 40 may be formed using N-doped amorphous silicon, but is not limited thereto. For example, the first conductivity type conductive layer 50 may be formed of amorphous silicon by PECVD by mixing a gas such as PH ₃ or P ₂ H ₆ with silane gas (SiH ₄ ).

An intrinsic layer 50 is formed on the first conductivity type conductive layer 40. The intrinsic layer 50 may serve as the I layer of the N-I-P diode employed in the embodiment.

The intrinsic layer 50 may be formed using intrinsic amorphous silicon. For example, the intrinsic layer 50 may be formed of amorphous silicon by PECVD using silane gas (SiH ₄ ).

Here, the intrinsic layer 50 may be formed to a thickness of about 10 to 1,000 times thicker than the thickness of the first conductivity type conductive layer 40. This is because the thicker the intrinsic layer 50 is, the more the depletion region of the pin diode increases, which is advantageous for storing and generating a large amount of photocharges.

The second conductivity type conductive layer 60 is formed on the intrinsic layer 50. The second conductivity type conductive layer 60 may be formed in a continuous process with the formation of the intrinsic layer 50.

The second conductivity type conductive layer 60 may serve as a P layer of the NIP diode employed in the embodiment. That is, the conductive conductive layer () may be a P type conductive conductive layer, but is not limited thereto. For example, the second conductive conductive layer 60 may be formed of amorphous silicon P-doped by PECVD by mixing a gas such as BH ₃ or B ₂ H ₆ with silane gas (SiH ₄ ).

Therefore, the CMOS circuit 15 formed on the semiconductor substrate 10 and the photodiode 70 may be collected in an integrated manner to approach the fill factor of the photodiode 70 to 100%.

Referring to FIG. 2, an upper electrode 80 is formed on the semiconductor substrate 10 on which the photodiode 70 is formed.

The upper electrode 80 may be formed of a transparent electrode having good light transmittance and high conductivity. For example, the upper electrode 80 may be formed of any one of indium tin oxide (ITO), cardium tin oxide (CTO), and ZnO ₂ .

Referring to FIG. 3, a color filter 90 is formed on the upper electrode 80.

The color filter 90 uses dyed photoresist, and one color filter 90 is formed for each unit pixel to separate colors from incident light. Each of the color filters 90 may represent a different color, and may be formed of three colors of red, green, and blue.

The color filter 90 may be formed to be spaced apart from the neighboring color filter 90. That is, the blue color filter 90 may be separated from the neighboring red color filter 90 and the green color filter 90 to have a gap region D2. The gap region D2 of the color filter 90 may have a width corresponding to the gap region D1 of the lower electrode 30.

Referring to FIG. 4, an ion implantation layer 65 is formed in the intrinsic layer 50 of the photodiode 70.

The ion implantation layer 65 may be formed by injecting impurities into a region of the lower photodiode 70 using the color filter 90 as a mask. For example, the ion implantation layer 65 may be formed by ion implantation of p-type impurities.

The ion implantation layer 65 is ion implanted using the color filter 90 as a mask and has a width corresponding to the gap region D2 of the color filter 90. In addition, the ion implantation layer 65 has a width corresponding to the gap region D1 of the lower electrode 30.

Therefore, when external light is incident to the lower photodiode 70 region through the color filter 90, the color filter 90 is separated by the gap region D2, thereby preventing cross talk of incident light. have.

In addition, incident light having an inclination angle with respect to the blue color filter 90 passes through the blue color filter 90 and is adjacent to the neighboring red color filter 90 or green color filter. Incident on the photodiode 17 corresponding to 90, crosstalk may be generated. However, in the embodiment, since the ion implantation layer 65 is formed in the intrinsic layer 50 of the photodiode 70, light having an inclination angle is transmitted through the blue color filter 90. 65) is incident on the area. Since the light incident on the ion implantation layer 65 is not electronicized, the incident light may be prevented from entering the photodiode 70 of the adjacent pixel, thereby preventing crosstalk and noise.

5, the light absorption filter 100 is formed in the gap region D2 of the color filter 90.

The light absorption filter 100 may be formed by gap filling a light absorption material in the gap region D2 of the color filter 90. For example, the light absorption filter 100 may be formed as a black filter.

Referring to FIG. 6, since the light absorption filter 100 is formed between the color filters 90, crosstalk between pixels may be blocked to improve the reliability of the image sensor.

Therefore, after the light passing through the color filter 90 is incident on the photodiode 70 to generate electrons, the electrons are collected by the lower electrode 30, and the lower CMOS circuit is formed by the metal wiring 21. May be passed to (15).

For example, light incident vertically with respect to the blue color filter 90 is incident to the corresponding photodiode 70 region below, and the CMOS is provided through the lower electrode 30 and the metal wiring 21. May be delivered to circuit 15.

In this case, the light incident with the inclination with respect to the blue color filter 90 may be a photodiode corresponding to an adjacent photodiode 70 region, that is, a red or green color filter 90. 70 may be incident to crosstalk. However, in the exemplary embodiment, the light absorption filter 100 is formed between the color filters 90 so that the light absorption filter 100 absorbs the light incident on the color filter 90 having an inclination angle, thereby adjoining the photodiode 70. ) Can be prevented from entering and preventing cross talk. In addition, the ion implantation layer 65 is formed between the photodiodes 70, and the light incident through the color filter 90 having the inclination angle and entering the photodiode 70 of the adjacent pixel is incident on the ion implantation layer 65. Since the incident light does not become electronized, crosstalk can be prevented.

The above-described embodiments are not limited to the above-described embodiments and drawings, and it is common in the technical field to which the present embodiments belong that various changes, modifications, and changes can be made without departing from the technical spirit of the present embodiments. It will be apparent to those who have

1 to 5 are cross-sectional views illustrating a manufacturing process of an image sensor according to an embodiment.

6 is a plan view of an image sensor according to an embodiment.

Claims (9)

A semiconductor substrate including a CMOS circuit arranged for each unit pixel; A metal wiring and an interlayer insulating layer disposed on the semiconductor substrate so as to be connected to the CMOS circuit; A lower electrode formed on the interlayer insulating film so as to be connected to the metal wiring and having a first gap region spaced apart from each other; A first conductivity type conductive layer disposed on the interlayer insulating layer including the lower electrode; An intrinsic layer disposed on the first conductivity type conductive layer; An ion implantation layer formed inside the intrinsic layer so as to correspond to the first gap region, and separating the intrinsic layer by unit pixel; A second conductivity type conductive layer disposed on the intrinsic layer and the ion implantation layer; An upper electrode disposed on the second conductivity type conductive layer; A color filter having a second gap region spaced apart from each other on the upper electrode; And And an optical absorption filter formed in the second gap region. The method of claim 1, The ion implantation layer and the second conductivity type conductive layer is formed of p-type impurities. The method of claim 1, And the first gap region, the ion implantation layer, and the second gap region are formed at positions corresponding to each other and have the same width. The method of claim 1, And the light absorption filter is a black filter. Forming a CMOS circuit for each unit pixel on the semiconductor substrate; Forming an interlayer insulating film on the semiconductor substrate to be connected to the CMOS circuit; Forming a lower electrode formed on the interlayer insulating layer so as to be connected to the metal wiring and having a first gap region therebetween; Forming a first conductivity type conductive layer on the interlayer insulating layer including the lower electrode; Forming an intrinsic layer on the first conductivity type conductive layer; Forming a second conductivity type conductive layer on the intrinsic layer; Forming an upper electrode on the second conductive conductive layer; Forming a color filter having a second gap region spaced apart from each other on the upper electrode; Performing an ion implantation process using the color filter as an ion implantation mask to form an ion implantation layer on the intrinsic layer; And And forming a light absorption filter in the second gap region. The method of claim 5, The first gap region, the ion implantation layer and the second gap region are formed at positions corresponding to each other, the manufacturing method of the image sensor, characterized in that formed in the same width. The method of claim 5, The ion implantation layer and the second conductive type conductive layer is a manufacturing method of an image sensor formed of p-type impurities. delete The method of claim 5, The light absorption filter is a manufacturing method of an image sensor comprising a black filter.

Images