KR100924412B1 - Image Sensor and Method for Manufacturing Thereof - Google Patents

Abstract

An image sensor according to an embodiment includes an interlayer insulating film including a metal wiring disposed on a semiconductor substrate; A lower electrode disposed on the interlayer insulating layer so as to be connected to the metal wiring; A photodiode disposed on the interlayer insulating layer including the lower electrode; An upper electrode disposed on the photodiode; Spacers disposed on sidewalls of the photodiode and the upper electrode; And a passivation layer disposed on the interlayer insulating layer including the photodiode, the upper electrode, and the spacer.

Image Sensors, Photodiodes and Passivation Layers

Description

Image Sensor and Method for Manufacturing Thereof}

In an embodiment, an image sensor and a method of manufacturing the same are disclosed.

The image sensor is a semiconductor device that converts an optical image into an electrical signal, and includes a charge coupled device (CCD) image sensor and a complementary metal oxide silicon (CMOS) image sensor (CIS). do.

The CMOS image sensor implements an image by sequentially detecting an electrical signal of each unit pixel by a switching method by forming a photodiode and a MOS transistor in the unit pixel.

The CMOS image sensor is a structure in which a photo diode area for receiving a light signal and converting it into an electric signal and a transistor for processing the electric signal are horizontally disposed on a semiconductor substrate.

According to the horizontal CMOS image sensor, a photodiode and a transistor are formed adjacent to each other horizontally on a substrate. Accordingly, an additional area for photodiode formation is required.

The embodiment provides an image sensor and a method of manufacturing the same that can provide vertical integration of a transistor circuit and a photodiode.

In addition, the embodiment provides an image sensor and a method of manufacturing the same that can be improved together with the resolution (Resolution) and sensor sensitivity (sensitivity).

An image sensor according to an embodiment includes an interlayer insulating film including a metal wiring disposed on a semiconductor substrate; A lower electrode disposed on the interlayer insulating layer so as to be connected to the metal wiring; A photodiode disposed on the interlayer insulating layer including the lower electrode; An upper electrode disposed on the photodiode; Spacers disposed on sidewalls of the photodiode and the upper electrode; And a passivation layer disposed on the interlayer insulating layer including the photodiode, the upper electrode, and the spacer.

In accordance with another aspect of the present invention, a method of manufacturing an image sensor includes: forming an interlayer insulating layer including metal wiring on a semiconductor substrate; Forming a lower electrode on the interlayer insulating layer so as to be connected to the metal wiring; Forming a photodiode on the interlayer insulating film including the lower electrode; Forming an upper electrode on the photodiode; Forming a spacer on sidewalls of the photodiode and the upper electrode; And forming a passivation layer on the interlayer insulating layer including the photodiode, the upper electrode, and the spacer.

According to the image sensor and the manufacturing method thereof according to the embodiment, it is possible to provide a vertical integration of the transistor circuit and the photodiode.

In addition, the fill factor can be approached to 100% by vertical integration of the transistor and the photodiode.

In addition, the vertical integration can provide higher sensitivity at the same pixel size than the prior art.

In addition, each unit pixel can implement a more complex circuit without reducing the sensitivity.

In addition, in implementing the unit pixel of the photodiode, the light sensing ratio may be improved by increasing the surface area of the photodiode in the unit pixel.

The embodiment also provides an image sensor and its manufacturing method which can improve subsequent processing steps while employing a vertical photodiode.

An image sensor and a method of manufacturing the same according to an embodiment will be described in detail with reference to the accompanying drawings.

In the description of the embodiments, where described as being formed "on / over" of each layer, the on / over may be directly or through another layer ( indirectly) includes everything formed.

In the drawings, the thickness or size of each layer is exaggerated, omitted, or schematically illustrated for convenience and clarity of description. In addition, the size of each component does not necessarily reflect the actual size.

5 is a cross-sectional view illustrating an image sensor according to an embodiment.

Referring to FIG. 5, the semiconductor substrate 100 includes a pixel area A and a peripheral circuit area B. FIG. In the pixel region A, a transistor circuit for processing the photocharge of the photodiode 140 is formed. In the peripheral circuit region B, a signal processing circuit (not shown) of the peripheral region may be formed.

An interlayer insulating layer 110 including a metal wiring 120 is disposed on the semiconductor substrate 100. The metal line 120 is formed for each unit pixel so as to be connected to the transistor circuit of the pixel area A. In addition, the metal line 120 may be connected to the signal processing circuit of the peripheral circuit region B.

The lower electrode 130 is disposed on the interlayer insulating layer 110 to be connected to the metal wiring 120. The lower electrode 130 may be electrically connected to the metal wiring 120 to transfer photoelectrons generated by the photodiode 140 to the metal wiring.

The photodiode 140 and the upper electrode 150 are disposed on the interlayer insulating layer 110 of the pixel region A including the lower electrode 130. The photodiode 140 includes a first conductivity type conductive layer, an intrinsic layer, and a second conductivity type conductive layer. For example, the first conductivity type conductive layer may be n-type amorphous silicon, the intrinsic layer may be intrinsic silicon, and the second conductivity type conductive layer may be formed of p-type amorphous silicon. In addition, the upper electrode 150 may be a transparent electrode. The upper electrode 150 may be formed only on the upper surface of the photodiode 140.

Therefore, the photodiode 140 and the upper electrode 150 may be formed at a height higher than the surface of the interlayer insulating layer 110 in the peripheral circuit region B. For example, the heights of the sidewalls of the photodiode 140 and the upper electrode 150 with respect to the interlayer insulating layer 110 may have a step of 3000 to 10000 Å. In addition, sidewalls of the photodiode 140 and the upper electrode 150 may be perpendicular to the surface of the interlayer insulating layer 110 of the peripheral circuit region B.

Spacers 165 are disposed on sidewalls of the photodiode 140 and the upper electrode 150. For example, the spacer 165 may be formed of a nitride film. The spacer 165 may be formed to be inclined on sidewalls of the photodiode 140 and the upper electrode 150. The spacer 165 is formed of a nitride film having excellent adhesive properties. Therefore, the sidewalls of the photodiode 140 and the upper electrode 150 and the spacer 165 may be formed to be in close contact with each other without voids.

The passivation layer 170 is formed on the semiconductor substrate 100 including the upper electrode 150, the photodiode 140, the spacer 165, and the interlayer insulating layer 110. For example, the passivation layer 170 may be formed of a low temperature oxide film. The passivation layer 170 is formed to cover all of the upper electrode 150, the photodiode 140, the spacer 165, and the interlayer insulating layer 110. In particular, a spacer 165 formed of a nitride film and inclined is formed on sidewalls of the photodiode 140 and the upper electrode 150. Therefore, the passivation layer 170 may be disposed to be in close contact with the surface of the spacer 165 without voids.

A manufacturing method of an image sensor according to an embodiment will be described with reference to FIGS. 1 to 6.

1 and 2, an interlayer insulating layer 110 including a metal wiring 120 is formed on a semiconductor substrate 100.

The semiconductor substrate 100 includes a pixel area A and a peripheral circuit area B. FIG. In the pixel region A, a transistor circuit may be formed for each unit pixel in order to convert an electric signal of photoelectric charges received by being connected to a photodiode described below. For example, the transistor circuit may be any one of 3Tr, 4Tr, and 5Tr. In the peripheral circuit region B, a transistor circuit (not shown) may be formed to sequentially detect an electrical signal of each unit pixel of the pixel region A to implement an image.

An interlayer insulating layer 110 and a metal wiring 120 are formed on the semiconductor substrate 100 to be connected to a power line or a signal line. The interlayer insulating layer 110 may be formed of a plurality of layers. The metal wire 120 may be formed in plural through the interlayer insulating layer 110. The metal wires 120 are disposed for each unit pixel and are formed to connect the transistor circuit and the photodiode. For example, the interlayer insulating layer 110 may be formed of an oxide film or a nitride film. In addition, the metal wire 120 may be formed of various conductive materials including metal, alloy, or silicide, that is, aluminum, copper, cobalt, or tungsten.

The lower electrode 130 is formed on the metal wire 120. For example, the lower electrode 130 may be formed of metal such as Cr, Ti, TiW, and Ta. Therefore, the lower electrode 130 may be electrically connected to the metal wiring 120 formed for each unit pixel. The lower electrode 130 may also be formed on the metal wiring 120 of the peripheral circuit region B. Of course, the lower electrode 130 may not be formed.

The photodiode 140 is formed on the interlayer insulating layer 110 including the lower electrode 130. The photodiode 140 is formed on the interlayer insulating layer 110 in the pixel region A. In an embodiment, the photodiode 140 uses a NIP diode. The NIP diode is formed of a structure in which a metal, an n-type amorphous silicon layer, an intrinsic amorphous silicon layer, and a p-type amorphous silicon layer are bonded to each other.

The NIP diode is a photodiode in which an intrinsic amorphous silicon layer, which is a pure semiconductor, is bonded between a p-type silicon layer and a metal, and the intrinsic amorphous silicon layer formed between the p-type metal and the metal becomes a depletion region to generate charge. And storage. The photodiode may have a structure such as P-I-N or N-I-P or I-P.

In an embodiment, the photodiode 140 may have an N-I-P structure. The n-type amorphous silicon layer of the photodiode 140 is referred to as a first conductive type conductive layer, an intrinsic amorphous silicon layer is an intrinsic layer, and the p-type amorphous silicon layer is referred to as a second conductive type conductive layer.

A method of forming the photodiode 140 will be described below.

The first conductivity type conductive layer is formed on the interlayer insulating layer 110 including the lower electrode 130. In some cases, the first conductivity type conductive layer may not be formed and subsequent processes may be performed. The first conductivity type conductive layer may serve as the N layer of the N-I-P diode employed in the embodiment. That is, the first conductivity type conductive layer may be an N type conductivity type conductive layer, but is not limited thereto. For example, the first conductivity type conductive layer may be formed using N-doped amorphous silicon, but is not limited thereto.

An intrinsic layer is formed on the first conductivity type conductive layer. The intrinsic layer may serve as the I layer of the N-I-P diode employed in the embodiment. The intrinsic layer may be formed using intrinsic amorphous silicon. The intrinsic layer may be formed to a thickness of about 10 to 1,000 times the thickness of the first conductive type conductive layer. This is because the thicker the thickness of the intrinsic layer is, the more the depletion region of the pin diode increases, which is advantageous for storing and generating a large amount of photocharges.

A second conductive conductive layer is formed on the intrinsic layer. The second conductivity type conductive layer may be formed by a continuous process of forming the intrinsic layer. The second conductivity type conductive layer may serve as a P layer of the N-I-P diode employed in the embodiment. That is, the second conductivity type conductive layer may be a P type conductivity type conductive layer, but is not limited thereto.

Therefore, the transistor circuit formed on the semiconductor substrate 100 and the photodiode 140 may be collected in an integrated manner to approach the fill factor of the photodiode 140 to 100%.

An upper electrode 150 is formed on the photodiode 140. The upper electrode 150 may be formed of a transparent electrode having good light transmittance and high conductivity. For example, the upper electrode 150 may be formed of any one of indium tin oxide (ITO), cardium tin oxide (CTO), and ZnO ₂ .

As described above, the photodiode 140 and the upper electrode 150 are formed on the semiconductor substrate 100 of the pixel region A so that the interlayer insulating layer 110 of the peripheral circuit region B is exposed. For example, the photodiode 140 and the upper electrode 150 may be formed only on the pixel region A by a photo process and an etching process after being formed on the interlayer insulating layer 110.

Therefore, the surface of the photodiode 140, the upper electrode 150, and the interlayer insulating layer 110 of the peripheral circuit region B has a step. For example, a step between the surface of the upper electrode 150 including the photodiode 140 and the surface of the interlayer insulating layer 110 may be 3000 to 10,000 Å. In particular, sidewalls of the photodiode 140 and the upper electrode 150 may be perpendicular to the surface of the interlayer insulating layer 110.

When a vertical step occurs between the sidewalls of the photodiode 140 and the upper electrode 150 and the interlayer insulating layer 110, it may be difficult to form the passivation layer 170 formed in a subsequent process. That is, when the passivation layer 170 is formed on the sidewalls of the photodiode 140 and the upper electrode 150, voids may occur between the photodiodes 140 and the upper electrode 150 to cause defects. Therefore, in the embodiment, as shown in FIG. 4, spacers 165 are formed on sidewalls of the photodiode 140 and the upper electrode 150.

Referring to FIG. 2, a sacrificial insulating layer 160 is formed on the interlayer insulating layer 110 including the photodiode 140 and the upper electrode 150. For example, the sacrificial insulating layer 160 may be a nitride film. The sacrificial insulating layer 160 may be formed of a nitride film at a temperature of 100 ~ 300Å by using a CVD or PECVD process. In this case, the nitride film used as the sacrificial insulating layer 160 has excellent adhesive properties, so that the surface of the upper electrode 150, the sidewalls of the upper electrode 150 and the photodiode 140, and the interlayer insulating layer 110 are separated from each other. It can be formed uniformly on the surface. In particular, since the nitride film used as the sacrificial insulating layer 160 has excellent adhesive properties, it may be formed without voids on the sidewalls of the upper electrode 150 and the photodiode 140 even when deposited at a low temperature.

Referring to FIG. 3, an etching process of the sacrificial insulating layer 160 is performed. The etching process may be formed using a blanket etch. When the blanket etch process is performed, the sacrificial insulating layer 160 on the upper surface of the upper electrode 150 and the upper surface of the interlayer insulating layer 110 may be removed. In addition, the sacrificial insulating layer 160 formed on sidewalls of the photodiode 140 and the upper electrode 150 may be removed to have an inclination.

Referring to FIG. 4, spacers 165 are formed on sidewalls of the photodiode 140 and the upper electrode 150. The spacer 165 may be formed to be inclined by a blanket etch process for the sacrificial insulating layer 160 described with reference to FIG. 3. Since the spacer 165 is formed of a nitride film, the spacer 165 may be formed on the sidewalls of the photodiode 140 and the upper electrode 150 without gaps. Since the spacer 165 is selectively formed only on sidewalls of the photodiode 140 and the upper electrode 150, the insulating interlayer corresponding to the surface of the upper electrode 150 and the peripheral circuit region B. 110 is exposed.

Referring to FIG. 5, a passivation layer 170 is formed on the interlayer insulating layer 110 including the upper electrode 150 and the spacer 165. The passivation layer 170 may be formed of a low temperature oxide film. Specifically, the passivation layer 170 may be formed at a temperature of 100 ~ 250 ℃ through CVD or PECVD process.

The passivation layer 170 may be uniformly formed on the interlayer insulating layer 110 including the upper electrode 150 and the photodiode 140. In particular, since the spacer 165 formed of a nitride film is formed on the sidewalls of the upper electrode 150 and the photodiode 140, the passivation layer 170 may be closely adhered along the sidewall of the spacer 165. . This is because the spacer 165 is formed to be inclined with respect to the surface of the interlayer insulating layer 110 and is formed of an insulating material. Accordingly, the passivation layer 170 may be continuously formed on the upper electrode 150, the photodiode 140, the spacer 165, and the interlayer insulating layer 110 without being voided.

Although not shown, a color filter and a micro lens may be formed on the passivation layer 170 corresponding to the pixel area A after the passivation layer 170 is formed.

In embodiments, the photodiode may be formed on a semiconductor substrate to provide vertical integration of the transistor circuit and the photodiode, thereby bringing the fill factor close to 100%.

In addition, a passivation layer formed of a low temperature oxide film may be formed on the photodiode to protect the surface of the photodiode.

In addition, by the spacers formed on the sidewalls of the photodiode and the upper electrode, it is possible to prevent voids or breakage during subsequent passivation layer formation, thereby improving reliability of the device.

The embodiments described above are not limited to the above-described embodiments and drawings, and it is to be understood that various changes, modifications, and changes can be made without departing from the technical spirit of the present embodiments. It will be obvious to those who have it.

1 to 5 are cross-sectional views illustrating a manufacturing process of an image sensor according to an embodiment.

Claims (8)

A semiconductor substrate including a pixel region in which a transistor circuit is formed and a peripheral circuit region; An interlayer insulating film including metal wires disposed on the semiconductor substrate; A lower electrode disposed on the interlayer insulating layer so as to be connected to the metal wiring; A photodiode disposed on the interlayer insulating layer including the lower electrode to correspond to the pixel region; An upper electrode disposed on the photodiode; Spacers disposed on sidewalls of the photodiode and the upper electrode; And And a passivation layer disposed on the interlayer insulating layer including the photodiode, the upper electrode, and the spacer. The method of claim 1, The spacer is an image sensor formed of a nitride film. The method of claim 1, The passivation layer is formed of a low temperature oxide film. Forming a semiconductor substrate including a pixel region including a transistor circuit and a peripheral circuit region; Forming an interlayer insulating film including metal wiring on the semiconductor substrate; Forming a lower electrode on the interlayer insulating layer so as to be connected to the metal wiring; Forming a photodiode on the interlayer insulating layer including the lower electrode to correspond to the pixel region; Forming an upper electrode on the photodiode; Forming a spacer on sidewalls of the photodiode and the upper electrode; And And forming a passivation layer on the interlayer insulating layer including the photodiode, the upper electrode, and the spacer. The method of claim 4, wherein Forming the spacers, Forming a sacrificial insulating layer on the interlayer insulating film including the photodiode; And performing a blanket etch on the sacrificial insulating layer. The method of claim 5, And the sacrificial insulating layer is formed of a nitride film. The method of claim 4, wherein The spacer is a manufacturing method of the image sensor is formed at a temperature of 100 ~ 250 ℃. The method of claim 4, wherein The passivation layer is a low temperature oxide film manufacturing method of the image sensor.

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