CN1604340A - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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Publication number
CN1604340A
CN1604340A CN200410079728.4A CN200410079728A CN1604340A CN 1604340 A CN1604340 A CN 1604340A CN 200410079728 A CN200410079728 A CN 200410079728A CN 1604340 A CN1604340 A CN 1604340A
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CN
China
Prior art keywords
mentioned
gate electrode
layer
diffusion layer
concentration diffusion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN200410079728.4A
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English (en)
Chinese (zh)
Inventor
杉原茂行
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Publication of CN1604340A publication Critical patent/CN1604340A/zh
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/62—Capacitors having potential barriers
    • H10D1/66—Conductor-insulator-semiconductor capacitors, e.g. MOS capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0212—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/021—Manufacture or treatment using multiple gate spacer layers, e.g. bilayered sidewall spacers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0144—Manufacturing their gate insulating layers
    • H10P14/40—
    • H10P14/412—
    • H10P14/6928—
    • H10P72/0431—

Landscapes

  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
CN200410079728.4A 2003-10-02 2004-09-17 半导体装置及其制造方法 Pending CN1604340A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2003344170A JP2005109389A (ja) 2003-10-02 2003-10-02 半導体装置及びその製造方法
JP2003344170 2003-10-02

Publications (1)

Publication Number Publication Date
CN1604340A true CN1604340A (zh) 2005-04-06

Family

ID=34537894

Family Applications (1)

Application Number Title Priority Date Filing Date
CN200410079728.4A Pending CN1604340A (zh) 2003-10-02 2004-09-17 半导体装置及其制造方法

Country Status (5)

Country Link
US (1) US7468303B2 (enExample)
JP (1) JP2005109389A (enExample)
KR (1) KR100659619B1 (enExample)
CN (1) CN1604340A (enExample)
TW (1) TWI260783B (enExample)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7696050B2 (en) 2005-10-04 2010-04-13 Renesas Technology Corp. Method of manufacturing semiconductor device carrying out ion implantation before silicide process
CN101814433B (zh) * 2009-02-20 2013-02-27 联发科技股份有限公司 横向双极结型晶体管及其制造方法
US8674454B2 (en) 2009-02-20 2014-03-18 Mediatek Inc. Lateral bipolar junction transistor
CN103840001A (zh) * 2012-11-27 2014-06-04 台湾积体电路制造股份有限公司 具有额外漏极od增加的高压漏极延伸mosfet
CN112151610A (zh) * 2019-06-27 2020-12-29 南亚科技股份有限公司 半导体元件及其制备方法

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7615426B2 (en) * 2005-02-22 2009-11-10 Taiwan Semiconductor Manufacturing Company, Ltd. PMOS transistor with discontinuous CESL and method of fabrication
KR100928504B1 (ko) * 2007-10-19 2009-11-26 주식회사 동부하이텍 반도체 소자 및 반도체 소자의 제조방법
KR100976793B1 (ko) * 2007-12-31 2010-08-20 주식회사 동부하이텍 모스 트랜지스터의 제조 방법
US20110065245A1 (en) * 2009-09-13 2011-03-17 Jei-Ming Chen Method for fabricating mos transistor
JP2011222955A (ja) * 2010-03-26 2011-11-04 Renesas Electronics Corp 半導体装置及びその製造方法
CN102456556A (zh) * 2010-10-18 2012-05-16 中芯国际集成电路制造(上海)有限公司 金属硅化物的形成方法
US8569171B2 (en) * 2011-07-01 2013-10-29 Globalfoundries Inc. Mask-based silicidation for FEOL defectivity reduction and yield boost
JP5927017B2 (ja) * 2012-04-20 2016-05-25 ルネサスエレクトロニクス株式会社 半導体装置及び半導体装置の製造方法
KR102288643B1 (ko) * 2019-03-29 2021-08-10 매그나칩 반도체 유한회사 마스크 레이아웃 및 그 마스크 레이아웃을 이용한 반도체 소자 및 그 반도체 소자 제조방법

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5208472A (en) * 1988-05-13 1993-05-04 Industrial Technology Research Institute Double spacer salicide MOS device and method
US4949136A (en) * 1988-06-09 1990-08-14 University Of Connecticut Submicron lightly doped field effect transistors
JP2551127B2 (ja) * 1989-01-07 1996-11-06 三菱電機株式会社 Ｍｉｓ型半導体装置およびその製造方法
JPH09507723A (ja) * 1994-01-12 1997-08-05 アトメル・コーポレイション 最適化したｅｓｄ保護を備える入力／出力トランジスタ
US6100125A (en) * 1998-09-25 2000-08-08 Fairchild Semiconductor Corp. LDD structure for ESD protection and method of fabrication
JP3594550B2 (ja) 2000-11-27 2004-12-02 シャープ株式会社 半導体装置の製造方法
JP2002353330A (ja) 2001-05-25 2002-12-06 Denso Corp 半導体装置及びその製造方法
JP2003151991A (ja) 2001-08-23 2003-05-23 Matsushita Electric Ind Co Ltd 半導体装置及びその製造方法
KR20030058437A (ko) 2001-12-31 2003-07-07 동부전자 주식회사 홈을 이용한 반도체 소자의 제조 방법

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7696050B2 (en) 2005-10-04 2010-04-13 Renesas Technology Corp. Method of manufacturing semiconductor device carrying out ion implantation before silicide process
CN1976007B (zh) * 2005-10-04 2010-06-16 株式会社瑞萨科技 半导体器件及其制造方法
US7872314B2 (en) 2005-10-04 2011-01-18 Renesas Electronics Corporation Method of manufacturing semiconductor device carrying out ion implantation before silicide process
CN101814433B (zh) * 2009-02-20 2013-02-27 联发科技股份有限公司 横向双极结型晶体管及其制造方法
US8674454B2 (en) 2009-02-20 2014-03-18 Mediatek Inc. Lateral bipolar junction transistor
US8836043B2 (en) 2009-02-20 2014-09-16 Mediatek Inc. Lateral bipolar junction transistor
US9324705B2 (en) 2009-02-20 2016-04-26 Mediatek Inc. Lateral bipolar junction transistor
CN103840001A (zh) * 2012-11-27 2014-06-04 台湾积体电路制造股份有限公司 具有额外漏极od增加的高压漏极延伸mosfet
US9299806B2 (en) 2012-11-27 2016-03-29 Taiwan Semiconductor Manufacturing Company, Ltd. High voltage drain-extended MOSFET having extra drain-OD addition
CN112151610A (zh) * 2019-06-27 2020-12-29 南亚科技股份有限公司 半导体元件及其制备方法
CN112151610B (zh) * 2019-06-27 2024-04-16 南亚科技股份有限公司 半导体元件及其制备方法

Also Published As

Publication number Publication date
JP2005109389A (ja) 2005-04-21
TW200514259A (en) 2005-04-16
TWI260783B (en) 2006-08-21
US20050104135A1 (en) 2005-05-19
KR100659619B1 (ko) 2006-12-20
KR20050033018A (ko) 2005-04-08
US7468303B2 (en) 2008-12-23

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