CN1577887A - 半导体装置 - Google Patents

半导体装置 Download PDF

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CN1577887A
CN1577887A CNA2004100476813A CN200410047681A CN1577887A CN 1577887 A CN1577887 A CN 1577887A CN A2004100476813 A CNA2004100476813 A CN A2004100476813A CN 200410047681 A CN200410047681 A CN 200410047681A CN 1577887 A CN1577887 A CN 1577887A
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diffusion layer
insulating film
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CN1324718C (zh
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北原明直
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Sanyo Electric Co Ltd
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Abstract

本发明提供一种减小电容元件的电压依存性且提高PN结耐压的半导体装置。在P型硅基板(1)的表面上配置第一N井(2)，在该第一N井(2)内，与此重叠地配置有第二N井(3)。在栅极绝缘膜(4)上的全面及场绝缘模(5)的一部分上配置栅电极(8)。而且，在第二N井(3)的表面上形成具有高P型杂质浓度的P+型扩散层(6)。P+型扩散层(6)的端部与电场集中的场绝缘膜(5)的端部{连接栅极绝缘膜(4)与场绝缘模(5)的部位}分隔开。即，P+型扩散层(6)的端部，从场绝缘膜(5)的端部，朝栅极绝缘膜(4)的方向，离开内侧地配置。

Description

半导体装置
技术领域
本发明涉及半导体装置，尤其涉及减小电压依存性的电容元件。
背景技术
近年来，正在开发CCD或有机EL显示装置用的驱动器IC。在这种驱动器IC中，由于必须有升压电源，因此作为升压电源电路，例如内置有DC-DC转换器(converter)。在DC-DC转换器中，虽然使用相位补偿用的电容元件，但在电路动作上，要求的是电压依存性小的电容元件。
图6是表示包含这种电容元件的半导体装置的剖面图。在P型硅基板50的表面上配置第一N井(well)51，在该第一N井51内与之重叠地配置第二N井52。在第二N井52上，配置有栅极绝缘膜53与相邻于该栅极绝缘膜53并包围其外围地配置场绝缘膜54。
另外，在栅极绝缘膜53上及场绝缘膜54的一部分上，与这些连接地配置着由金属或多晶硅等导电体构成的栅电极56。然后，在第二N井52的表面上形成具有高P型杂质浓度的P+型扩散层55(也被称为PDD层)。P+型扩散层55的上面连接栅极绝缘膜53，其端部与场绝缘膜54的端部(连接栅极绝缘膜53与场绝缘膜54的部位)匹配地配置着。
在该半导体装置中，由栅电极56、栅极绝缘膜53、P+型扩散层55构成电容元件。栅电极56是相对向于P+型扩散层55的电容电极，介于它们之间的栅极绝缘膜53是电容绝缘膜。而且，由于P+型扩散层55是高浓度，从而可以减小电容元件的电压依存性(比如栅极电压依存性)。
另外，在相关的先行技术文献中比如可以列举专利文献1。
【专利文献1】
特开2000-243979号公报
但是，在将上述的电容元件应用于DC-DC转换器等升压电源电路时，在电路动作中，在由P+型扩散层55和第二N井52形成的PN结上施加高的反向偏压(比如12.5V)。这样，由于在以往例的电容元件中，PN结耐压不够，在电路动作中，产生PN结的雪崩击穿(avalanche breakdown)，从而产生电容元件不能正常发挥作用的问题。
发明内容
本发明的半导体装置的第一特征构成，具有：第一导电型半导体基板；在第一导电型半导体基板的表面上配置的第二导电型的第一井；配置于第一井内的第二导电型的第二井；在第二井的表面上配置的第一导电型的第一扩散层；配置于第一扩散层上的电容绝缘膜；与电容绝缘膜相邻且配置为包围其外围的场绝缘膜；和配置于电容绝缘膜上的电极，第一扩散层的端部从所述场氧化膜的端部分隔地配置。
根据该构成，由第一扩散层、电容绝缘层、电极构成电容元件。而且，由于第一扩散层的端部从电场集中的场氧化膜的端部分隔地配置，因此，提高了由第一扩散层与第二井形成的PN结的耐压。
本发明的半导体装置的第二特征构成，具有：第一导电型半导体基板；在第一导电型半导体基板的表面上配置的第二导电型的第一井；配置于第一井内的第一导电型的第二井；在第二井的表面上配置的第一导电型的扩散层；配置于扩散层上的电容绝缘膜；与电容绝缘膜相邻且包围其外围地配置的场绝缘膜；和配置于电容绝缘膜上的电极。
根据该构成，由扩散层、电容绝缘层、电极构成电容元件。而且，由于扩散层配置在与其为相同导电型的第二井的表面上，因此，由第一井和第二井形成PN结，提高了PN结的耐压。
根据本发明，可以减小电容元件的电压依存性，同时可以提高PN结耐压。尤其是，适宜作为DC-DC转换器等中使用的电容元件。
附图说明
图1是用于实施本发明的最佳实施方式1的半导体装置的平面图。
图2是沿图1的X-X线的剖面图。
图3是用于实施本发明的最佳实施方式2的半导体装置的平面图。
图4是沿图3的Y-Y线的剖面图。
图5是表示电容元件的栅极电压依存性的图。
图6是表示包含以往例的电容元件的半导体装置的剖面图。
具体实施方式
其次，参照附图，对用于实现本发明的最佳方式进行说明。图1是用于实施本发明的最佳实施方式1的半导体装置的平面图。图2是沿图1的X-X线的剖面图。
作为P型半导体基板，比如在P型硅基板1的表面上配置第一N井2，在该第一N井2内与之重叠地配置第二N井3。在第二N井3上，配置栅极绝缘膜4与相邻于该栅极绝缘膜4且包围其外围的场绝缘膜5。场绝缘膜比如可以是由选择氧化法形成的LOCOS氧化膜。栅极绝缘膜4具有比场绝缘膜5薄的膜厚。第一N井2的端部、第二N井3的端部都配置在场绝缘膜5的下方。
而且，在栅极绝缘膜4上的全面以及场绝缘膜5的一部分上，与这些连接地配置有由金属或多晶硅等导电体构成的栅电极8。然后，在第二N井3的表面上形成具有高P型杂质浓度的P+型扩散层6(也称为PDD层)。P+型扩散层6的上面连接栅极绝缘膜4，P+型扩散层6的端部与电场集中的场绝缘膜5的端部(连接栅极绝缘膜4与场绝缘膜5的部位)分隔着。即，P+型扩散层6的端部从场绝缘模5的端部朝栅极绝缘膜4的方向离开内侧地配置，并收纳在活化区域(栅极绝缘膜4之下的第二N井3)内。而且，如图2所示，在场绝缘模5为LOCOS氧化膜时，P+型扩散层6和其飞边尖头(burrs beak)分隔。
在该半导体装置中，由栅电极8、栅极绝缘膜4、P+型扩散层6构成PDD电容元件。栅电极8是相对向于P+型扩散层6的电容电极，介于它们之间的栅极绝缘膜4是电容绝缘膜。而且，由于P+型扩散层6具有高浓度，故可以使电容元件的电压依存性减小(比如栅极电压依存度)。在减小电压依存性方面，P+型扩散层6的P杂质浓度优选为1×1018/cm3～1×1020/cm3。而且，由于P+型扩散层6的端部与电场集中的场绝缘模5的端部分隔，故可以提高由P+型扩散层6与第二N井3形成的PN结的耐压。而且，设置比P+型扩散层6的浓度低，内包该P+型扩散层6的P-型扩散层7，在提高PN结耐压的观点上是优选的。通过离子注入，从而于场绝缘膜5的端部匹配地形成P-型扩散层7。
而且，该半导体装置，在P型硅基板1上配置第一N型井2，在第一N型井2内，与第二N井相邻地配置P井10，具有三重井结构。然后，如上所述，在第二N井3内构成有电容元件，但是还另外形成多个第二N井3，在这种第二N井3内，配置P沟道型MOS晶体管。而且，在P井10内配置N沟道型MOS晶体管。
而且，也可以将P型硅基板1、第一N井2、第二N井3及P井10的极性从P型变更为N型，同时将P+型扩散层6的极性变更成N+型，从而构成NDD电容元件。此时，在减小电压依存性方面，最好使N+型扩散层的N型杂质浓度为5×1018/cm3～5×1020/cm3。
图3是用于实施本发明的最佳实施方式2的半导体装置的平面图。图4是沿图3的Y-Y线的剖面图。另外，对于与图1、图2相同构成的部分附加同样的符号并省略其说明。
上述实施方式1的半导体装置，由于P+型扩散层6与场绝缘模5的端部分隔，因此，在该分隔区域内，在形成有第二N井3或P-型扩散层7的情况下栅电极8与该P-型扩散层7相对向，结果是，电容元件的栅电极电压依存性扩大了一些。因此，在本实施方式中，既可以抑制电容元件的栅电极电压依存性又可以提高PN结的耐压。
在本实施方式中，在第一N井2内配置P井11，在该P井11的表面上配置了P+型扩散层12。P+型扩散层12的端部与场氧化膜5的端部匹配地配置着。比如，以场氧化膜5作为掩膜，通过向栅极绝缘膜4之下的P井11表面离子注入P型杂质(比如硼或BF2)而形成这种配置关系。由此，由于P+型扩散层12配置在栅极绝缘膜4之下的全面上，因此栅电极8通过栅极绝缘膜4与P+型扩散层12对面，不会与浓度比其还低的P井11对面，因此可以将电容元件的栅极电压依存性抑制得小。而且，在该电容元件内，由于低浓度的P井11与第一N井3形成PN结，故可以提高PN结的耐压。
在减小电压依存性方面，与实施方式1同样，优选P+型扩散层12的杂质浓度为1×1018/cm3～1×1020/cm3。
另外，该半导体装置，在P型硅基板1上配置第一N型井2，在第一N型井2内，与P井11相邻地配置第二N井13，具有三重井结构。而且，如上所述，在P井11内构成电容元件，但是还另外形成多个P井11，在这种P井11内，配置N沟道型MOS晶体管。再有，在第二N井13内配置P沟道型MOS晶体管。
而且，也可以将P型硅基板1、第一N井2、第二N井13及P井11的极性从P型变更为N型，同时将P+型扩散层12的极性变更为N+型，从而构成NDD电容元件。此时，在减小电压依存性方面，优选使N+型扩散层的N型杂质浓度为5×1018/cm3～5×1020/cm3。
图5是表示用于实施本发明的最佳实施方式2的PDD电容元件与以往例的PDD电容元件(参照图6)的栅极电压依存性的图。在这里，在用于实施本发明的最佳实施方式2的PDD电容元件中，第二N井3为电浮动状态，在以往例的PDD电容元件中，第一N井51为电浮动状态。从该图可以看出，用于实施本发明的最佳实施方式2的PDD电容元件，与以往例相同程度地减小其栅极电压依存性。

Claims (6)

1.一种半导体装置，其特征在于，具有：
第一导电型半导体基板；
在所述第一导电型半导体基板的表面上配置的第二导电型的第一井；
配置于所述第一井内的第二导电型的第二井；
在所述第二井的表面上配置的第一导电型的第一扩散层；
配置于所述第一扩散层上的电容绝缘膜；
相邻于所述电容绝缘膜且包围其外围地配置的场绝缘膜；和
配置于所述电容绝缘膜上的电极，
所述第一扩散层的端部从所述场氧化膜的端部分隔地配置。
2.如权利要求1所述的半导体基板，其特征在于，
具有比所述第一扩散层浓度低，内包所述第一扩散层的第一导电型的第二扩散层。
3.如权利要求2所述的半导体基板，其特征在于，
所述场绝缘膜的端部与所述第二扩散层的端部匹配地配置着。
4.一种半导体装置，其特征在于，具有：
第一导电型半导体基板；
在所述第一导电型半导体基板的表面上配置的第二导电型的第一井；
配置于所述第一井内的第一导电型的第二井；
在所述第二井的表面上配置的第一导电型的扩散层；
配置于所述扩散层上的电容绝缘膜；
相邻于所述电容绝缘膜且包围其外围地配置的场绝缘膜；和
配置于所述电容绝缘膜上的电极。
5.如权利要求4所述的半导体基板，其特征在于，
所述场绝缘膜的端部与所述扩散层的端部匹配地配置着。
6.如权利要求4或5所述的半导体基板，其特征在于，
在所述第一井内，具有与第二井相邻地配置的第二导电型的第三井。
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