TWI235409B - Semiconductor device - Google Patents

Semiconductor device Download PDF

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TWI235409B
TWI235409B TW093119402A TW93119402A TWI235409B TW I235409 B TWI235409 B TW I235409B TW 093119402 A TW093119402 A TW 093119402A TW 93119402 A TW93119402 A TW 93119402A TW I235409 B TWI235409 B TW I235409B
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well
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diffusion layer
insulating film
insulation film
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TW200504811A (en
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Akinao Kitahara
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Sanyo Electric Co
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    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/92—Capacitors having potential barriers
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/02107—Forming insulating materials on a substrate
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
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    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/0805—Capacitors only
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    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0928—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising both N- and P- wells in the substrate, e.g. twin-tub
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66272—Silicon vertical transistors
    • H01L29/66295—Silicon vertical transistors with main current going through the whole silicon substrate, e.g. power bipolar transistor
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    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
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  • Computer Hardware Design (AREA)
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  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Description

1235409 玖、發明說明 【發明所屬之技術領域】 本發明為有關一種半導體裝置，尤有關於減少電壓依 存性的電容元件。 【先前技術】 近年來’業已開發CCD或有機電場發光（electr〇 lUminescence;以下稱EL)顯示裝置用的驅動器ic。在這 種驅動器1C中，由於必須有升壓電源，因此例如内置有 〇(：-〇(：轉換器（0_咖0以作爲升壓電源電路。在此〜 DC轉換器中’雖然使用相位補償用的電容元件，但在電 路動作上’則須電壓依存性較小的電容元件。 第6圖是表示包含這種電容元件的半導體裝置的 圖。在P型矽基板50的表面上配置第1N阱(_”51 該第1…1内則與其重疊而配置第2…。在第2n 解52上，配置有間極絕緣膜53、以 鄰俾將其周邊包圍之場絕緣膜54。 緣膜53相 另外，在㈣1_53上及場I㈣ 上’配置著有由今屬弋夕a 口刀 者有由金屬或多晶矽等導電 與㈣相鄰接。然後，在第2心2的表面 P型雜質濃度的P+型擴㈣ 〃、向 散層…*係與閛極絕緣膜53:接D:端層= 擴 ^於場絕緣膜W絕緣m場m整合纪 接的部位）。 _、纟巴緣膜54連 在該半導體裝置中 係由閘極電極56、間極絕緣祺 315911 5 1235409 53、P +型擴散層55構成電容元件。閘極電極56、P+型擴 散層55為柄對向的電容電極，而插置在該等之間的閘極絕 緣膜53則為電容絕緣膜。此外，由於p +型擴散層55為高 濃度’從而可以減少電容元件的電壓依存性（例如閘極電壓 依存性）。 另外’在相關的先行技術文獻中，例如有專利文獻1。 [專利文獻1 ] 曰本專利特開2000 — 243979號公報 【發明内容】 [發明欲解決之問題] 但是，在將上述的電容元件應用於DC — DC轉換器等 升壓電源電路時，係在電路動作中，對於由P +型擴散層5 5 和苐2 N味5 2所形成的p is[接合予以施加高的逆向偏壓（例 如12.5V)。於是，由於在習知例的電容元件中，pN接合 耐壓不夠’因此在電路動作中産生PN接合的雪崩崩潰 (avalanche breakdown)，從而産生電容元件不能正常發揮 作用的問題。 [解決問題之方案] 本發明的半導體裝置的第1特徵構成，具有：第1導 電型半導體基板；在第1導電型半導體基板的表面上配置 的第2導電型的第1阱；配置於第1阱内的第2導電型的 第2阱；在第2阱的表面上配置的第1導電型的第1擴散 層，配置於第1擴散層上的電容絕緣膜；與電容絕緣膜相 鄰且配置爲包圍其周邊的場絕緣膜；以及配置於電容絕緣 6 315911 1235409 面圖。第2圖是沿第！圖的χ·χ線的剖面圖。 作爲Ρ型半導體基板，例如在ρ型石夕基板i的表面上 配置第⑽2,在該第内則與其重疊而配置第2 N陕3。在第2NP^ 3上’配置閘極絕緣膜4、以及盘該間 極絕緣膜4相鄰俾包圍其周邊的場絕緣膜5。場絕緣膜例 如可以是由選擇氧化法形成的L〇c〇s氧化膜。閘極絕緣 膜4具有比場絕緣膜5薄的膜厚。第i n味2的端部、第 2 N阱3的端部均配置在場絕緣膜5的下方。 此外，在閘極絕緣膜4上的全面以及場絕緣膜5的一 部分上，係配置有由金屬或多晶料導電體構成的開極電 極8與該等連接。然後，在第2料3的表面形成具有高 P型雜質濃度# P +型擴散層6(亦稱爲PDD層）。p +型擴今 層6的上面係連接於閑極絕緣膜4，p +型擴散層6的端： 係與電場集中的場絕緣膜5的端部⑽極絕緣膜4與場絕緣 膜5連接的部位）分⑮。亦即，p+型擴散層6的端部係從 場絕緣膜5的端部向閘極絕緣膜4的方向朝内側分隔地配 置，收納在活化區域（閘極絕緣膜4之下的第2n_ W中。 此外’如第2圖所示’在場絕緣膜5爲L〇c〇s氧化膜時， P+型擴散層6係與其鳥嘴(bird，s的前端相分隔。 在4半導體裝置中’係由閘極電極8、閘極絕緣膜4、 以及P +型擴散層6構成PDD電容元件。閘極電極8、p + 型擴散層6為相對向的電容電極，而插置在該等之間的閘 極絕緣膜4則為電容絕緣膜。再者，由於p +型擴散層6具 有高濃度’故可以使電容元件的電壓依存性(例如閘極電壓 315911 8 1235409 依存度）減少。在減少電壓依存性方面，p+型擴散層6的p 雜貝派度係以1 x 1 〇 /cm3至1 X 1 〇2〇/cm3為佳。此外，由於 型擴散層6的端部係與電場集中的場絕緣膜5的端部 分隔，故可以提高由P+型擴散層6與第2N# 3形成的 PN接合耐壓。此外，並以設置比p +型擴散層6的濃度低 且將該P+型擴散層6包括在内的p一型擴散層7，在提高 PN接合耐壓的觀點上較理想。p一型擴散層7係在藉由離 子注入，從而整合形成為場絕緣膜5的端部。 此外，該半導體裝置係在P型矽基板丨上配置第i N 型阱2，在第IN型阱2内，與第2N阱相鄰地配置p阱 10，具有二重阱結構。然後，如上前述，在第2N@ 3内 構成有電谷兀件，但是第2N阱3又另外形成多個，而在 14種第2N阱3内，配置p通道型M〇s電晶體。此外， 在P阱10内配置N通道型m〇S電晶體。 此外，也可以將P型矽基板j、第i N阱2、第2 N 阱3及P阱1 〇的極性從p型變更爲N型，同時將p +型 擴散層6的極性變更成N +型，從而構成ndd電容元件。 此時，在減少電壓依存性方面，最好使N+型擴散層的N 型雜質濃度爲5xl〇18/cm3至5xl〇2〇/cm3。 第3圖疋用以實施本發明的最佳第2形態的半導體裝 置的平面圖。第4圖是沿第3圖的γ_γ線的剖面圖。另外， 對於與第1圖、第2圖相同構成的部分附加同樣的符號並 省略其說明。 上述第1形恶的半導體裝置，由於ρ +型擴散層6與場 9 315911 1235409 絕緣膜5的端部分隔 8係在形成有第2心3^ 域内，閘極電極 型擴散層7相對向，L果;1擴散層7時成為與該P — 將會稍增大。因此，二件的閑極電麼依存性 件的間極，壓依存性，—面提高pN接合耐壓。 在本貫施形態中，将尤 係在弟1N阱2内配置P#n，並 的^人的表面配置P+型擴散層12°P+型擴散層12 如而1Γ正口配置於場氧化膜5的端部。此種配置關係例 “氧化膜5作爲遮罩，#由對閘極絕緣膜4之下的p 表面離子/主入p型雜質(例如硼或BF2)而形成。由 ^心P +型擴散層1 2配置在閘極絕緣膜4之下的全 口此閘極電極8透過閘極絕緣膜4而與p +型擴散層12 相對’不會有與濃度比其更低的p阱i "目對之情況，因 此：以將電容元件的閘極電壓依存性抑制得較小。而且， 在4電谷元件中，係由低濃度的p阱丨1與第丨N阱3形成 PN接合，故可以提高pn接合耐壓。 在減少電壓依存性方面，p +型擴散層丨2的p型雜質 濃度係與第1形態同樣，以1><1〇】8/(^3至lxl〇20/cm3為佳。 此外’該半導體裝置係在P型矽基板1上配置第1 N 型阱2,在第1N型阱2内與？阱u相鄰地配置第2N_ 13，具有二重阱結構。再者，如上前述，在ρ —丨1内構 成電容兀件，但是P阱丨丨又另外形成多個，且在此種p 阱11内配置N通道型M〇s電晶體。此外，在第2N_ 13 内配置P通道型]vios電晶體。 10 315911 1235409 而且，也可以將P型矽基板1、第1 N阱2、第2N 阱13及P阱11的極性從p型變更爲N型，同時將p+型 擴散層12的極性變更爲N+型，從而構成NDD電容元件。 此時，在減少電麼依存性方面，係以使N+型擴散層的N 型雜質濃度爲5xl〇18/Cm3至5xl〇2〇/cm3為佳。
第5圖是表示用以實施本發明的最佳第2形態的PDD 電容元”件(參照第！、第2圖）、以及習知例的PDD電容元 件(參照第6圖)的閘極電壓依存性的圖。在此，在用以實 施，發明的最佳第2形態的pDD電容元件中第2 N阱3 二二電f生私狀悲，而在習知例的pDD電容元件中，第1 爲電性漂移狀態。從該圖可以看出，用以實施本 ㈣習/圭弟2形態的PDD電容元件，其閑極電壓依存性 ’…、I知例相同程度地較小。 【圖式之簡單說明】 2 1圖是用以實施本發明的最佳第i形態 置的平面圖。 f版衣 第2圖是沿第1圖的X-X線的剖面圖。 署沾ί 3圖疋用以實施本發明的最佳第2形態的半導體F 置的平面圖。 」干兮篮裝 楚 Λ 圖是沿第3圖的Υ-Υ線的剖面圖。 第6圖疋表示電容元件的閘極電壓依存性的圖。 剖面圖^圖是表示包含習知例的電容元件的半導體裝置的 [元件符號說明] 315911 11 1235409 1、50 3 、 13 、 52 5、54 7 10、11 2 4、53 6 、 12 、 55 8、56 51 P型矽基板 第2 N阱 場絕緣膜 P —型擴散層 P阱 第1 N阱 閘極絕緣膜 P +型擴散層 問極電極 第 1 N 阱（well) 12 315911

Claims (1)

1235409 94 第93 1 19402號專利申請案 申請專利範圍修正本 κ 一料導體裝置，其特徵為具有··（94年4月18日 第1導電型半導體基板； 在別述第1導電型半導^ 導電型的第丨啡；〜基板的表面上配置的第 ^二；剐述第1阱内的第2導電型的第2阱· I則述第2阱的表面上配w ’ 散層； 衣由上配置的弟1導電型的第！揭 :己置於前述第"廣散層上的電容絕緣膜； 相鄰於前述電容絕綾胺 絕緣膜；以及 置為包圍其周邊的場 =置=前述電容絕緣膜上的電極， 浐邱：中别述第1擴散層的端部係從前述場絕緣膜的 編部予以分隔地配4。 犋的 (修正本）315911 1235409 導電型的第1阱； 配置於前述第1阱内的第1導電型的第2阱； 在前述第2阱的表面上配置的第1導電型的擴散 層； 配置於前述擴散層上的電容絕緣膜； 相鄰於前述電容絕緣膜且配置為包圍其周邊的場 絕緣膜；以及 配置於前述電容絕緣膜上的電極。 5. 如申請專利範圍第4項之半導體裝置，其中，前述擴散 層的端部係整合配置於前述場絕緣膜的端部。 6. 如申請專利範圍第4或5項之半導體裝置，其中，在前 述第1阱内，具有與前述第2阱相鄰配置的第2導電型 的第3阱。 (修正本）315911
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