CN1554214A - 电子装配件和构建电子装配件的方法 - Google Patents

电子装配件和构建电子装配件的方法 Download PDF

Info

Publication number
CN1554214A
CN1554214A CNA028178114A CN02817811A CN1554214A CN 1554214 A CN1554214 A CN 1554214A CN A028178114 A CNA028178114 A CN A028178114A CN 02817811 A CN02817811 A CN 02817811A CN 1554214 A CN1554214 A CN 1554214A
Authority
CN
China
Prior art keywords
bump
solder
power supply
ground connection
length
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CNA028178114A
Other languages
English (en)
Other versions
CN1291629C (zh
Inventor
ղķ˹���ܿ�ѷ
詹姆斯·杰克逊
I
达米翁·瑟尔斯
特伦斯·迪斯洪格
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of CN1554214A publication Critical patent/CN1554214A/zh
Application granted granted Critical
Publication of CN1291629C publication Critical patent/CN1291629C/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838Geometry or layout
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/11Printed elements for providing electric connections to or between printed circuits
    • H05K1/111Pads for surface mounting, e.g. lay-out
    • H05K1/112Pads for surface mounting, e.g. lay-out directly combined with via connections
    • H05K1/113Via provided in pad; Pad over filled via
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/16Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
    • H05K1/162Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor incorporating printed capacitors
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3431Leadless components
    • H05K3/3436Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0213Electrical arrangements not otherwise provided for
    • H05K1/0263High current adaptations, e.g. printed high current conductors or using auxiliary non-printed means; Fine and coarse circuit patterns on one circuit board
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09209Shape and layout details of conductors
    • H05K2201/09218Conductive traces
    • H05K2201/09236Parallel layout
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09209Shape and layout details of conductors
    • H05K2201/09372Pads and lands
    • H05K2201/094Array of pads or lands differing from one another, e.g. in size, pitch, thickness; Using different connections on the pads
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09209Shape and layout details of conductors
    • H05K2201/095Conductive through-holes or vias
    • H05K2201/09618Via fence, i.e. one-dimensional array of vias
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621Components characterised by their electrical contacts
    • H05K2201/10734Ball grid array [BGA]; Bump grid array
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/04Soldering or other types of metallurgic bonding
    • H05K2203/0465Shape of solder, e.g. differing from spherical shape, different shapes due to different solder pads
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02PCLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50Manufacturing or production processes characterised by the final manufactured product
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49124On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49126Assembling bases
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49124On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49144Assembling to base an electrical component, e.g., capacitor, etc. by metal fusion
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49124On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49147Assembling terminal to base
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49124On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49147Assembling terminal to base
    • Y10T29/49149Assembling terminal to base by metal fusion bonding
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49174Assembling terminal to elongated conductor
    • Y10T29/49179Assembling terminal to elongated conductor by metal fusion bonding

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Combinations Of Printed Boards (AREA)

Abstract

在电子装配件(10)的衬底上形成焊接凸起(40A、40B),这些焊接凸起具有比其宽度大的长度。通过将电源连接或接地连接的焊球(36A、36B)相互接近放置,从而使回流焊时焊球(36A、36B)相结合,来形成焊接凸起(40A、40B)。但是信号焊球(36C)保持分开。通过将电源焊接凸起(40A)与接地焊接凸起(40B)相邻放置,并且相互平行地延伸以形成电容器。

Description

电子装配件和构建电子装配件的方法
技术领域
本发明总地涉及一种电子装配件,这通常是一种具有封装衬底的电子装配件,该封装衬底利用焊接凸起被紧固到印刷电路板上。
背景技术
通常是在半导体晶片之内和其上制作集成电路,随后将这些半导体晶片切割为单独的半导体芯片。然后,将芯片安装到封装衬底上,并与其进行电连接。接着,将封装衬底安装到印刷电路板上。
焊球通常位于封装衬底的表面上,封装衬底则抵靠在印刷电路板上。然后,对该组合进行加热并使其冷却,使得焊球不但将封装衬底电连接到印刷电路板上,而且形成焊接凸起,在结构上将封装衬底紧固在印刷电路板上。
电信号能够通过印刷电路板和集成电路之间的焊接凸起被提供。其他的多个焊接凸起为集成电路提供电源和进行接地。可能发生这样的情形:大电流会流过一些焊接凸起,特别是那些为集成电路提供电源和进行接地的焊接凸起。这些大电流可能对这些焊接凸起造成损害。通常还将提供电源、接地和信号连接的焊接凸起相互间等距离地放置,这样它们能够占据类似大小的空间。
附图说明
参考附图,以举例的方法对本发明进行说明,其中:
图1是图示了根据本发明一个实施例的电子装配件的部件的横截面图;
图2是将部件放在一起,进行加热并使其冷却之后的与图1相类似的视图;
图3是电子装配件的印刷电路板的焊接凸起和过孔布局的平面图;
图4是图示了更多电子装配件的部件的侧视图;以及
图5是根据本发明另一个实施例的印刷电路板的平面图。
具体实施方式
附图1图示了在相互间被紧固之前的电子装配件10的部件。电子装配件10包括封装衬底子装配件12和印刷电路板子装配件14。
印刷电路板子装配件14包括印刷电路板16、过孔18和接触焊盘20。
印刷电路板16具有包括电源平面22、接地平面24的许多的层以及多个其他的层26。电源平面22与接地平面24由一个层26分开。另一个层26被置于电源平面22顶上,还有一个层26被置于接地平面24的下表面。于是,电源平面22和接地平面24被一个层26相互分开,并且与印刷电路板16的上表面和下表面之间由多个其他的层26间隔开。
过孔18位于印刷电路板16中,并且从其上表面穿过层22、24和26延伸到其下表面。过孔18包括电源过孔18A、接地过孔18B和信号过孔18C。电源过孔18A的下端被连接到电源平面22。接地过孔18B的下端被连接到接地平面24。信号过孔18C不与电源平面22和接地平面24相连接。
接触焊盘20包括电源接触焊盘20A、接地接触焊盘20B和信号接触焊盘20C。电源接触焊盘20A具有从纸面底部到纸面顶部方向上测量的高度,向纸面中测量的宽度,从纸面左侧到右侧测量的长度。长度是宽度的许多倍。所有电源过孔18A上都设置有电源接触焊盘20A。每一个电源过孔18A在沿着电源接触焊盘20A的长度方向的各自的位置处与电源接触焊盘20A附着、连接。同样,电源过孔18A将电源接触焊盘20A平行地连接到电源平面22。在另一个实施例中,在一种被普遍地称为“狗骨(dogbone)”配置的布置中,过孔可以位于接触焊盘之外。
接地接触焊盘20B同样具有高度、宽度以及是宽度许多倍的长度。所有接地过孔18B上都设置有接地接触焊盘20B,使得每个接地过孔18B各自的上端在沿接地接触焊盘20B长度的各自的位置处与接地接触焊盘20B连接。
每个信号接触焊盘20C位于相应的一个信号过孔18C上,并且与其连接。每个信号接触焊盘20C与其他的每个接触焊盘20不相连接。
封装衬底子装配件12包括封装衬底30、过孔32、接合焊盘34和焊球36。封装衬底30也是具有接地平面和电源平面的多层的衬底。过孔包括多个电源过孔32A、接地过孔32B和信号过孔32C。每一个电源过孔32A的上端被连接到封装衬底30中的电源平面,每一个接地过孔32B的上端被连接到封装衬底30中的接地平面。
接合焊盘34包括多个电源接合焊盘34A、接地接合焊盘34B和信号接合焊盘34C,它们所有都位于封装衬底30的下表面上。每个电源接合焊盘34A位于相应的一个电源过孔32A的各自的下端上,每个接地接合焊盘34B位于相应的接地过孔32A的各自的下端上,每个信号接合焊盘34C位于相应的信号过孔32C的各自的下端上。
焊球36包括多个电源焊球36A、接地焊球36B和信号焊球36C。每个电源焊球36A位于相应的一个电源接合焊盘34A的各自的下端上,每个接地焊球36B位于相应的接地接合焊盘34B的各自的下端上,每个信号焊球36C位于相应的信号接合焊盘34C的各自的下端上。
每个相应的电源过孔32A与一个电源接合焊盘34A、一个电源焊球36A和一个电源过孔18A对齐。这些电源焊球36A的中心点相互大约间隔开1mm。右侧的电源焊球36A的中心点与左侧的接地焊球36B的中心点大约间隔1.2mm。这些接地焊球36B的中心点相互大约间隔开1mm。右侧的接地焊球36B的中心点与左侧的信号焊球36C的中心点大约间隔1.2mm。信号焊球36C的中心点相互大约间隔开1.2mm。所有的焊球36A、36B和36C具有相等的大小和质量。所以,电源焊球36A结合后的质量除以电源过孔18A的数目等于接地焊球36B结合后的质量除以接地过孔18B的数目,也等于信号焊球36C结合后的质量除以信号过孔18C的数目。
封装衬底子装配件12被向下放到印刷电路板子装配件14之上,从而焊球36的下表面与接触焊盘20的上表面接触。所有的电源焊球36A与电源接触焊盘20A接触,所有的接地焊球36B与接地接触焊盘20B接触,每个信号焊球36C与相应的一个信号接触焊盘20C接触。
然后,将封装衬底子装配件12和印刷电路板子装配件14的组合置于回流炉中。将焊球36的加热到它们的熔点温度之上,使其熔化。这些电源焊球36A在熔化时,由于它们之间较近的间距而结合;这些接地焊球36B在熔化时,由于它们之间较近的间距而结合。但是,电源焊球36A不会与接地焊球36B相结合。信号焊球36C保持相互间不连接,也保持不与电源焊球36A和接地焊球36B相连接。
然后,将封装衬底子装配件12和印刷电路板子装配件14的组合从回流炉中取出,并使其冷却,使得熔化后的焊球的材料再次固化。电源焊球36A经过固化的材料在图2中由电源焊接凸起40A表示,结合的接地焊球36B由接地焊接凸起40B表示,经过熔化和回流的信号焊球36C由信号焊接凸起40C表示。
每一个电源焊接凸起40A具有高度,以及与电源接触焊盘20A的宽度和长度相对应的宽度和长度。类似地,接地焊接凸起40B具有高度、宽度和长度,宽度和长度对应于接地接触焊盘20B的宽度和长度。同样,电源焊接凸起40A的长度是它宽度的多倍,接地焊接凸起40B的长度是它宽度的多倍。
电源过孔18A的上端通过电源接触焊盘20A被连接到电源焊接凸起40A沿其长度方向的各点上,接地过孔18B的上端连接到接地接触焊盘20B从而在沿接地焊接凸起40B的长度的各自的位置被连接到接地焊接凸起40B。于是,电源焊接凸起40A通过电源过孔18A被平行地连接到电源平面22,接地焊接凸起通过接地过孔18B被平行地连接到接地平面24。
结合电源焊球36A和结合接地焊球36B的优点在于,它们能相互间更接近。于是为其它多个信号焊球36C空出了更多空间。结合电源焊球36A和结合接地焊球36B另外的优点在于,通过单个的焊球36A或36B的潜在大电流能够被分散通过更大的焊接凸起40A或40B上。
图3是对电源焊接凸起40A和接地焊接凸起40B的相对位置更准确的表达。电源焊接凸起40A和接地焊接凸起40B都以矩形表示。信号焊接凸起40C以较大的圆形表示。电源过孔18A、接地过孔18B和信号过孔18C以较小的圆形表示。
能够看出,电源焊接凸起40A和接地焊接凸起40B位于相互平行的线上,相互间直接相邻,各接地焊接凸起40B位于两个电源焊接凸起40A之间。于是,一个电源焊接凸起40A的表面朝向一个接地焊接凸起40B的相应的表面,以形成多个电容。在所图示的例子中,有三个电源焊接凸起40A和三个接地焊接凸起40B,产生了5个电容。该电容有助于减少电源或接地信号的电阻性和电感性的时间延迟。所有电源过孔18A和接地过孔18B都位于矩形区域上,在该矩形区域中没有信号过孔18C,所有的信号过孔18C都围绕在所有电源过孔18A和接地过孔18B所在的矩形区域周围。
图4图示了电子装配件更多的部件。除封装衬底30和印刷电路板16外,电子装配件10还包括半导体芯片50。半导体芯片50中具有电子部件的集成电路。半导体芯片50被安装在封装衬底30上,并且与其电连接。通过焊接凸起40和封装衬底30能够为半导体芯片50中的集成电路以及印刷电路板16提供电信号,或从其得到电信号。
图5图示了通过电源和接地焊接凸起形成电容器的另一种方式。使用了与图3的实施例相类似的标号。电源焊接凸起140具有多个分支140A-E。分支140A-D都从分支140E出发。接地焊接凸起150被提供有多个分支150A-E。分支150A-D都从分支150E出发。分支150A-D都位于分支140A-D之间,使得分支140A-D与分支150A-D交错。已经发现,通过如图所示的将分支“扇形散开(fanning)”到相互之间,能够在给定表面区域上形成更大的电容器。
尽管已经说明并在附图中示出了某些示例性的实施例,但是应该理解,这样的实施例仅仅是说明性的而不是对本发明的限制,并且由于本领域的普通技术人员可以进行修改,所以本发明并不限于所说明和示出的具体构造和布置。

Claims (23)

1.一种电子装配件,包括:
衬底,具有多层,至少其中之一是电源平面;
所述衬底中的多个电源过孔,具有各自的下端和各自的上端,所述下端在各自被间隔开的位置被连接到所述电源平面;以及
在所述衬底上表面上的电源焊接凸起,其具有高度、宽度和长度,所述长度是宽度的多倍,所述电源焊接过孔的上端在沿所述电源焊接凸起的长度的各自被间隔开的位置被连接到所述电源焊接凸起。
2.如权利要求1的电子装配件,还包括:
在所述衬底上表面上的电源接触焊盘,所述电源过孔被连接到所述接触焊盘,所述电源焊接凸起位于所述电源接触焊盘上。
3.如权利要求1的电子装配件,其中所述衬底具有与所述电源平面分开的接地平面,还包括:
所述衬底中的多个接地过孔,具有各自的下端和各自的上端,所述下端在各自被间隔开的位置被连接到接地平面;以及
在所述衬底上表面上的接地焊接凸起,其具有高度、宽度和长度,所述长度是宽度的多倍,所述接地焊接过孔的上端在沿所述接地焊接凸起的长度的各自被间隔开的位置被连接到所述接地焊接凸起。
4.如权利要求3的电子装配件,还包括:
在所述衬底上表面上的接地接触焊盘,所述接地过孔被连接到所述接地接触焊盘,所述接地焊接凸起位于所述接地接触焊盘上。
5.如权利要求3的电子装配件,其中所述电源焊接凸起和接地焊接凸起相互间直接相邻,它们的长度基本上相互平行地延伸,从而具有朝向彼此的表面以形成电容器。
6.如权利要求5的电子装配件,还包括多个电源凸起和接地凸起,它们相互间交错形成了多个电容器。
7.如权利要求1的电子装配件,还包括:
所述衬底中的多个信号过孔;以及
在所述衬底上表面上的多个信号焊接凸起,每个都被连接到单独的一个信号过孔上。
8.如权利要求3的电子装配件,还包括
所述衬底中的多个信号过孔;以及
在所述衬底上表面上的多个信号焊接凸起,每个都被连接到单独的一个信号过孔上。
9.如权利要求7的电子装配件,其中所述电源过孔比所述信号过孔密集。
10.如权利要求7的电子装配件,其中一个电源焊接凸起的质量基本上等于一个信号焊接凸起的质量。
11.如权利要求1的电子装配件,其中所述衬底是印刷电路板。
12.如权利要求11的电子装配件,还包括:
封装衬底;
在所述封装衬底下表面上的多个电源结合焊盘,所述电源结合焊盘被连接到所述电源焊接凸起;以及
在所述封装衬底中的多个电源过孔,每个都有连接到相应的一个所述电源结合焊盘的端。
13.如权利要求12的电子装配件,其中所述封装衬底中的每个电源过孔与所述印刷电路板中相应的电源过孔相对齐。
14.一种电子装配件,包括:
具有多层的衬底,其中所述多层中的一个是电源平面,一个是分开的接地平面;
所述衬底中的多个电源过孔,具有各自的下端和各自的上端,所述下端在各自被间隔开的位置被连接到所述电源平面;
在所述衬底上表面上的电源焊接凸起,其具有高度、宽度和长度,所述长度是宽度的多倍,所述电源焊接过孔的上端在沿所述电源焊接凸起的长度的各自被间隔开的位置被连接到所述电源焊接凸起;
所述衬底中的多个接地过孔,具有各自的下端和各自的上端,所述下端在各自被间隔开的位置被连接到所述接地平面;
在所述衬底上表面上的接地焊接凸起,其具有高度、宽度和长度,所述长度是宽度的多倍,所述接地焊接过孔的上端在沿所述接地焊接凸起的长度的各自被间隔开的位置被连接到所述接地焊接凸起;
所述衬底中的多个信号过孔;以及
在所述衬底上表面上的多个信号焊接凸起,每个都被连接到单独的一个信号过孔上。
15.如权利要求14的电子装配件,还包括:
在所述衬底上表面上的电源接触焊盘,所述电源过孔被连接到所述接触焊盘,所述电源焊接凸起位于所述电源接触焊盘上。
16.如权利要求14的电子装配件,其中所述电源焊接凸起和接地焊接凸起相互间直接相邻,它们的长度基本上相互平行地延伸,从而具有朝向彼此的表面以形成电容器。
17.一种电子装配件,包括:
具有多层的印刷电路板,其中所述的多层中的一个是电源平面,另一个是分开的接地平面;
所述印刷电路板中的多个电源过孔,具有各自的下端和上端,所述下端在各自被间隔开的位置被连接到所述电源平面;
在所述印刷电路板上表面上的电源焊接凸起,其具有高度、宽度和长度,所述长度是宽度的多倍,所述电源焊接过孔的上端在沿所述电源焊接凸起的长度的各自被间隔开的位置被连接到所述电源焊接凸起;
所述印刷电路板中的多个接地过孔,具有各自的下端和各自的上端,所述下端在各自被间隔开的位置被连接到所述接地平面;
在所述印刷电路板上表面上的接地焊接凸起,其具有高度、宽度和长度,所述长度是宽度的多倍,所述接地焊接过孔的上端在沿所述接地焊接凸起的长度的各自被间隔开的位置被连接到所述接地焊接凸起;
所述印刷电路板中的多个信号过孔;
在所述印刷电路板上表面上的多个信号焊接凸起,每个都被连接到单独的一个信号过孔上;
封装衬底:
在所述封装衬底下表面上的多个电源结合焊盘,所述电源结合焊盘被连接到所述电源焊接凸起;
在所述封装衬底中的多个电源过孔,每个都有连接到相应的一个所述电源结合焊盘的端;
在所述封装衬底下表面上的多个接地结合焊盘,所述接地结合焊盘被连接到所述接地焊接凸起;以及
在所述封装衬底中的多个接地过孔,每个都有连接到相应的一个所述接地结合焊盘的端。
18.如权利要求17的电子装配件,其中所述电源焊接凸起的质量除以所述印刷电路板中电源过孔的总数基本上等于一个信号焊接凸起的质量。
19.如权利要求17的电子装配件,其中所述封装衬底中的每个电源过孔与所述印刷电路板中相应的电源过孔对齐。
20.一种构建电子装配件的方法,包括:
将多个焊球附着到第一衬底上,所述焊球包括以第一距离相互间隔开的电源焊球,以及以第二距离相互间隔开的信号焊球,所述第二距离比第一距离大;
将所述焊球抵靠在第二衬底上;
对所述焊球加热使得它们熔化,所述电源焊球相互结合,而所述信号焊球相互间保持不连接;以及
使所述焊球冷却使得它们固化,随后所述电源焊球被平行地连接到公共电源平面上,每个信号焊球被连接到单独的信号过孔上。
21.如权利要求20的方法,其中一个电源焊球具有与一个信号焊球相等的质量。
22.如权利要求20的方法,其中所述焊球包括以比第二距离小的距离间隔开的多个接地焊球,所述接地焊球相互间结合,并且被平行地连接到与所述电源平面分开的公共接地平面上。
23.如权利要求22的方法,其中所述电源焊球和接地焊球形成相互间直接相邻的电源焊接凸起和接地焊接凸起,并且具有基本上相互平行地延伸的长度,从而具有朝向彼此的表面以形成电容器。
CNB028178114A 2001-09-13 2002-08-15 电子装配件和构建电子装配件的方法 Expired - Fee Related CN1291629C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/952,653 2001-09-13
US09/952,653 US6730860B2 (en) 2001-09-13 2001-09-13 Electronic assembly and a method of constructing an electronic assembly

Publications (2)

Publication Number Publication Date
CN1554214A true CN1554214A (zh) 2004-12-08
CN1291629C CN1291629C (zh) 2006-12-20

Family

ID=25493108

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB028178114A Expired - Fee Related CN1291629C (zh) 2001-09-13 2002-08-15 电子装配件和构建电子装配件的方法

Country Status (4)

Country Link
US (2) US6730860B2 (zh)
EP (1) EP1425946B1 (zh)
CN (1) CN1291629C (zh)
WO (1) WO2003024170A1 (zh)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101673725B (zh) * 2008-09-09 2011-02-09 奇景光电股份有限公司 可挠性电路板
CN103702508A (zh) * 2012-09-27 2014-04-02 三菱电机株式会社 挠性基板以及基板连接构造
CN104981089A (zh) * 2014-04-08 2015-10-14 日本航空电子工业株式会社 印刷电路板
CN105702659A (zh) * 2006-03-31 2016-06-22 英特尔公司 单封装无线通信装置
WO2022193326A1 (zh) * 2021-03-19 2022-09-22 华为技术有限公司 封装组件及电子设备

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6885102B2 (en) * 2002-08-26 2005-04-26 Intel Corporation Electronic assembly having a more dense arrangement of contacts that allows for routing of traces to the contacts
US7005736B2 (en) 2002-09-30 2006-02-28 Intel Corporation Semiconductor device power interconnect striping
US20040061241A1 (en) * 2002-09-30 2004-04-01 Osburn Edward P. Semiconductor device power interconnect striping
US7361988B2 (en) * 2003-12-17 2008-04-22 Intel Corporation Apparatuses and methods to route line to line
US6994570B2 (en) * 2004-01-28 2006-02-07 International Business Machines Corporation High performance interposer for a chip package using deformable button contacts
US7612449B2 (en) * 2004-02-24 2009-11-03 Qualcomm Incorporated Optimized power delivery to high speed, high pin-count devices
US7185799B2 (en) * 2004-03-29 2007-03-06 Intel Corporation Method of creating solder bar connections on electronic packages
US7230317B2 (en) * 2004-09-08 2007-06-12 Intel Corporation Capacitor placement for integrated circuit packages
TWI259748B (en) * 2004-09-22 2006-08-01 Murata Manufacturing Co Wiring board and wiring board module
US7280370B2 (en) * 2005-08-26 2007-10-09 Delphi Technologies, Inc. Electronic package and circuit board having segmented contact pads
US20070230150A1 (en) * 2005-11-29 2007-10-04 International Business Machines Corporation Power supply structure for high power circuit packages
WO2008047852A1 (en) * 2006-10-13 2008-04-24 Nec Corporation Multilayer substrate
US20090310320A1 (en) * 2008-06-16 2009-12-17 Weston Roth Low profile solder grid array technology for printed circuit board surface mount components
US10251273B2 (en) 2008-09-08 2019-04-02 Intel Corporation Mainboard assembly including a package overlying a die directly attached to the mainboard
US20110048775A1 (en) * 2009-08-31 2011-03-03 Ibiden Co., Ltd. Printed wiring board and method for manufacturing the same
KR20120039460A (ko) 2010-10-15 2012-04-25 삼성전자주식회사 반도체 패키지
US8680689B1 (en) 2012-10-04 2014-03-25 International Business Machines Corporation Coplanar waveguide for stacked multi-chip systems
US9372205B2 (en) * 2014-01-15 2016-06-21 Taiwan Semiconductor Manufacturing Co., Ltd. Universal probe card PCB design
US9343398B2 (en) * 2014-09-26 2016-05-17 Invensas Corporation BGA ballout partition techniques for simplified layout in motherboard with multiple power supply rail
US11742270B2 (en) 2016-12-15 2023-08-29 Intel Corporation Landing pad apparatus for through-silicon-vias
TWI640229B (zh) * 2017-04-14 2018-11-01 和碩聯合科技股份有限公司 電源信號傳遞結構及其設計方法
CN110312363B (zh) * 2019-06-24 2020-10-16 维沃移动通信有限公司 一种印刷电路板组件及终端

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0669120B2 (ja) 1986-06-20 1994-08-31 松下電器産業株式会社 シ−ルド装置
US5088007A (en) * 1991-04-04 1992-02-11 Motorola, Inc. Compliant solder interconnection
US5643831A (en) * 1994-01-20 1997-07-01 Fujitsu Limited Process for forming solder balls on a plate having apertures using solder paste and transferring the solder balls to semiconductor device
US6025258A (en) * 1994-01-20 2000-02-15 Fujitsu Limited Method for fabricating solder bumps by forming solder balls with a solder ball forming member
JP3363651B2 (ja) 1994-04-21 2003-01-08 キヤノン株式会社 プリント配線板およびその設計方法
JP3473923B2 (ja) 1995-02-27 2003-12-08 新光電気工業株式会社 Bgaパッケージと該パッケージの実装構造
JPH08288626A (ja) 1995-04-19 1996-11-01 Canon Inc Ic及びプリント配線基板
US5607099A (en) * 1995-04-24 1997-03-04 Delco Electronics Corporation Solder bump transfer device for flip chip integrated circuit devices
TW353223B (en) * 1995-10-10 1999-02-21 Acc Microelectronics Corp Semiconductor board providing high signal pin utilization
JPH1056093A (ja) 1996-08-07 1998-02-24 Hitachi Ltd 半導体装置およびその半導体装置を組み込んだ電子装置
US5786630A (en) * 1996-08-07 1998-07-28 Intel Corporation Multi-layer C4 flip-chip substrate
US5842877A (en) 1996-12-16 1998-12-01 Telefonaktiebolaget L M Ericsson Shielded and impedance-matched connector assembly, and associated method, for radio frequency circuit device
US5847936A (en) * 1997-06-20 1998-12-08 Sun Microsystems, Inc. Optimized routing scheme for an integrated circuit/printed circuit board
DE19748689C2 (de) 1997-11-04 2000-01-27 Trenew Electronic Gmbh Niederinduktive Verbindung
US6191475B1 (en) * 1997-11-26 2001-02-20 Intel Corporation Substrate for reducing electromagnetic interference and enclosure
US6064113A (en) * 1998-01-13 2000-05-16 Lsi Logic Corporation Semiconductor device package including a substrate having bonding fingers within an electrically conductive ring surrounding a die area and a combined power and ground plane to stabilize signal path impedances
US6198635B1 (en) * 1999-05-18 2001-03-06 Vsli Technology, Inc. Interconnect layout pattern for integrated circuit packages and the like
JP3343730B2 (ja) * 1999-08-27 2002-11-11 埼玉日本電気株式会社 実装基板及び電気部品の実装方法
JP2001203470A (ja) * 2000-01-21 2001-07-27 Toshiba Corp 配線基板、半導体パッケージ、および半導体装置
US6388890B1 (en) * 2000-06-19 2002-05-14 Nortel Networks Limited Technique for reducing the number of layers in a multilayer circuit board
US6448639B1 (en) * 2000-09-18 2002-09-10 Advanced Semiconductor Engineering, Inc. Substrate having specific pad distribution
US6449169B1 (en) * 2001-02-28 2002-09-10 Siliconware Precision Industries Co., Ltd. Ball grid array package with interdigitated power ring and ground ring

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105702659A (zh) * 2006-03-31 2016-06-22 英特尔公司 单封装无线通信装置
US10439265B2 (en) 2006-03-31 2019-10-08 Intel Corporation Single-package wireless communication device
US10727567B2 (en) 2006-03-31 2020-07-28 Intel Corporation Single-package wireless communication device
US11552383B2 (en) 2006-03-31 2023-01-10 Tahoe Research, Ltd. Single-package wireless communication device
US11942676B2 (en) 2006-03-31 2024-03-26 Tahoe Research, Ltd. Single-package wireless communication device
CN101673725B (zh) * 2008-09-09 2011-02-09 奇景光电股份有限公司 可挠性电路板
CN103702508A (zh) * 2012-09-27 2014-04-02 三菱电机株式会社 挠性基板以及基板连接构造
CN104981089A (zh) * 2014-04-08 2015-10-14 日本航空电子工业株式会社 印刷电路板
CN104981089B (zh) * 2014-04-08 2017-10-27 日本航空电子工业株式会社 印刷电路板
WO2022193326A1 (zh) * 2021-03-19 2022-09-22 华为技术有限公司 封装组件及电子设备

Also Published As

Publication number Publication date
US20030047356A1 (en) 2003-03-13
EP1425946B1 (en) 2013-10-02
US20030136579A1 (en) 2003-07-24
EP1425946A1 (en) 2004-06-09
WO2003024170A1 (en) 2003-03-20
US6996899B2 (en) 2006-02-14
US6730860B2 (en) 2004-05-04
CN1291629C (zh) 2006-12-20

Similar Documents

Publication Publication Date Title
CN1291629C (zh) 电子装配件和构建电子装配件的方法
JP2541775B2 (ja) 容量性負荷が低い接合構造を有する電子構造体
CN1192429C (zh) 线路
US7335995B2 (en) Microelectronic assembly having array including passive elements and interconnects
US7667299B2 (en) Circuit board and method for mounting chip component
CN1930927B (zh) 构造电子组件的方法
US20020105078A1 (en) Semiconductor device, a method for making the same, and an LCD monitor comprising the same
US20070176297A1 (en) Reworkable stacked chip assembly
US6054758A (en) Differential pair geometry for integrated circuit chip packages
CN101276800B (zh) 电路基板及其制造方法
US9839132B2 (en) Component-embedded substrate
US6492620B1 (en) Equipotential fault tolerant integrated circuit heater
CN109075130B (zh) 中间连接器、包括中间连接器的半导体装置和制造中间连接器的方法
US6683781B2 (en) Packaging structure with low switching noises
US20100327452A1 (en) Mounting structure and method of manufacturing the same
KR100326834B1 (ko) 와이어본딩반도체장치및반도체패키지
CN1433574A (zh) 集成电路封装
KR20050042732A (ko) 높은 배선 능력을 갖춘 고밀도 마이크로비아 기판
CN1294484A (zh) 印刷电路板结构
US9929067B2 (en) Ceramic package, method of manufacturing the same, electronic component, and module
EP3745456A1 (en) Decoupling capacitor layers perpendicularly mounted between semiconductor chip and substrate
KR20230158860A (ko) 파워 모듈 및 그 제조 방법
JPH03110768A (ja) 配線パターン接続用チップ
EP1122781A2 (en) High-density mounted device employing an adhesive sheet
JPS61296794A (ja) 電子装置の製造方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20061220

Termination date: 20170815

CF01 Termination of patent right due to non-payment of annual fee