CN1547358A - A data frame buffer memory device and method for Ethernet passive optical network - Google Patents
A data frame buffer memory device and method for Ethernet passive optical network Download PDFInfo
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- CN1547358A CN1547358A CNA2003101168868A CN200310116886A CN1547358A CN 1547358 A CN1547358 A CN 1547358A CN A2003101168868 A CNA2003101168868 A CN A2003101168868A CN 200310116886 A CN200310116886 A CN 200310116886A CN 1547358 A CN1547358 A CN 1547358A
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Abstract
The invention refers to a kind of data frame buffer device and method for Ethernet passive optical network, the buffer device and method in the invention use a structure of first-in first-out, in order to realize the memorization and management to variable-length data frame in the Ethernet, it examines the data frame entering the buffer queue at first, writes them to the memory device with first-in first-out mode, one pointer pointing to the data frame are written to the descriptor memory device, at the same time, the length information of the data frame is written to the second area of the descriptors memory device, one data frame corresponds to a descriptor, these descriptors forms the queue with first-in first-out mode, when the pointer pointing to data frame memory structure occurs chaos in the using process, it causes the data frame generate error, but when uses the next descriptor to be used as the new point of the first-in first-0 out queue, the whole structure can be restored according to the new address, thus it maintains the integrity of the data frame memory structure.
Description
Technical field
The present invention relates to a kind of Frame buffer memory equipment and method that is used for Ethernet passive optical network (EPON).Particularly, the present invention is used for realizing the buffer memory equipment and the method for the Ethernet variable length data frame that two layer medium access control (MAC) exchange chip of EPON system receives and transmits.
Background technology
Regulation according to 802.3 agreements, in the ethernet frame of standard, should comprise one group of data byte, its composition specifically has: the lead code of 7 bytes (preamble), the frame delimiter of 1 byte (SFD), the source address of 6 bytes and 6 byte destination addresses, the length/type territory of 2 bytes, the data field of 46-1500 byte, and the frame check series of 4 bytes.If semiduplex mode of operation, also need to increase the carrier extend territory for length less than the frame of 512 bytes, length is increased to 512 bytes, promptly the length of the frame of Ethernet is the elongated frame from 64 bytes to 1518 bytes.
The Ethernet bag that two layers of exchange chip of Ethernet need buffer memory to receive usually and transmit, different according to the location of the speed of exchange and buffer unit, ethernet frame store multiple implementation method.At present typical method has two kinds: storage of linked list and storage continuously are representative with the two layers of chip GT-48360 of GALILEO company and the LAN91C111 chip of SMSC company.
The storage of linked list structure is applicable to the storage of fixed-length data frames such as asynchronous transfer mode (ATM) cell.It manages a plurality of formations in public internal memory (RAM), this method also is " chained list ".The chain table method is that each unit in particular queue writes pointer, a sequential cells in each pointed internal memory (RAM), thus allow a plurality of data queues fragmented storage in a public RAM.The GT-48360 chip is the individual sheet stored Gigabit Ethernet controller that has.It has just continued the fixed-length data form to the storage of Ethernet bag.It is divided into piece (BLOCK) by the length of the longest bag (1516 byte) of Ethernet basically with sheet stored unit, every address that takies 0X600 byte, if the memory cell of 1 megabit just can be divided into 80, also just can store 80 Ethernet bags.Use the identifier queue technology simultaneously, " feature " of each Ethernet bag noted, feature comprises: block address, packet length, clean culture/multicast mark or the like.In received frame, the storage frame content, extraction and recording feature value are in the identifier formation; In transmitted frame, at first read the characteristic value in the identifier formation, from buffer memory, take out ethernet frame according to these information again.
The storage mode of this Ethernet bag of GT-48360 chip has write down the details of store frames of data, the initial value of read pointer is a block address in read data, it is provided by the identifier formation, and the time of transfer interval one frame of identifier formation reading, writing address, and the preceding address pointer of once reading in the initial value of read pointer and the metadata cache does not have direct relation, if the therefore preceding address pointer of once reading is made mistakes and can not be had influence on reading of data this time.When write data frame, write address also is address in the piece, can not have influence on other ethernet frame if write pointer is made mistakes equally.For elongated Frame, and the processing speed situation of having relatively high expectations, the benefit that such storing mode brings is clearly.And can divide different identifier formations for the ethernet frame of different priorities and different forwarding destination, the feature of the ethernet frame of each identifier queue stores individual features, and the content of frame can be stored in the same memory cell.If but the Bao Changwei master of the Ethernet bag that sends to lack, so this storage organization is just lower for the utilance of memory cell.1,000,000 the memory cell Ethernet bag that can to store about 2,000 length be 64 bytes for example, and if with 1,000,000 memory cell with such structure store frames of data, then can only store 80 Frames, wasted most memory cell.
The LAN91C111 chip has the fast Ethernet controller of buffer memory in the 8K chunk, and it adopts continuous storage mode to the storage of Ethernet bag, and data width is 16 bits.Storage organization comprises the status word of 16 bits, the frame length of 11 bits, the data field of 64～1518 bytes, the not bit data of the control word of 1 byte and 1 byte.The status word of received frame comprises the frame queue mistake, and whether received frame broadcast frame, received frame have or not Cyclic Redundancy Check mistake or the like information, the status word of transmit frame comprises that the mode of operation of chip, auto-negotiation handle or the like information.The frame length territory keeps the length of ethernet frame to remove 2 information, and this numerical value perseverance is an even number, if the length of ethernet frame is odd number, then the value in this territory is littler by 1 than actual value.Data field is the information of whole Ethernet bag.Control word comprises parity information and CRC information, is 1 if be provided with parity information, and then the not bit data of 1 byte after control word is effective content frame.
The storage mode of the Ethernet bag of LAN91C111 chip has effectively utilized memory space in some use occasion, simultaneously owing to the data/address bus of widening, thereby has reduced the read-write clock, has improved the buffer memory operating efficiency.But the read/write pointer of working as a certain moment is made mistakes and then inevitably can be influenced the read/write operation of subsequent frame, cause a series of rascal, especially for the demanding system of processing speed, this mistake almost is inevitably, so just may need more additional control circuits to solve this problem.And realize the situation of sub-category store frames of data if desired, such as minute priority store frames of data etc., just need to use a plurality of same data store organisations, might occur the lower problem of utilance of some storage organization equally, cause the waste of memory cell.
Also have a kind of storage mode to be similar to the storage mode of GT-48360, generally in the network interface card of computer, use.This structure is by the page or leaf storage, will store the RAM paging, and 256 bytes are one page, and the most-significant byte of 16 address ram can be called the page number., to page or leaf 0X7F, have 64 pages and can be used to receive and send Frame from 0X4000-0X7FFF such as the address ram of 16K from page or leaf 0X40.Generally deposit the transmission Frame with preceding 12 pages, deposit receiving data frames for back 52 pages, this can have different configurations as required, but the buffer unit of configuration must be able to be stored an Ethernet bag the longest.If the relatively shorter discontented one page of the Frame of storage must use one page storage, next bag, promptly must be stored by page or leaf if Frame need be stored with multipage than length with one page storage down.Obviously, this storage organization not only has the advantage of the storage mode of GT-48360, and has improved the utilance of memory cell.
For the EPON system, because up time division multiple access (TDMA) access way, therefore especially in two layers of exchange chip of optical network unit at remote side (ONU) equipment, need than the big frame memory capacity of general two layers of exchange chip, if the improper packet loss that can increase far-end ONU equipment of memory capacity, just mean the increase cost and increase memory capacity, and the complexity of increase management, therefore use what kind of storage organization, all most important for cost that reduces whole system and raising systematic function.The another one important parameters that determines EPON systematic function quality simultaneously is whether the upstream bandwidth distribution is reasonable, promptly use what kind of Dynamic Bandwidth Allocation strategy, some good allocated bandwidth strategies often require to provide the mobility status of how finer user data, therefore may require remote equipment that data queue's situation of classification is provided, such as separate service or divide priority or the like.And top present each ethernet frame storage mode of stating all can not well satisfy these needs of EPON system, therefore descriptor first in first out (FIFO) formation that queue structure's integrality is kept in a kind of employing is proposed in the present invention, manage the method for variant pack queue row, so that meet the bag memory requirement of EPON system.
For solving above-mentioned existing in prior technology technical problem, need to consider following aspect:
At first, adopt the sort of managerial structure to come storage and management to the such elongated frame of Ethernet.
The Ethernet bag that two layers of exchange chip of Ethernet need buffer memory to receive usually and transmit, different according to the location of the speed of exchange and buffer unit, ethernet frame store multiple implementation method, typical method has two kinds at present: storage of linked list and storage continuously.Have now found that there are some shortcomings in these implementation methods that companies such as GALILEO and SMSC adopt in practicality: one) storage mode that adopts among the GT-48360 of GALILEO company is applicable to the storage as fixed-length data frames such as ATM cell; Two) the LAN91C111 chip of SMSC company is effectively utilizing memory space aspect the storage of Ethernet bag, but the read/write pointer of working as a certain moment is made mistakes and then inevitably can be influenced the read/write operation of subsequent frame, cause a series of rascal, especially for the demanding system of processing speed, this mistake almost is inevitable.Main contribution of the present invention is to have adopted a kind of pair of first in first out (DFIFO) structure, realize storage and management to the such elongated frame of Ethernet, at first check the Frame that enters buffer queue, it is write Frame RAM according to the memory of first in first out, a pointer that points to this Frame is written to descriptor, the bag of this Frame is long simultaneously also is written in second territory of descriptor, the corresponding descriptor of Frame, these descriptors have been formed a fifo queue again.When confusion took place storage organization pointer DFIFO, total still can be recovered according to new address like this.Kept the storage organization integrality of Frame.This major queue structure is a two-port RAM, though write pointer of needs (MWA) and read pointer (MRA) are also arranged, the read pointer of DFIFO is that descriptor queue produces and control, and the write pointer of FIFO oneself counting produces, and formation is noted down but the address information of first byte should be described symbol.
Secondly, how to guarantee stability, reliability, the high efficiency of the total work under asynchronous read and write clock situation;
In the present invention, consideration will utilize dual port RAM to be used as required storage organization.Specific implementation for dual port RAM will adopt IP kernel, and owing to the reason of hardware cost causes, its scale is absolute limited when design, therefore will consider so whether the current state of RAM allows new frame data to be written among the RAM, if RAM is for full, in order to guarantee the integrality of frame, it will should not be written into; Whether and also will judge has a complete frame to exist among the RAM, if having and receive the request of transmission, at this moment reads whole complete ethernet frame.So the generation (as handshake such as FULL, EMPTY) that the technical problem that the present invention will solve in addition is the state control signal of RAM, they will influence the performance of whole device.
The generation of the RAM state control signal in this device can be divided into two big classes again according to concrete application scenario: one) the read-write clock synchronization in the device; Two) the read-write clock in the device is asynchronous.Under the situation of read-write clock synchronization, its design is very simple, and does not have the application of patent.But reading and writing under the asynchronous situation of clock, it is complicated many that its realization is wanted, and some will relate to other patented technology, as in Xilinx App Notes XAPP131, XAPP175 and XAPP151, related to the method that some RAM state control signals produce, but by the analysis of next joint, will find that their method is not very suitable in our this occasion, they mainly are suitable for some and utilize dual port RAM to design the occasion of a little little FIFO.The auxiliary contribution of another one of the present invention is to have adopted a kind of state control signal of RAM more simply and easily production method.
Summary of the invention
The object of the invention provides a kind of Frame buffer memory equipment that is used for Ethernet passive optical network.
Another object of the present invention provides a kind of Frame caching method that is used for Ethernet passive optical network.
The invention provides a kind of Frame buffer memory equipment that is used for Ethernet passive optical network, it is characterized in that this equipment comprises: Frame input bus and Frame output bus, the data that are connected respectively to the Frame storage device are write inlet and data readout window; Descriptor is write and is made energy control module, produces the enable signal of writing to the descriptor storage device; Descriptor write address generation module produces the address of descriptor in the descriptor storage device that is written into; Descriptor is read address generating module, produces the address of descriptor in the descriptor storage device that is read out; Frame length adds counter, produces Frame length information according to writing enable signal, and this information is written in the frame length and odd even indicating section of descriptor storage device; Frame length down counter, initial value are the Frame length in the descriptor storage device, represent that when this counter is decremented to 0 complete frame is read out; The Frame storage device reads to make energy control module, produces the Frame storage device read to enable control signal; Frame storage device write address generation module produces the initial address of Frame in the Frame storage device, and this initial address is stored in the header addresses part of descriptor storage device simultaneously; The Frame storage device is read address generating module, according to the Frame initial address that is stored in the descriptor storage device header addresses part, the address of reading that produces this Frame; Frame odd even indicating module, reading the enable signal valid period of Frame storage device, the odd even index signal of output data frame; The descriptor storage device is divided into header addresses part and frame length and odd even indicating section, the initial address of store frames of data in the header addresses part, and the length information and the odd even of store frames of data are delivered for a check information in frame length and odd even indicating section; Frame storage device, Frame are written into wherein or are therefrom read.
In the buffer memory equipment of the present invention, also comprise a read-write arbitration modules and a state generation module, state generation module wherein comprises: read address scrambler for one, four comparators, an empty judge module, a full judge module.
In the buffer memory equipment of the present invention, described Frame storage device is the push-up storage of being made up of Double Port Random Memory, and described descriptor storage device is the push-up storage of being made up of Double Port Random Memory.
In the buffer memory equipment of the present invention, the width of described Frame input bus and Frame output bus is 16.
The present invention also provides a kind of Frame caching method that is used for Ethernet passive optical network, it is characterized in that this method is by existing Frame determining step, reading step to form in buffer memory device space determining step, write step, the buffer memory equipment, wherein buffer memory device space determining step further comprises: buffer memory equipment is received new Frame, whether judgment data frame storage device and descriptor storage device be full, if full then this Frame is dropped, if less than, this Frame is allowed to begin to write; Write step further comprises: begin Frame is written to the Frame storage device, write down the initial address of this Frame, and the write address of descriptor storage device adds 1, the initial address of this Frame is write the header addresses part of descriptor storage device, whether judgment data frame storage device is full, if it is full, then this Frame writes and is terminated, and descriptor storage device write address subtracts 1, Frame storage device write address is returned to this Frame initial address, if the Frame storage device less than, this Frame writes continuation, write end up to this frame, and the length information of this Frame is write in the frame length and odd even indicating section of descriptor storage device; Exist the Frame determining step further to comprise in the buffer memory equipment: buffer memory equipment receives that new Frame sends request signal, judge that whether the descriptor storage device is empty, if be empty, then continues to wait for, if be not empty, allow to read a Frame from the Frame storage device; Reading step further comprises: the descriptor storage device is read the address and is added 1, counter O reset, the initial address of sense data frame and frame length information from the descriptor storage device, judge that whether Counter Value is less than frame length, if less than this Frame continued to read, and Counter Value adds 1, if judge that Counter Value is not less than frame length, then this Frame is read and is terminated; Above-mentioned writing and reading all and carry out to Frame storage device and descriptor storage device according to the first-in first-out mode.
Frame caching method of the present invention, in the said write step, also further comprise the step that produces two descriptor write control signals, during first descriptor write control signal, Frame is stored in the header addresses part that initial address in the Frame storage device is stored in the descriptor storage device, the length and the odd even indicating section that during second descriptor write control signal, the frame length information and the odd even indication information of Frame are stored in the descriptor storage device.
Technique scheme of the present invention has overcome the shortcoming of the storage mode of existing elongated Ethernet bag, for example in the storage of linked list mode of 48360 chips at the Ethernet bag of storage during with short Bao Changwei master, it is lower for the utilance of memory cell, 1,000,000 the memory cell Ethernet bag that to adopt storage means described in the invention can store about 2,000 length be 64 bytes for example, use 48360 storage mode then can only store 80 Frames, wasted most memory cell.
Simultaneously since the operating rate of EPON system at 1.25Gbps, if in system so at a high speed, adopt the storage mode of the Ethernet bag of LAN91C111 chip, when appearring in a certain moment circuit, abnormal conditions cause read/write pointer to be made mistakes, then inevitably can influence the read/write operation of subsequent frame, cause a series of rascal.The present invention then by the use of descriptor FIFO, preserves the stored information of data in addition, has guaranteed that the read-write mistake of a frame can not have influence on correct the reading and writing of other frame.
And when the Dynamic Bandwidth Allocation of system mechanism requires according to priority or other standard when dividing a plurality of queue stores with Ethernet, only the descriptor queue among the present invention need be divided into many queue stores, then can be competent at this business, and can not waste the memory cell of data.
Description of drawings
Fig. 1 is the schematic diagram of the two first-in first-out buffer memory device structures of the present invention;
Fig. 2 is the schematic diagram of buffer memory equipment top-level module of the present invention;
Fig. 3 A is the schematic diagram of descriptor memory device structure in the buffer memory equipment of the present invention;
Fig. 3 B is the frame length of descriptor storage device in the buffer memory equipment of the present invention and the schematic diagram of odd even indicating section structure;
Fig. 4 is the schematic diagram of Frame memory device stores structure in the buffer memory equipment of the present invention;
Fig. 5 is the schematic diagram of buffer memory outfit of equipment structure of the present invention;
Fig. 6 is that buffer memory equipment of the present invention writes arbitration process figure;
Fig. 7 is the sequential chart that buffer memory equipment of the present invention allows the WE signal to produce;
Fig. 8 is the sequential chart that buffer memory equipment refusal WE signal of the present invention produces;
Fig. 9 is the sequential chart that buffer memory equipment of the present invention writes the descriptor storage device;
Figure 10 is that signal produces the sequential schematic diagram when stopping after buffer memory equipment of the present invention allows to write;
Figure 11 is a buffer memory equipment write operation flow chart of the present invention;
Figure 12 is that buffer memory equipment of the present invention is read arbitration process figure;
Figure 13 is that buffer memory equipment of the present invention is read the sequential chart that enable signal produces;
Figure 14 is that buffer memory equipment of the present invention is read another sequential chart that enable signal produces;
Figure 15 is a buffer memory equipment read operation flow chart of the present invention;
Figure 16 is that buffer memory equipment of the present invention is read the sequential chart of buffered signal;
Figure 17 is the Gray code function schematic diagram that buffer memory equipment of the present invention is adopted;
Figure 18 is a state generation module detailed structure schematic diagram in the buffer memory equipment of the present invention;
Figure 19 is the flow chart that buffer memory equipment of the present invention is read geocoding;
Figure 20 is the flow chart of buffer memory equipment write address coding of the present invention;
Figure 21 is the dummy status output flow chart of buffer memory equipment of the present invention;
Figure 22 is the full state output flow chart of buffer memory equipment of the present invention;
Figure 23 is the demonstration mode that buffer memory equipment of the present invention is used for Ethernet passive optical network.
Embodiment
Apparatus of the present invention adopt DFIFO structure (principle is seen figure (1)), and this is than the memory management architecture that is easier to realize.The effect of first FIFO is similar to descriptor queue's chained list in other words, the width of data/address bus is 16 bits, the stored Ethernet bag of essential record initial address pointer accounts for 16 bit widths, parity flag 1 bit width that length 15 bit widths of bag and bag are long.Second its major queue structure of FIFO is two-port RAM, the width of data/address bus also is 16 bits, it is used for depositing continuously the data of Ethernet bag, because the original position and the length of the storage data segment of each Ethernet bag all are recorded, take place when chaotic when the storage organization pointer of certain Frame like this, can recover according to the characteristic value that is stored among the FIFO according to the address pointer of storage organization.DWA among Fig. 1: the write pointer of descriptor queue; DRA: the read pointer of descriptor queue; MVVA: the write pointer of metadata cache formation; MRA: the read pointer of metadata cache formation.
Apparatus of the present invention are by adopting the DFIFO structure based on RAM, and that it is showed in figure (2) is the top-level module figure that adopts this structure.Below will be along the implementation method that the decomposition successively of this figure is illustrated this device.By top level diagram as can be known, this device mainly is made of two top-level modules, and one is the descriptor fifo module; One is the metadata cache fifo module, and each module is made up of storage entity and control circuit again.
The signal of whole device and outside is shown in table (1) among Fig. 2.
Table (1)
| Title | I/O | Width | Describe | |
| WR_EN_IN | I | 1 | Whether enable signal is write in the input of this device, and this signal is effective, represent that then this device receiving frame, but be written among the RAM, also will decide according to the read-write arbitration modules.When unit state FULL was effective, this frame was not written among the RAM, otherwise is written among the RAM. | |
| RD_EN_IN | I | 1 | Enable signal is read in the input of this device, this signal is effective, represent that then this device asking transmit frame, whether respond this request, to decide according to the read-write arbitration modules, when unit state AM was effective, response request was read a complete ethernet frame from RAM.Otherwise response request does not continue to wait for effective up to Av. | |
| DATA_IN[15:0] | I | 16 | The input data signal of this device. | |
| FM_ODD_IN | I | 1 | Be used for illustrating that the byte number of the current Frame that receives is odd number or even number. | |
| WR_CLK | I | 1 | Go out the clock of writing of buffer structure, frequency is 62.5MHz. | |
| RD_CLK | I | 1 | Read clock, frequency is 62.5MHz, and the read-write clock is homology not. | |
| | O | 1 | Go into the index signal that whether has at least a complete Frame to read in the buffer structure, effective then the table do not have at least a complete Frame to read. | |
| | O | 1 | Go into the full condition indicative signal of buffer structure, go into buffer structure and represent that completely the remaining space among the storage RAM of buffer structure is not enough to store an Ethernet bag the longest (1516 byte), this signal effectively then represents to go into buffer structure with full, it offers arbitration modules, judges whether to carry out the write operation of next frame. | |
| | O | 1 | Go into the condition indicative signal of buffer structure sky, this signal is effectively represented storage RAM for empty, at present only as test signal. | |
| | O | 1 | The odd even index signal of the byte number of the Frame of reading. | |
| DATA_OUT[15:0] | O | 16 | The outputting data signals of this device. | |
| | O | 1 | The delimitation signal of the data of reading and is read clock synchronization, effectively (" 1 ") expression data/address bus DATA_OUT[15:0] transmitting valid data. |
Signal between the whole device internal module is shown in table (2).
Table (2)
| Title | Width | Describe |
| Add_in[15:0] | 16 | This signal is generated by storage FIFO write address generation module, is used for writing down the current initial address of writing incoming frame in data RAM.It is fed to the initial address data of descriptor FIFO. |
| Add_out[15:0] | 16 | When having complete frame to read among the storage FIFO, under read control signal control, initial address among the descriptor FIFO that reads is used as the initial value of storage FIFO read pointer. |
| Length_in[15:0] | 16 | This signal is generated by the write address generation module of storage FIFO, is used for writing down the current Address Space Number that takies of writing incoming frame at storage FIFO.It is as the frame length information among the descriptor FIFO, and highest order length_in[15 wherein] expression frame parity information. |
| Length_out[15:0] | 16 | When having complete frame to read among the storage FIFO, under read control signal control, the length value of reading from descriptor FIFO is used for controlling reading of entire frame. |
Figure (3) is the storage entity structure chart of descriptor fifo module, and it is made up of the data that comprise information such as address and frame length and odd even indication; It passes through add_in[15:0], add_out[15:0], length_in[15:0], length_out[15:0] these internal signals and storage fifo module get in touch with.Relevant information for a frame that writes the data FIFO module: initial address, frame length and odd even indication are corresponding to a same memory address in the descriptor fifo module.
Figure (4) is the structure chart of storage FIFO, and it utilizes a dual port RAM to realize, can read while write.Ethernet frame is storage continuously in storage FIFO, writes down this frame and initially write pointer when writing each frame, and writing the length information of noting this frame when finishing.If in the process of writing, the full situation of data RAM has appearred, ablation process will finish, and next will write the initial value that pointer is got back to present frame that writes of incoming frame in data RAM, and the write address of the address of descriptor fifo module, frame length and odd even indication will be the memory address of present frame also, and present frame will abandon.
The course of work to the embodiment of the invention is described further below.
Figure (5) is the composition sub modular structure figure of whole device, and wherein the module of grey mark realizes the function of descriptor FIFO, and all the other are used to realize metadata cache FIFO.This device comprises 13 submodules, and each submodule functional description is as follows.
Read-write is arbitrated: provide according to condition indicative signal (FULL and AV) and read to enable and write the control signal that enables, concrete operating process and sequential are seen figure (6)～figure (8);
State produces logic: expire (FULL), empty (EMPTY), have at least complete frame index signal states such as (AV) to produce logical circuit in metadata cache RAM, the realization principle is seen the description of scheming (17)～figure (22) in 5.4 joints;
DWR control: descriptor FIFO writes and enables control logic;
DWA produces: descriptor FIFO write address produces logic;
DRA produces: descriptor FIFO reads the address and produces logic;
The FL+ counter: frame length adds counter, according to writing the length information that enable signal produces ethernet frame, is used as the input data of descriptor FIFO;
The FL-counter: frame length down counter, initial value are the frame length of reading among the descriptor FIFO, when down counter is 0, represent that complete frame reads;
MRD control: data RAM read to enable control logic;
MWA produces: the write address generation module of data RAM;
MRA produces: the address of reading of data RAM produces logic;
ODD indication: frame odd even indication logic;
Descriptor RAM: the storage entity of descriptor FIFO;
The storage entity of storage RAM: storage FIFO.
The realization module of the write operation of frame comprises: read-write arbitration, state produce logic, DWR control, DWA generation, FL+ counter, MWA generation, descriptor RAM, storage RAM, and concrete realization flow figure and sequential are seen figure (9)～figure (11).
The operation principle that frame writes is: when the WR_EN_OUT signal that arbitration modules provides effective, showing DATA_IN[15:0 this moment] data that transmitting on the data signal line need storage, if this moment, the status signal FULL demonstration of device was invalid, expression has data space storage data, also there is the descriptor space to remove to store the frame information of a new frame, produce the write control signal and the address signal of data RAM according to the WR_EN_OUT signal, produce write control signal and the address signal of descriptor RAM simultaneously according to the WR_EN_OUT signal.Write the WR_EN_OUT signal that enable signal just uses arbitration modules to provide in the data RAM module, it is effective status in the process of storage always, last byte up to a Frame is stored or an ablation process forced termination, and the enable signal of the write pointer counter among the descriptor RAM is only at time slot of the beginning of writing each Frame, and the Frame storage finishes, and length counter first clock cycle after stopping to count is effective, descriptor RAM just can write at two and enable when effective, write initial address and its length information and the odd even indication information of Frame storage respectively, therefore, descriptor RAM writes enable signal, be that the WR_EN_OUT signal that arbitration modules provides re-uses through after " writing control " logical process, descriptor RAM writes the initial address of Frame in its first term of validity of writing enable signal, second term of validity writes the length information and the parity information (FM_ODD_IN) of Frame, and data RAM is write enable signal at it and data write in the dual port RAM when effective.
The realization module of frame read operation comprises: read-write arbitration, state produce logic, DRA generation, FL-counter, MRD control, MRA generation, descriptor RAM, storage RAM.Concrete realization flow figure and sequential are seen figure (12)～figure (16).
The operation principle that frame is read is: read enable signal RD_EN_OUT when effective when what arbitration modules provided, process of transmitting expression this moment " free time " then, respond one and sent request, can send a new data frame, and this moment, the state control signal AV of this device was effective, promptly exist a Frame to be read out at least in the device, the RD_EN_OUT signal is the width of 1 clock cycle.RD_EN_OUT is directly imported in the descriptor RAM submodule enable signal as its read pointer generation unit, initial address message, length information and the odd even indication information of while sense data frame in this clock cycle, and initial address message is sent in the read pointer generation unit in the RAM module, initial value as the read pointer counter, and length information is sent in the length down counter, as the initial value of this counter, simultaneously the odd even indicating bit (15BIT) in the length information is maintained in the register.The RD_EN_OUT signal also is input to " reading control " logic in the data RAM submodule simultaneously, produce the enable signal of reading of a RAM, make and finish in these two actions, storage RAM to read enable signal effective immediately, beginning sense data frame enables the length down counter simultaneously and just subtracts " 1 " operation in the data of whenever reading a 16BIT.When the value of length down counter is reduced to " 0 ", export an index signal Fm_end, represent complete reading of Frame, this signal feedback is given " reading control " logic, make the read signal of RAM invalid, coming reading of control data like this is to be unit with the frame, the reading an of frame one frame, and the read signal of this RAM is exported the delimitation signal as the Frame of reading simultaneously.Simultaneously when data RAM read enable signal when effective, then trigger the odd even indicator register simultaneously, output odd even index signal FM_ODD_OUT.
Figure (6) is to write arbitration process figure, when this device is received a new ethernet frame, at first want judgment data RAM or descriptor RAM whether full, if be written in this storage device for full this new frame will be rejected, when also not expiring, this writes request and is accepted, and figure (7) and figure (8) are the sequential explanations of this flow chart, figure (7) expression is accepted to write, and figure (8) expression refusal writes.
When the request that writes is accepted, will enter into the write operation flow chart, see figure (6).Frame is when beginning to be written in the data RAM, initial address is written among the RAM of address, when this frame is writing in the data RAM process, if find that data RAM is full, then this frame will be terminated, and the address that writes of following frame still is that present frame is write that fashionable initial address, and this process is seen the sequential chart description of figure (11) and figure (10).By adopting this method, can reduce those storage of incomplete frame in data RAM, improved the storage efficiency of data RAM.
Figure (9) is the sequential chart that writes descriptor RAM, and wherein the WR_EN_OUT signal is to obtain from arbitrated logic, and storage RAM also is the delimitation signal of Frame from the enable signal of writing of module in fact.And the FIFO_WR_EN signal is the WR_EN_OUT signal through " writing control " logical conversion and obtain.
Figure (12) is to read arbitration process figure, when this device is received a new transmission request, to judge at first whether descriptor RAM is empty, if will do not responded for empty this new request, in this storage device, stored a complete frame at least, be that descriptor RAM is not for empty, at this moment this request of reading is accepted, figure (13) and figure (14) are the sequential explanations of this flow chart, making an immediate response request of figure (13) expression, figure (14) expression wait earlier response request again when the response request condition satisfies.
When response request and response request condition satisfied, device entered the read operation flow chart, sees figure (15).When initiating read operation, that reads present frame from descriptor RAM writes initial address, length and odd even indication information, utilizes these parameters to read a complete frame from data RAM.
Figure (16) is the read operation sequential, wherein the RD_EN_OUT signal is obtained by arbitrated logic, be used for the address and the length information of descriptor queue are read, only need a clock cycle, the Fm_end signal is the index signal of the value of length down counter output when reducing to " 0 ".The EN_OUT signal is that RD_EN_OUT signal and Fm_end signal obtain through " reading control " logic, be used for the data RAM module read enable, in fact also be the demarcation information of sense data frame.The FM_ODD_OUT signal indication is read the parity word joint number indication of frame.
In the present invention, consideration will utilize dual port RAM to be used as required storage organization.Specific implementation for dual port RAM will adopt IP kernel, but owing to the reason of hardware cost causes, its scale is absolute limited when design, therefore will consider so whether the current state of RAM allows new frame data to be written among the RAM, if RAM is for full, in order to guarantee the integrality of frame, it will should not be written into; And also to judge whether exist a complete frame to exist among the RAM,, at this moment read whole complete ethernet frame if having and receive the request of transmission.So generation (as signals such as FULL, EMPTY) that the technical problem that the present invention will solve in addition is the state control signal of RAM, no matter be in write operation, still in read operation, what wherein play key effect is the state control signal of device, it plays an important role to the operating efficiency of whole device, stability etc., the quality of their designs will influence the performance of whole device
For the state control signal how to produce, can be divided into two classes to this device according to the read-write clock in fact: synchronous and asynchronous structure.Synchronization structure is meant the read and write of identical this device of clock control, and asynchronous structure is meant the read and write of removing to control this device with independent clock.Want simple relatively for the design of the state control signal of synchronization structure, do not have the application of patent, and generation that can the Guarantee Status control signal easily, stable performance.But just be difficult to convenient the realization for asynchronous structure, so mainly be to analyze asynchronous structure below, in Xilinx App Notes XAPP131, XAPP175 and XAPP151, the method that has had some RAM state control signals to produce, but by analyzing, its method this occasion in the present invention is not very suitable, they mainly are suitable for some and utilize dual port RAM to design the occasion of a little little FIFO, but this device is owing to will load more a plurality of ethernet frames, its address realm is very big, so those methods are not too reasonable.But some thought can be used for reference, and at first analyzes some theoretical and application of Gray code below, and it is the main foundation of the state generation module logic simplifying of this device.
In Logical Design, owing on the device and line of signal in chip, certain time-delay is arranged all.Condition influence such as the number of the size of time-delay and the length of line, logical block, manufacturing process, operating voltage, temperature are relevant.Owing to be subjected to the effect of these factors, when the level value of multiple signals changes, in the moment that signal changes, the output of combinational logic has sequencing, be not to change simultaneously, tend to occur some incorrect spikings like this, these spikings are exactly " burr ".If have " burr " to occur in the combinational logic circuit, just illustrate that there be " risk " in circuit.Risk tends to have influence on the stability of logical circuit, just as the state in this patent produces circuit, it plays a part crucial for the performance of whole system, because its design will use some many combinational logics of input signal, so when considering the performance of whole device, this piece circuit will be a key.And in the books and article of " pulse and digital circuit " this respect, there have been a lot of methods can be used for judging whether a logical circuit exists " risk ", as Karnaugh map, logical function expression formula by logical function.For the solution of " risk " problem, a good method is that the employing gray code counter replaces common binary counter, because the output of Gray code has only one saltus step at every turn, so just can well avoid the generation of burr.Figure (17) is the schematic diagram of Gray code togray function, and Din is the Input Address signal, and dout is the OPADD signal.Annotate: below the analysis of several figure that will introduce all utilizes VHDL language to describe.
Figure (18) is the condition indicative signal generation module figure that apparatus of the present invention adopt, and it has also adopted Gray code, but it has adopted diverse ways to carry out the generation of status signal.Can see in the drawings by three grades and finishing that read/write address through the geocoding module, becomes Gray code to 8421 yards addresses earlier, and produce the relevant Gray code signal that some need, see that in detail figure (19) reads geocoding and figure (20) write address is encoded.The output signal of read/write address coding module more tentatively obtains state control signal to the signal behind these codings by comparator, emptyg signal, almostemptyg signal again shown in 1-5 numeral among the figure (18); Almostfullg signal, fullg signal.Emptyg signal and almostemptyg signal and read clock, read enable signal and be input to the generation of carrying out the empty status signal in the empty judge module.Almostfullg signal, fullg signal and write clock, write enable signal and be input to the generation of carrying out the full status signal in the full judge module.
The concrete implication of each road signal is as follows among Figure 18:
1 represents the rd_addr_gray1 signal; 2 represent the rd_addr_gray2 signal;
3 represent the rd_addr_gray3 signal; 4 represent the wr_addr_gray1 signal;
5 represent the wr_addr_gray2 signal; 6 represent the emptyg signal;
7 represent the almostemptyg signal; 8 represent the almostfullg signal;
9 represent the fullg signal.
Figure (19) and figure (20) are read and write geocoding flow charts, and be first the rd_addr_gray1 signal in figure (19) when reset signal is effective, rd_addr_gray2 signal, rd_addr_gray3 signal and rd_addr signal initialize.Wr_addr_gray1 signal in figure (20), wr_addr_gray2 signal and wr_addr signal initialize; When becoming, successively read/write address is carried out Gray code in clock signal, and the rd_addr_gray1 signal prolonged a clock respectively and two clock cycle are rd_addr_gray2 signal and rd_addr_gray3 signal.And it is the wr_addr_gray2 signal that the wr_addr_gray1 signal is prolonged a clock.
After rd_addr_gray1 signal, rd_addr_gray2 signal, rd_addr_gray3 signal and wr_addr_gray1 signal, wr_addr_gray2 signal have produced, be sent in the comparator, this comparator is realized the comparison to two signals of input, equates output 1, does not wait output 0.Use four identical comparators altogether, their realization is described below with VHDL language:
emptyg＜＝′1′when?wr_addr_gray2＝rd_addr_gray2?else′0′；
almostemptyg＜＝′1′when?wr_addr_gray2＝rd_addr_gray1?else′0′；
fullg???????＜＝′1′when?wr_addr_gray2＝rd_addr_gray3?else′0′；
almostfullg?＜＝′1′when?wr_addr_gray1＝rd_addr_gray3?else′0′；
Figure (21) and figure (22) are the flow charts of empty state output and the output of full state, owing to relevant with the full state be the write operation of device, so needs with the full state with write clock synchronization.And relevant with the empty state is the read operation of device, so also need the empty state and read clock synchronization.
Figure (23) is the concrete exemplary embodiment used of apparatus of the present invention in the EPON System on Chip/SoC.The EPON system is made up of local side apparatus OLT and remote equipment ONU, and in the description of figure in (23) is a The general frame of OLT side chip.It is made up of modular units such as interface unit, buffer structure unit, the up processing of MPCP, MPCP downlink processing, control client, multiplexing, parsing, MAC layer, RS layers.
The workflow of entire circuit is on sending direction, from the signal that interface is sent here, in interface module, carry out some earlier and handle, as data width 8bit to the conversion of 16bit etc.Owing in the EPON system, need to insert some MPCP protocol frames, utilize the buffer structure unit that the frame elder generation buffer memory that receives is got off, when not sending the MPCP protocol frame, from buffer structure, frame is read again, like this after the multiple connection of finishing frame, enter MAC layer, RS layer, realize IEEE 802.3 protocol functions.
On receive direction, from the data that RS layer, MAC layer are come, by resolving the MPCP protocol frame is found out, and be sent in the MPCP uplink processing module, and remaining frame is sent in the buffer structure unit, when interface unit is idle, frame is read.
Can see by top workflow, in the EPON system, just realize the insertion and the parsing of MPCP frame easily, and guaranteed the efficient, stable of whole system by adopting buffer structure of the present invention unit to make.
In addition, apparatus of the present invention also can be applied in other some application scenarios, as two layers of ethernet controller or the like easily.
Claims (6)
1. Frame buffer memory equipment that is used for Ethernet passive optical network is characterized in that this equipment comprises:
Frame input bus and Frame output bus, the data that are connected respectively to the Frame storage device are write inlet and data readout window;
Descriptor is write and is made energy control module, produces the enable signal of writing to the descriptor storage device;
Descriptor write address generation module produces the address of descriptor in the descriptor storage device that is written into;
Descriptor is read address generating module, produces the address of descriptor in the descriptor storage device that is read out;
Frame length adds counter, produces Frame length information according to writing enable signal, and this information is written in the frame length and odd even indicating section of descriptor storage device;
Frame length down counter, initial value are the Frame length in the descriptor storage device, represent that when this counter is decremented to 0 complete frame is read out;
The Frame storage device reads to make energy control module, produces the Frame storage device read to enable control signal;
Frame storage device write address generation module produces the initial address of Frame in the Frame storage device, and this initial address is stored in the header addresses part of descriptor storage device simultaneously;
The Frame storage device is read address generating module, according to the Frame initial address that is stored in the descriptor storage device header addresses part, the address of reading that produces this Frame;
Frame odd even indicating module, reading the enable signal valid period of Frame storage device, the odd even index signal of output data frame;
The descriptor storage device is divided into header addresses part and frame length and odd even indicating section, the initial address of store frames of data in the header addresses part, and the length information and the odd even of store frames of data are delivered for a check information in frame length and odd even indicating section;
Frame storage device, Frame are written into wherein or are therefrom read.
2. according to the buffer memory equipment of claim 1, it is characterized in that this equipment also comprises a read-write arbitration modules and a state generation module, state generation module wherein comprises: read address scrambler for one, four comparators, an empty judge module, a full judge module.
3. according to the buffer memory equipment of claim 1, it is characterized in that the push-up storage of described Frame storage device for being made up of Double Port Random Memory, described descriptor storage device is the push-up storage of being made up of Double Port Random Memory.
4. according to the buffer memory equipment of claim 1, it is characterized in that the width of described Frame input bus and Frame output bus is 16.
5. Frame caching method that is used for Ethernet passive optical network is characterized in that this method by existing Frame determining step, reading step to form in buffer memory device space determining step, write step, the buffer memory equipment,
Wherein buffer memory device space determining step further comprises:
Buffer memory equipment is received new Frame, and whether judgment data frame storage device and descriptor storage device be full, if full then this Frame is dropped, if less than, this Frame is allowed to begin to write;
Write step further comprises:
Begin Frame is written to the Frame storage device, write down the initial address of this Frame, and the write address of descriptor storage device adds 1, the initial address of this Frame is write the header addresses part of descriptor storage device, whether judgment data frame storage device is full, if it is full, then this Frame writes and is terminated, and descriptor storage device write address subtracts 1, Frame storage device write address is returned to this Frame initial address, if the Frame storage device less than, this Frame writes continuation, write end up to this frame, and the length information of this Frame is write in the frame length and odd even indicating section of descriptor storage device;
Exist the Frame determining step further to comprise in the buffer memory equipment:
Buffer memory equipment receives that new Frame sends request signal, judges whether the descriptor storage device is empty, if be empty, then continues to wait for, if be not empty, allows to read a Frame from the Frame storage device;
Reading step further comprises:
The descriptor storage device is read the address and is added 1, counter O reset, and the initial address of sense data frame and frame length information from the descriptor storage device,
Whether judge Counter Value less than frame length, and if less than this Frame continued to read, and Counter Value adds 1, if judge that Counter Value is not less than frame length, then this Frame is read and is terminated;
Above-mentioned writing and reading all and carry out to Frame storage device and descriptor storage device according to the first-in first-out mode.
6. according to the Frame caching method of claim 5, it is characterized in that in the said write step, also further comprising the step that produces two descriptor write control signals, during first descriptor write control signal, Frame is stored in the header addresses part that initial address in the Frame storage device is stored in the descriptor storage device, the length and the odd even indicating section that during second descriptor write control signal, the frame length information and the odd even indication information of Frame are stored in the descriptor storage device.
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| CN1282339C (en) | 2006-10-25 |
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