CN101150589B - A data conversion method and device for link layer - Google Patents
A data conversion method and device for link layer Download PDFInfo
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- CN101150589B CN101150589B CN2006101132855A CN200610113285A CN101150589B CN 101150589 B CN101150589 B CN 101150589B CN 2006101132855 A CN2006101132855 A CN 2006101132855A CN 200610113285 A CN200610113285 A CN 200610113285A CN 101150589 B CN101150589 B CN 101150589B
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Abstract
The invention discloses a data conversion method for link layers and a device therefor, the method comprises: step A. conversing frame data sent from a physical layer processing unit; and/or step B. conversing data sent from a network layer processing unit; the step A comprises: buffering frame data sent from the physical layer processing unit to an asynchronous buffered interface with a write back mechanism, conversing the frame data and sending to the network layer processing unit; the step B comprises: conversing the data sent from the network layer processing unit, buffering the conversedframe data to the asynchronous buffered interface with a write back mechanism, then sending to the physical layer processing unit. The invention not only realizes data buffer and clock isolation of the physical layer processing and the link layer processing, realizes more agile interfaces of the physical layer and the link layer and data conversion of the link layer. The invention can be widely applied to a repeater system based on FPGA or ASIC.
Description
Technical field
The present invention relates to data communication field, relate in particular to a kind of data transfer device and device that is used for link layer, to realize interface and the link layer data transaction between the physical layer and link layer flexibly.
Background technology
Digital network system with the interface of synchronous optical network on, common selection at present is to use SPI-3 interface (System Packet Interface Level-3, system's packet interface-3), the SPI-3 interface is the interface shape that is used for networked physics layer (ground floor) device and link layer (second layer) device interconnection that OIF (OpticalInternetworking Forum, optical interconnection forum) recommends.
In the traditional design scheme of data network, usually there is dual mode to realize the data processing of link layer: first kind, be outside system, to increase an independent link layer process chip, adopt a ppu to realize link layer process and traffic management task, can increase design cost so on the one hand, on the other hand, also can increase design difficulty; Second kind, be to use the general-purpose device of supporting SPI-3 interface and link layer process, but be to use this mode to a great extent the limit design personnel to the selection of function element.
Development along with modern network technology and IPv6 technology, performance requirement for routing device is more and more higher, this makes and more use ASIC (Application Specific IntegratedCircuit, application-specific integrated circuit (ASIC)) device rather than network processing unit in high-end router.Realizing that ASIC has own advantageous advantage aspect the high-end data product, but because the inferior position on its development and maintenance difficulty, cause in the reality research and development and in using feasibility can reduce greatly.And FPGA (Field Programmable GateArray, field programmable gate array) has the characteristics of Reprogrammable, therefore safeguard than ASIC greater advantage is arranged in new function, and do not have too big difference on the performance, high-end router is being attempted aspect the use FPGA in recent years.Though there is FPGA producer that the kernel of SPI-3 interface is provided, lack enough flexibilities when being to use, function is also perfect inadequately, especially also has many defectives on the may command ability, brings a lot of inconvenience for the application of FPGA in the network equipment.
Summary of the invention
At above-mentioned defective, the object of the present invention is to provide a kind of data transfer device and device that is used for link layer, to realize physical layer and interconnected interface and the link layer data transaction of link layer flexibly.
To achieve these goals, the invention provides a kind of data transfer device that is used for link layer, comprising:
The frame data that physical layer processing unit is sent carry out data transaction; And/or
The data that the network layer handles unit is sent are carried out data transaction; Wherein,
The step that the described frame data that physical layer processing unit is sent carry out data transaction comprises: the frame data that physical layer processing unit is sent are cached to the asynchronous buffer interface with write-back mechanism, and described frame data are carried out sending to the network layer handles unit after the conversion process;
The step that the described data that the network layer handles unit is sent are carried out data transaction comprises: the data that the network layer handles unit is sent are carried out conversion process, and send to physical layer processing unit after will being cached to the asynchronous buffer interface with write-back mechanism through the frame data of conversion process gained.
The method according to this invention, described have the asynchronous buffer interface of write-back mechanism as the SPI-3 interface between physical layer and the link layer.
The method according to this invention, described asynchronous buffer interface with write-back mechanism are added at skin by dual port RAM reads address control circuit and the write address control circuit is realized.
The method according to this invention, the step that the described frame data that physical layer processing unit is sent carry out data transaction further comprises:
A, described asynchronous buffer interface will receive the frame data that come from physical layer processing unit and carry out data buffering and clock isolation;
B, the frame data of buffer memory are carried out the frame analysis and select handling;
C, send to CPU after going up information header for the frame data encapsulation that needs CPU to handle;
D, separate frame, generate the network layer message and send to the network layer handles unit for the frame data that need SCN Space Cable Network layer processing unit processes.
The method according to this invention is only made the data buffering with a described asynchronous buffer interface in the described steps A and clock isolation is handled.
The method according to this invention, described steps A further comprises:
A1, according to the gross space value of described asynchronous buffer interface and the usage space value calculate the remaining space value of asynchronous buffer interface;
A2, the typical value of the remaining space value of the asynchronous buffer interface that obtains in the steps A 1 and the some condition indicative signals that prestore is compared obtaining the current state index signal, described condition indicative signal comprises the sky of fixed configurations, with sky, completely, will expire and user configured predefine sky, predefine full;
A3, will as the current state index signal full, will expire or predefine is completely delivered to described write address control circuit to realize writing control;
A4, will be as the sky of current state index signal, sky or predefine sky are delivered to the described address control circuit of reading to realize reading control.
The method according to this invention, the step that the described data that the network layer handles unit is sent are carried out data transaction further comprises:
E, handle, obtain sending to described asynchronous buffer interface behind the frame data and handle for carry out framing from the data of network layer handles unit;
F, handle, obtain sending to described asynchronous buffer interface behind the frame data and handle for carry out framing from the data of CPU;
G, described asynchronous buffer interface will send to physical layer processing unit again and handle after will carrying out data buffering and clock isolation through step e and/or the resulting frame data of step F.
The method according to this invention further comprises the processing from the data of network layer handles unit in the described step e:
E1, described network layer handles unit send data to the network layer interface request;
E2, judge whether this network layer interface is full, if execution in step E3 then, otherwise execution in step E4;
E3, carry out the data discard processing, and return wait state;
E4, the data that described network layer handles unit is sended over write network layer interface.
The method according to this invention further comprises the processing from the data of CPU in the described step F:
F1, described CPU send data to the cpu i/f request;
F2, judge whether this cpu i/f is full; If execution in step F3 then, otherwise execution in step F4;
F3, carry out the data discard processing, and return wait state;
F4, the data that described CPU is sended over write cpu i/f.
The method according to this invention, the asynchronous buffer interface further comprises to the step of physical layer processing unit transmit frame data among the described step G:
G1, described asynchronous buffer interface are to corresponding physical layer receiving port request transmit frame data;
G2, continue to judge whether described corresponding physical layer receiving port is effective; If execution in step G3 then, otherwise execution in step G4;
G3, described asynchronous buffer interface are to corresponding physical layer receiving port transmit frame data;
G4, by waiting for that counter counts, and gained count value and the threshold values that presets are compared;
G5, judge that whether this count value surpasses threshold values, if, execution in step G6, otherwise return step G2;
G6, carry out the data discard processing.
The present invention also provides a kind of DTU (Data Transfer unit) that is used for link layer, comprising:
Asynchronous buffer interface with write-back mechanism is used for the data buffering between physical layer processing unit and link layer process unit;
Frame receives processing unit: be used for the frame data of sending and be buffered in described asynchronous buffer interface from physical layer processing unit are carried out conversion process, and the data of conversion process gained are sent to the network layer handles unit;
Frame sends processing unit: the data that are used for the network layer handles unit is sent are carried out conversion process, and send to physical layer processing unit after will being cached to described asynchronous buffer interface through the frame data of conversion process gained.
According to device of the present invention, described asynchronous buffer interface is as the SPI-3 interface between physical layer and the link layer.
According to device of the present invention, described asynchronous buffer interface comprise dual port RAM with and outer add read address control circuit and write address control circuit.
According to device of the present invention, described asynchronous buffer interface further comprises:
Subtracter is used for the remaining space value of calculating the asynchronous buffer interface with spatial value and gross space value according to the asynchronous buffer interface;
Comparator, be used to store fixed configurations and user configured some condition indicative signals and typical value thereof, and the remaining space value and the described typical value of described asynchronous buffer interface compared, draw the current state index signal, should send to described write address control circuit to realize writing control by current condition indicative signal, perhaps send to the described address control circuit of reading to realize reading control.
According to device of the present invention, the condition indicative signal that prestores in the described comparator comprise fixed configurations sky, with sky, full, will expire and user configured predefine sky, predefine full; And will be full as the signal of current indicative signal, will expire or predefine is completely delivered to described write address control circuit, and the signal sky, sky or predefine sky are delivered to the described address control circuit of reading.
According to device of the present invention, described frame receives processing unit and further comprises:
Frame analytic unit: be used for processing is analyzed and selected to the frame data that are buffered in described asynchronous buffer interface;
Information header processing unit: be used for information header is gone up in the frame data encapsulation of delivering the CPU processing from the needs of described frame analytic unit reception, and send to described CPU;
Separate frame processing unit: be used for the frame data of delivering the network layer handles cell processing from the needs of described frame analytic unit reception are separated frame, be sent to the network layer handles unit to generate the network layer message.
According to device of the present invention, described frame sends processing unit and further comprises:
Become frame processing unit: be used for the data encapsulation that network layer handles unit and/or CPU send here is become frame data, send to physical layer processing unit after being cached to described asynchronous buffer unit with write-back mechanism;
Wait for counter, it is subjected to the control of described one-tenth frame processing unit and disposes threshold values;
When described asynchronous buffer interface to physical layer processing unit transmit frame data and corresponding physical layer receiving port when stopping to receive, become frame processing unit to trigger and wait for rolling counters forward, when count value exceeds described threshold values, described one-tenth frame processing unit carries out the discard processing of frame data according to the drop mechanism that presets.
The present invention adopts the FIFO with write-back mechanism as the asynchronous buffer interface in the link layer data transaction, not only realize the data buffering and the clock isolation of physical layer process and link layer process, and can delete, thereby physical layer and interconnected interface and the link layer data transaction of link layer have more flexibly been realized to the frame data that write.In addition, the present invention can add more status signal in the asynchronous buffer interface, and is feasible more perfect for the control of asynchronous buffer interface, can increase the preliminary treatment ability to link-layer frame, makes the realization of product more simplify.
Description of drawings
Fig. 1 is the structural representation of link layer DTU (Data Transfer unit) of the present invention in system.
Fig. 2 is the structure chart of link layer DTU (Data Transfer unit) of the present invention at receive direction.
Fig. 3 is the structure chart of link layer DTU (Data Transfer unit) of the present invention at sending direction.
Fig. 4 is the scheduling mechanism flow chart of the present invention at sending direction.
Fig. 5 is the packet loss schematic diagram of mechanism of the present invention at sending direction.
Fig. 6 is the structural representation of asynchronous buffer interface of the present invention.
Embodiment
Present invention is described below in conjunction with Fig. 1, and Fig. 1 is the structural representation of link layer DTU (Data Transfer unit) in system, comprising:
Fiber optic network 101: physical layer data can transmit in fiber optic network 101.
Physical layer processing unit 102: it is connected with link layer DTU (Data Transfer unit) 103 by SPI-3 interface 110, finishes the conversion between the light signal and the signal of telecommunication: at receive direction, light signal is converted to the signal of telecommunication; At sending direction, be light signal with electrical signal conversion.
Network layer handles unit 104: carrying out the network layer message forwarding and handle, is not emphasis of the present invention.
Facility interface 109: the interface of fiber optic network 101 and physical layer processing unit 102.
SPI-3 interface 110: the interface of physical layer processing unit 102 and link layer DTU (Data Transfer unit) 103, because descending physical layer interface has a plurality of ports, the SPI-3 interface 110 that therefore is connected with it adopts the work of multi-port (multiport) pattern.Described SPI-3 interface 110 of the present invention is realized by asynchronous buffer interface 107 and/or 108.Certainly, SPI-3 interface 110 is not unique physical layer and the interface between the link layer, can be replaced by SPI-4 interface or SPI-5 interface yet.
Data buffering 111: the interface of link layer DTU (Data Transfer unit) 103 and network layer handles unit 104 is used for the IP bag of being received and dispatched is carried out buffered.
Link layer information table (interface attributes) 112: the interface message of storage physical layer and and based on the business information of interface, little with relation of the present invention.
Link layer DTU (Data Transfer unit) 103: be emphasis of the present invention, described link layer DTU (Data Transfer unit) 103 further includes asynchronous buffer interface 107 and 108, and frame receives processing unit 105 and frame sends processing unit 106, wherein:
Asynchronous buffer interface 107: the physical layer processing unit 102 on the receive direction and the interface of link layer DTU (Data Transfer unit) 103, described asynchronous buffer interface 107 is realized by the FIFO with write-back mechanism, specifically referring to Fig. 6 and explanation thereof, it not only can realize the data buffering and the clock isolation of physical layer process and link layer process, thereby can avoid because the metastable state that asynchronous clock causes occurs, and the frame data of having the ability to have write delete, and the described frame data that write can be useless frames such as erroneous frame or invalid frame.
Asynchronous buffer interface 108: the link layer DTU (Data Transfer unit) 103 on the sending direction and the interface of physical layer processing unit 102, described asynchronous buffer interface 108 is structurally just the same with asynchronous buffer interface 107, but a little other functions have been increased, for example hereinafter described wait counter.
Frame receives processing unit 105: be used for the frame data of sending and be buffered in described asynchronous buffer interface 107 from physical layer processing unit 102 are carried out conversion process, and will send to network layer handles unit 104 through the data of conversion process gained.
Frame sends processing unit 106: the data that are used for network layer handles unit 104 is sent are carried out conversion process, and will be cached to described asynchronous buffer interface 108 through the frame data of conversion process gained, send to physical layer processing unit 102 again.
Wherein, on receive direction, link layer DTU (Data Transfer unit) 103 will be put into asynchronous buffer interface 107 buffer memorys from the frame data of being sent by physical layer processing unit 102 that SPI-3 interface 110 is received; On sending direction, the network layer message that link layer DTU (Data Transfer unit) 103 is sent network layer handles unit 104 here is buffered in asynchronous buffer interface 108 after being processed into frame data, sends to physical layer processing unit 102 by SPI-3 interface 110 again.What deserves to be mentioned is, behind the data extract frame that physical layer processing unit 102 is sent here, link layer DTU (Data Transfer unit) 103 is only done clock isolation and data buffering processing (asynchronous buffer interface 107) by an asynchronous FIFO at SPI-3 interface 110 receive directions, as long as fifo status allows, just can receive the data that physical layer processing unit 102 sends, thereby make interface operation farthest simplify.Simultaneously because 110 SPI-3 interfaces carry out write operation to asynchronous buffer interface 107, and 103 of link layer DTU (Data Transfer unit) are done read operation to asynchronous buffer interface 107 and the processing of frame will be finished after asynchronous buffer interface 107 buffered, thereby two clock zones are kept apart fully, avoided the metastable state phenomenon that asynchronous clock caused.
In addition, for fear of to writing chaotic data in asynchronous buffer interface 107 or 108, therefore to filter, have only when control signal be followed successively by " data effectively and transmission beginning "-" data effectively and start of heading "-when " data effectively and ENMES ", just think frame data and be written among the inner FIFO, otherwise lose as useless frame (for example invalid frame or erroneous frame), if write partial data in asynchronous buffer interface 107 or 108, because this asynchronous buffer interface 107 or 108 has write-back mechanism, can delete the frame data that write.For the data that needs abandon, only the original position of the next frame of pointed can need be removed the data that write just now.
Because asynchronous buffer interface 107 and 108 all is 36 bit wides, and SPI-3 interface 110 need the data of read-write to comprise " RDAT[31:0], RMOD[1:0]; RSOP, REOP, RERR; RSX " have 38, so will flag bit (high 4) be encoded, decode again at output at input.Asynchronous buffer interface 107 and the 108 coding rule ginsengs at SPI-3 interface 110 are shown in Table 1.
SOP: data initial (Start Of Packet);
EOP: ED (End Of Packet);
RSX: transmit initial (Receive Start of Transfer);
ERR: error in data.
| din[35] | din[34] | din[33] | din[32] | Corresponding field |
| 0 | 0 | 0 | 1 | SOP |
| 0 | 0 | 1 | 0 | EOP |
| 0 | 0 | 1 | 1 | RSX |
| 1 | 1 | 1 | 1 | ERR |
Table 1
Each interface among the present invention generally adopts packet-level (bag level) mode to realize interface, can certainly adopt byte-level (position level) mode to realize interface, like this can the more efficient use bandwidth.
The present invention adopts the FIFO with write-back mechanism as the asynchronous buffer interface in the link layer data transaction, not only realize the data buffering and the clock isolation of physical layer process and link layer process, and can delete, thereby physical layer and interconnected interface and the link layer data transaction of link layer have more flexibly been realized to the frame data that write.The present invention can be applied to the network equipment based on FPGA or ASIC.In addition, the present invention can become the checking in early stage of ASIC, as Embedded POS-PHY Level 3 (Packet Over SONET PHYsical Level 3 as the realization of FPGA, bag on the SONET physical layer-3) interface is applied in the communication products of chipization.
Fig. 2 be link layer DTU (Data Transfer unit) of the present invention at the receive direction structure chart, frame among Fig. 1 receives processing unit 105 and further comprises:
Frame analytic unit 113: be used for the frame data of sending from physical layer processing unit 102 that are buffered in asynchronous buffer interface 107 are analyzed and select handling, flowing to analytically the flow direction that decides frame by frame informations such as the frame head that extracts and input slogans.For IPv6 (Internet Protocol Version 6, IPv 6), IPv4 (Internet Protocol Version 4, internet protocol version four), MPLS (Multi Protocol Label Switch, multi protocol label exchanges) and protocol frame etc., network layer handles unit 104 or CPU 118 given respectively; Can directly abandon for useless frames such as erroneous frame, invalid frames.
Information header processing unit 114: deliver the frame data packaging information head that CPU118 handles for the needs that receive from described frame analytic unit 113, and these information headers are attached to send data the front by cpu i/f 116 transmitted to CPU 118.For example need the protocol frame that CPU 118 handles or the frame of special processing, stamp the heading that CPU 118 needs in the frame data front, wherein the heading information such as frame type, IP bag type, message length, port numbers that comprised message are given CPU 118 on again.
Separate frame processing unit 115: be used for the frame work of separating to link-layer frame.At receive direction, after the frame of receiving from asynchronous buffer interface 107 analyzed, to the frame data that need SCN Space Cable Network layer processing unit 104 to handle, as IPv6, IPv4 and MPLS frame etc., peel off frame head with extraction network layer message, and give network layer handles unit 104 by network layer interface 117 this network layer message.
Link layer DTU (Data Transfer unit) 103 of the present invention further includes:
Cpu i/f 116: mainly constitute, be used to realize that link layer DTU (Data Transfer unit) 103 and the data of CPU 118 transmit by dual port RAM.
Network layer interface 117: mainly constitute, be used to realize that the link layer DTU (Data Transfer unit) 103 and the data of network layer handles unit 104 transmit by dual port RAM.
Fig. 3 is the structure chart of link layer DTU (Data Transfer unit) at sending direction, and the frame among Fig. 1 sends processing unit 106 and comprises into frame processing unit 119 and wait for counter 120, wherein:
Become frame processing unit 119: be used for the data encapsulation that network layer handles unit 104 and/or CPU 118 send here is become frame data, send to physical layer processing unit 102 after being cached to described asynchronous buffer unit 108.Become frame processing unit 119 to be used for the sequential that the control frame data send, search link layer information, the structure link-layer frame.In the present embodiment, become frame processing unit 119 that 2 parts are arranged, respectively corresponding 2 IP FIFO---cpu i/f 116 and network layer interface 117, this two parts are sealed IP and are dressed up link-layer frame according to take out IP bag data and corresponding address information from IP FIFO, be buffered in again in the asynchronous buffer interface 108, and send to physical layer processing unit 102 through SPI-3 interface 110.
Wait for counter 120: it is subjected to the control of described one-tenth frame processing unit 119 and disposes threshold values.When described asynchronous buffer interface 108 to physical layer processing unit 102 transmit frame data and corresponding physical layer receiving port when causing stopping to receive owing to reasons such as obstructions, become frame processing unit 119 to trigger and wait for counter 120 countings, when count value exceeds described threshold values, wait for that counter 120 is used for realizing the sequencing control of discard processing, the drop mechanism that described one-tenth frame processing unit 119 bases preset carries out the discard processing of frame data, to prevent the congested of formation.In addition, wait for that the threshold values of counter 120 is to be provided with by register or counter by the user, concrete threshold values can be set according to pre-judgement and restriction to flow.It is bigger that threshold values is provided with, and can reduce packet loss, but the chance that port is stopped up is bigger.Can regulate the control of SPI-3 interface 110 buffering so more easily and then realize control flow.
Fig. 4 is the scheduling mechanism flow chart of the present invention at sending direction.Because the present invention has only a circuit-switched data etc. to be sent at receive direction, and on sending direction, owing to have two paths of data etc. to be sent, so sending direction should have a scheduling mechanism.
Step S401 is in wait state;
Step S402 when CPU has data to send, sends a request by cpu i/f to the link layer DTU (Data Transfer unit);
Step S403 judges whether cpu i/f is full, if execution in step S408 then, otherwise execution in step S404;
Step S404 carries out the write operation of dual port RAM, and the data (IP wraps data) that CPU is sended over write in the dual port RAM of cpu i/f;
Step S405 when the network layer handles unit has data to send, sends a request by network layer interface to the link layer DTU (Data Transfer unit);
Step S406 judges whether the dual port RAM of this network layer interface is full, if execution in step S407 then, otherwise execution in step S408;
Step S407 carries out the write operation of dual port RAM, and the data that the network layer handles unit is sended over write in the dual port RAM in the network layer interface;
Step S408: when the dual port RAM in cpu i/f or the network layer interface is expired, carry out discarded packets and handle,, turn back to step S401 after the packet loss in order to avoid cause the obstruction of link.
Fig. 5 is the schematic diagram of the present invention in sending direction packet loss mechanism.Wherein, on sending direction, the link layer conversion equipment sends to corresponding physical layer port with packaged frame data, if in the process of transmitting of a frame, but corresponding port is in accepting state all the time, and then this frame is understood the continuous corresponding port that sends to.If this port stops to receive when sending, then enter wait state, and packet loss processing by force after waiting for certain hour.
Step S501 on sending direction, if in the asynchronous buffer interface data are arranged, will send one and ask corresponding physical layer port clearly, and begin the inspection to the corresponding port state.If corresponding port is effective, execution in step S502 then, if corresponding port is invalid, execution in step S503.
Step S502, the asynchronous buffer interface generates the sequential of data-interface, and the data in the asynchronous buffer unit are sent to physical layer processing unit.If corresponding port is effective all the time, then carries out this step always and send until data and finish, in case otherwise port is invalid, execution in step S503 then.
Step S503 is counted by wait counter 306, if exceed count threshold, execution in step S504 in the process of counting; If surpassing threshold values and port, counting do not recover effectively then to continue execution in step S502; If surpass threshold values, invalid but port continues, then continue to carry out this step, effectively or exceed threshold values until port.
Step S504 when the count value of waiting for counter surpasses threshold values, deletes useless data.
Wherein, described port is meant that effectively port receives data enable; Port is invalid to be meant that port receives data and do not enable, and reason may be that port does not exist, closes or data are stopped up; The described threshold values that exceeds is meant when waiting for that the current count value of counter is greater than threshold values; The described threshold values that do not exceed is meant when waiting for that the current count value of counter is less than threshold values.
Fig. 6 is the structural representation of asynchronous buffer interface of the present invention, wherein:
The asynchronous buffer interface is one of topmost feature of the present invention, its also provide empty, full, with sky, will expire, predefine sky, various states index signal such as completely, wherein, predefine sky and predefine are full of the new improved part of the present invention, are realized by a comparator that can dispose.
Asynchronous buffer interface 601 (synchronous and asynchronous buffer cell 107 and 108) with write-back mechanism of the present invention is added the write address control circuit and reads the FIFO that address control circuit constitutes at skin by dual port RAM 605, dual port RAM 605 is as the kernel of asynchronous buffer interface 103, the user externally only need provide read-write, and do not need the direct control address, so, on the use aspect, seem to be equivalent to a FIFO.
Described write address control circuit includes:
FIFO write control unit 602 is used to finish the write operation logic of asynchronous buffer interface 601.
Write address control 606: be used for control signal (write signal) according to the outside and finish write operation to dual port RAM 605, directly current frame data is deleted in the increase of control address if desired, directly the address is pointed to next frame section start.
The described address control circuit of reading includes:
FIFO reads control unit 604: the read operation logic that has been used for asynchronous buffer interface 601.
Read address control 607: be used for control signal (read signal) and finish read operation to dual port RAM 605, the directly increase of control address according to the outside.
Asynchronous buffer interface 601 of the present invention also includes:
Subtracter 608: be used for calculating FIFO remaining space value with spatial value and FIFO gross space value according to the FIFO of described asynchronous buffer interface 601.Then, subtracter 608 sends to comparator 609 with described FIFO remaining space value.Wherein FIFO gross space value is notified to subtracter 608 by the asynchronous buffer interface, and described FIFO has used spatial value by the total depth of present dual port RAM 605 as can be known.
Comparator 609: be used to store fixed configurations and user configured some condition indicative signals and typical value thereof, and the FIFO remaining space value that described subtracter 608 is calculated and the typical value of described condition indicative signal compare, and draws the current state index signal.
Wherein, the condition indicative signal of fixed configurations comprises: empty, with sky, completely, will expire.For expire, will expire, empty, with the state of sky, be when FIFO remaining space value is respectively 0,1, the situation of total depth, total depth-1, the numerical value that promptly is equivalent to control register is the situation of fixing.And user configured condition indicative signal comprises: predefine is empty and predefine is full.Its numerical value by the user that predefine is full and the predefine sky is write comparator 609 in the mode of control register, the FIFO remaining space value of the dual port RAM 605 that comparator 609 obtains subtracter 608 register therewith compares, if numerical value greater than the predefine sky, so just think that asynchronous buffer interface 601 has entered the state that needs sky to alarm, with the pull-up of predefine spacing wave; If less than the full numerical value of predefine, so just think that asynchronous buffer interface 601 has entered the state of the full alarms of needs, with the full signal pull-up of predefine.And, will be full as the signal of current indicative signal, will expire or predefine is completely delivered to described write address control circuit realizing writing control, and as the signal sky of current indicative signal, sky or predefine sky are delivered to the described address control circuit of reading to realize reading control.
Adopt above-mentioned user configured predefine sky and predefine completely to wait the preliminary treatment option, overcome the very few shortcoming of common cell fifo state, and the signal of more expression state is provided in the data buffering process, make more perfect for the control of asynchronous buffer interface; Further, the system that makes can judge the full state of sky of FIFO in advance, thereby the preliminary treatment ability of raising system makes the user can only be concerned about the processing of exchanging network data, has simplified the realization of data product.
Described asynchronous buffer interface 601 is connected with frame processing unit 610, and this frame processing unit 610 carries out the analysis and the classification of frame data, and it comprises:
4 grades of shift registers 611: the link-layer frame head that obtains is assembled into the data of one 4 to 14 byte, and every grade of register is 32, needs 4 grades of registers at most;
Priority selector 612: generate the processing mode for present frame, control signal is exactly link layer informations such as frame type.
To sum up, the invention describes a kind of link layer data transfer device and device based on FPGA, with a kind of very simple method realized one, the double layer network interface, Layer 2 data transmits and two, the three-layer network interface.Realize easily because interface of the present invention is simple, can be applied in widely in the hardware repeater system based on FPGA or ASIC.
Certainly; the present invention also can have other various embodiments; under the situation that does not deviate from spirit of the present invention and essence thereof; those of ordinary skill in the art work as can make various corresponding changes and distortion according to the present invention, but these corresponding changes and distortion all should belong to the protection range of the appended claim of the present invention.
Claims (10)
1. data transfer device that is used for link layer comprises:
The frame data that physical layer processing unit is sent carry out data transaction; And/or
The data that the network layer handles unit is sent are carried out data transaction; It is characterized in that,
The step that the described frame data that physical layer processing unit is sent carry out data transaction comprises: the frame data that physical layer processing unit is sent are cached to the asynchronous buffer interface with write-back mechanism, and described frame data are carried out sending to after the conversion process network layer handles unit, described asynchronous buffer interface with write-back mechanism is added at skin by dual port RAM reads address control circuit and the write address control circuit is realized;
The step that the described data that the network layer handles unit is sent are carried out data transaction comprises: the data that the network layer handles unit is sent are carried out conversion process, and send to physical layer processing unit after will being cached to the asynchronous buffer interface with write-back mechanism through the frame data of conversion process gained;
The step that the described frame data that physical layer processing unit is sent carry out data transaction further comprises:
A, described asynchronous buffer interface will receive the frame data that come from physical layer processing unit and carry out data buffering and clock isolation;
B, the frame data of buffer memory are carried out the frame analysis and select handling;
C, send to CPU after going up information header for the frame data encapsulation that needs CPU to handle;
D, separate frame, generate the network layer message and send to the network layer handles unit for the frame data that need SCN Space Cable Network layer processing unit processes;
Described steps A further comprises:
A1, according to the gross space value of described asynchronous buffer interface and the usage space value calculate the remaining space value of asynchronous buffer interface;
A2, the typical value of the remaining space value of the asynchronous buffer interface that obtains in the steps A 1 and the some condition indicative signals that prestore is compared obtaining the current state index signal, described condition indicative signal comprises the sky of fixed configurations, with sky, completely, will expire and user configured predefine sky, predefine full;
A3, will as the current state index signal full, will expire or predefine is completely delivered to described write address control circuit to realize writing control;
A4, will be as the sky of current state index signal, sky or predefine sky are delivered to the described address control circuit of reading to realize reading control.
2. method according to claim 1 is characterized in that, described have the asynchronous buffer interface of write-back mechanism as the SPI-3 interface between physical layer and the link layer.
3. method according to claim 1 is characterized in that, only does data buffering and clock isolation processing with a described asynchronous buffer interface in the described steps A.
4. method according to claim 1 is characterized in that, the step that the described data that the network layer handles unit is sent are carried out data transaction further comprises:
E, handle, obtain sending to described asynchronous buffer interface behind the frame data and handle for carry out framing from the data of network layer handles unit;
F, handle, obtain sending to described asynchronous buffer interface behind the frame data and handle for carry out framing from the data of CPU;
G, described asynchronous buffer interface will send to physical layer processing unit again and handle after will carrying out data buffering and clock isolation through step e and/or the resulting frame data of step F.
5. method according to claim 4 is characterized in that, in the described step e processing from the data of network layer handles unit is further comprised:
E1, described network layer handles unit send data to the network layer interface request;
E2, judge whether this network layer interface is full, if execution in step E3 then, otherwise execution in step E4;
E3, carry out the data discard processing, and return wait state;
E4, the data that described network layer handles unit is sended over write network layer interface.
6. method according to claim 4 is characterized in that, in the described step F processing from the data of CPU is further comprised:
F1, described CPU send data to the cpu i/f request;
F2, judge whether this cpu i/f is full; If execution in step F3 then, otherwise execution in step F4;
F3, carry out the data discard processing, and return wait state;
F4, the data that described CPU is sended over write cpu i/f.
7. method according to claim 4 is characterized in that, the asynchronous buffer interface further comprises to the step of physical layer processing unit transmit frame data among the described step G:
G1, described asynchronous buffer interface are to corresponding physical layer receiving port request transmit frame data;
G2, continue to judge whether described corresponding physical layer receiving port is effective; If execution in step G3 then, otherwise execution in step G4;
G3, described asynchronous buffer interface are to corresponding physical layer receiving port transmit frame data;
G4, by waiting for that counter counts, and gained count value and the threshold values that presets are compared;
G5, judge that whether this count value surpasses threshold values, if, execution in step G6, otherwise return step G2;
G6, carry out the data discard processing.
8. a DTU (Data Transfer unit) that is used for link layer is characterized in that, comprises
Asynchronous buffer interface with write-back mechanism is used for the data buffering between physical layer processing unit and link layer process unit;
Frame receives processing unit: be used for the frame data of sending and be buffered in described asynchronous buffer interface from physical layer processing unit are carried out conversion process, and the data of conversion process gained are sent to the network layer handles unit;
Frame sends processing unit: the data that are used for the network layer handles unit is sent are carried out conversion process, and send to physical layer processing unit after will being cached to described asynchronous buffer interface through the frame data of conversion process gained;
Described frame receives processing unit and further comprises:
Frame analytic unit: be used for processing is analyzed and selected to the frame data that are buffered in described asynchronous buffer interface;
Information header processing unit: be used for information header is gone up in the frame data encapsulation of delivering the CPU processing from the needs of described frame analytic unit reception, and send to described CPU;
Separate frame processing unit: be used for the frame data of delivering the network layer handles cell processing from the needs of described frame analytic unit reception are separated frame, be sent to the network layer handles unit to generate the network layer message;
Described asynchronous buffer interface comprise dual port RAM with and outer add read address control circuit and write address control circuit;
Described asynchronous buffer interface further comprises:
Subtracter is used for the remaining space value of calculating the asynchronous buffer interface with spatial value and gross space value according to the asynchronous buffer interface;
Comparator, be used to store fixed configurations and user configured some condition indicative signals and typical value thereof, and the remaining space value and the described typical value of described asynchronous buffer interface compared, draw the current state index signal, should send to described write address control circuit to realize writing control by current condition indicative signal, perhaps send to the described address control circuit of reading to realize reading control;
The condition indicative signal of storing in the described comparator comprise fixed configurations sky, with sky, full, will expire and user configured predefine sky, predefine full; And will be full as the signal of current indicative signal, will expire or predefine is completely delivered to described write address control circuit, and the signal sky, sky or predefine sky are delivered to the described address control circuit of reading.
9. device according to claim 8 is characterized in that, described asynchronous buffer interface is as the SPI-3 interface between physical layer and the link layer.
10. device according to claim 8 is characterized in that, described frame sends processing unit and further comprises:
Become frame processing unit: be used for the data encapsulation that network layer handles unit and/or CPU send here is become frame data, send to physical layer processing unit after being cached to described asynchronous buffer unit with write-back mechanism;
Wait for counter, it is subjected to the control of described one-tenth frame processing unit and disposes threshold values;
When described asynchronous buffer interface to physical layer processing unit transmit frame data and corresponding physical layer receiving port when stopping to receive, become frame processing unit to trigger and wait for rolling counters forward, when count value exceeds described threshold values, described one-tenth frame processing unit carries out the discard processing of frame data according to the drop mechanism that presets.
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